Ryan Houdek 3df344a78d Fixes some asserts from vixl and a bug in ExitSpillSRA ...

Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.

Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location

2021-01-27 00:53:27 -08:00

..

Config

IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner

2021-01-21 21:38:41 +02:00

Context

IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner

2021-01-21 21:38:41 +02:00

Core

Fixes some asserts from vixl and a bug in ExitSpillSRA

2021-01-27 00:53:27 -08:00

HLE/Thunks

Moves FEXCore's SignalDelegator and SyscallHandler to the frontend

2020-12-13 22:38:04 -08:00

IR

Merge pull request #670 from FEX-Emu/skmp/faster-ra

2021-01-22 04:54:08 -08:00