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9,148 Commits 11 Branches 71 Tags
2b4ec88daebd35fefb5bf5c73d7fc2b4155771ed
Commit Graph
976 Commits
Author SHA1 Message Date
Paulo Matos 2b4ec88dae Whole-tree reformat 
This follows discussions from #3413.
Followup commits add clang-format file, script and blame ignore lists.
 2024-04-12 16:26:02 +02:00
Paulo Matos 6524716404 Move const to the left in preparation for reformatting 
clang-format-16 had some issues with const placement, so we are manually changing these.
 2024-04-12 16:06:57 +02:00
Ryan Houdek 271700e9f6 Merge pull request #3568 from lioncash/const 
X87: Simplify constant loading for FLD family
 2024-04-11 00:32:26 -07:00
Ryan Houdek 1ba678f631 Merge pull request #3562 from Sonicadvance1/fix_rsp_store_tso 
OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores
 2024-04-11 00:32:14 -07:00
Ryan Houdek a0f2cae1cb Merge pull request #3567 from lioncash/veczero 
IR: Remove VectorZero
 2024-04-09 20:04:26 -07:00
Ryan Houdek 66cbb66732 Merge pull request #3566 from lioncash/address 
OpcodeDispatcher: Add helper for making segment offset addresses
 2024-04-09 17:31:43 -07:00
Lioncache 4cb2432b5c OpcodeDispatcher: Make use of new x87 constants 
Now we can load these directly instead of needing to manually materialize them.
 2024-04-09 10:17:15 -04:00
Lioncache 65b5281d7c IR: Add constants for FLD variants 2024-04-09 10:13:33 -04:00
Ryan Houdek 1a8b61b9fc Merge pull request #3560 from bylaws/ec-pt6 
FEXCore: Support x64 -> arm64ec calls
 2024-04-09 07:08:38 -07:00
Ryan Houdek f0dad86332 Merge pull request #3559 from bylaws/ec-pt5 
LookupCache: Track ARM64EC page state in the code cache
 2024-04-09 07:08:29 -07:00
Mai eedb120fd0 Merge pull request #3563 from Sonicadvance1/fill_spill_pairs 
JIT: Adds support for spilling/Filling GPRPair
 2024-04-08 23:05:11 -04:00
Lioncache 98841fe07a IR: Remove VectorZero 
We have LoadNamedVectorConstant that now performs this behavior while
also being more flexible.
 2024-04-08 22:42:58 -04:00
Lioncache b0aeb501f4 OpcodeDispatcher: Add helper for making segment offset addresses 
There's quite a few places where the segment offset appending is open-coded
throughout the opcode dispatcher, but we can pull these out into a few
helpers to make the sites a little more compact and declarative.
 2024-04-08 17:50:58 -04:00
Lioncache b26bf2eaf6 DebugData: Remove header 
This isn't included or used anywhere, so it can be removed.
 2024-04-08 16:05:40 -04:00
Ryan Houdek 574fdcef32 JIT: Adds support for spilling/Filling GPRPair 
Tony noticed this last week. I encountered it this week.
Add support for spilling and filling GPR pairs.
 2024-04-08 11:55:29 -07:00
Ryan Houdek 0e93fd0f3e OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores 
GPR Direct/Indirect already had this and SIB version also already
supported on the load side. Fixes this missed behaviour.
 2024-04-08 11:32:01 -07:00
Alyssa Rosenzweig d9493e5d9b OpcodeDispatcher: fix xblock liveness in xsave/xrstr 
didn't fix this hard enough before. caught by validation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:48:29 -04:00
Alyssa Rosenzweig eb83c9e7f2 Core: use safe CondJump for self-modifying code 
this ensures we put the StoreNZCV in the right block, which will fix validation
fails later in the series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:48:29 -04:00
Billy Laws 526e3e654f LookupCache: Track ARM64EC page state in the code cache 
Rather than checking the actual EC bitmap in the dispatcher (~6 instrs), this
indirection through the code cache allows just 1 instr for the hot path
of calling repeated EC code/x64 code.
 2024-04-08 16:08:17 +01:00
Billy Laws 243bb45a68 FEXCore: Support x64 -> arm64ec calls 
The frontend will provide the return logic via ExitFunctionEC, which
will be jumped to whenever there is an indirect branch/return to an addr
such that RtlIsEcCode(addr) returns true.
 2024-04-06 13:20:48 +00:00
Alyssa Rosenzweig 95589f6172 OpcodeDispatcher: rm deferred variable shift flag calcs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 098859caf7 OpcodeDispatcher: use _ShiftFlags for ASHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig c632543451 OpcodeDispatcher: use _ShiftFlags for SHRD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 801cf72f95 OpcodeDispatcher: use _ShiftFlags for SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 650cd2c46e OpcodeDispatcher: use _ShiftFlags for SHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 5b48ce2228 OpcodeDispatcher: use _ShiftFlags for SHL 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 2173c26fd8 OpcodeDispatcher: add HandleShift helper 
all the variable shift impls need to do this dance, make it common.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 982391ba9d IR: add ShiftFlags op 
Generates flags for a variable shift as a dedicated IR op. This lets us optimize
around it (without generating control flow, relying on deferred flag infra,
etc). And it neatly solves our RA problem for shifts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 3661da1bc6 OpcodeDispatcher: calculate deferred flags before RMW on NZCV 
otherwise we might have the wrong input NZCV.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 859df5e0b2 OpcodeDispatcher: optimize shl flag 
This is something the new shift flag code will do. Backporting the opt since
that's stalled and this reduces the diff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 19:38:44 -04:00
Alyssa Rosenzweig a05cc06ab4 OpcodeDispatcher: unify imm/1-bit ASHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 031e756a78 OpcodeDispatcher: unify imm/1-bit SHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 2a9f1ce8cb OpcodeDispatcher: unify imm/1-bit SHL 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 8c53a9f051 OpcodeDispatcher: use LoadConstantShift for rotates 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig cf26ec7898 OpcodeDispatcher: use LoadConstantShift for SHRD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 582c3dae6e OpcodeDispatcher: use LoadConstantShift for SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 2abac03ab0 OpcodeDispatcher: add LoadConstantShift helper 
shows up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 8cc684fa12 OpcodeDispatcher: drop misinformed comment 
tbnz only tests a single bit, not a mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig d92de1d947 OpcodeDispatcher: drop result masking for shifts 
flag calcs are fine with upper garbage.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig 37f2b417e4 Merge pull request #3546 from alyssarosenzweig/flag/cleanup 
Minor cleanups around flags
 2024-04-02 11:29:19 -04:00
Alyssa Rosenzweig bd0b5eceb8 Merge pull request #3545 from alyssarosenzweig/opt/pf-scalar 
Use scalar integer code to calculate PF
 2024-04-02 11:28:53 -04:00
Alyssa Rosenzweig b632f7215c Merge pull request #3544 from alyssarosenzweig/ra/zero-multiple 
OpcodeDispatcher: drop ZeroMultipleFlags
 2024-04-02 11:27:45 -04:00
Ryan Houdek e8abc88702 Merge pull request #3542 from alyssarosenzweig/ra/rep 
Eliminate xblock liveness with rep cmp/lod/scas
 2024-04-02 04:24:24 -07:00
Ryan Houdek 29c6281e11 Merge pull request #3539 from alyssarosenzweig/ra/rol-ror2 
rewrite ROL/ROR
 2024-04-02 00:17:08 -07:00
Alyssa Rosenzweig 067a5444dc OpcodeDispatcher: use HandleNZ00Write 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Alyssa Rosenzweig c7f159972d OpcodeDispatcher: rm pointless NZCV loads 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Alyssa Rosenzweig a70d0a5dd4 OpcodeDispatcher: rm unnecessary NZCV dirtying 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Ryan Houdek cd9ffd2045 Merge pull request #3536 from alyssarosenzweig/ra/rcl-rcr 
OpcodeDispatcher: eliminate xblock liveness for rcl/rcr
 2024-04-01 11:44:37 -07:00
Alyssa Rosenzweig eb4bb5875e OpcodeDispatcher: absorb invert into PF calculation 
with xorn

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:33 -04:00
Alyssa Rosenzweig 3b052e826f OpcodeDispatcher: calculate PF with integer ops 
based on clang's __builtin_parity

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:32 -04:00