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IR: Add constants for FLD variants

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Lioncache committed 2024-04-09 10:13:33 -04:00
1 parent 1a8b61b9fc
commit 65b5281d7c
5 files changed
+26 -12
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FEXCore/Source/Interface/Core/CPUBackend.cpp
+6
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@@ -29,6 +29,12 @@ constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant:
{0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B
{0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB
{0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER
{0x8000'0000'0000'0000ULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_ONE
{0xD49A'784B'CD1B'8AFEULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_LOG2_10
{0xB8AA'3B29'5C17'F0BCULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_LOG2_E
{0xC90F'DAA2'2168'C235ULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_PI
{0x9A20'9A84'FBCF'F799ULL, 0x0000'0000'0000'3FFDULL}, // NAMED_VECTOR_X87_LOG10_2
{0xB172'17F7'D1CF'79ACULL, 0x0000'0000'0000'3FFEULL}, // NAMED_VECTOR_X87_LOG_2
};
constexpr static auto PSHUFLW_LUT {
FEXCore/include/FEXCore/IR/IR.h
+8
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@@ -59,6 +59,14 @@ enum NamedVectorConstant : uint8_t {
NAMED_VECTOR_BLENDPS_1110B,
NAMED_VECTOR_MOVMASKB,
NAMED_VECTOR_MOVMASKB_UPPER,
NAMED_VECTOR_X87_ONE,
NAMED_VECTOR_X87_LOG2_10,
NAMED_VECTOR_X87_LOG2_E,
NAMED_VECTOR_X87_PI,
NAMED_VECTOR_X87_LOG10_2,
NAMED_VECTOR_X87_LOG_2,
NAMED_VECTOR_CONST_POOL_MAX,
// Beginning of named constants that don't have a constant pool backing.
NAMED_VECTOR_ZERO = NAMED_VECTOR_CONST_POOL_MAX,
unittests/InstructionCountCI/FEXOpt/libnss.json
+3 -3
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@@ -197,10 +197,10 @@
"ldr q3, [x11, #272]",
"ldr q4, [x11]",
"ldr q5, [x11, #16]",
"ldr x0, [x28, #1712]",
"ldr x0, [x28, #1752]",
"ldr q6, [x0, #2832]",
"tbl v2.16b, {v2.16b}, v6.16b",
"ldr x0, [x28, #1712]",
"ldr x0, [x28, #1752]",
"ldr q7, [x0, #432]",
"tbl v3.16b, {v3.16b}, v7.16b",
"ldr q8, [x11, #32]",
@@ -281,7 +281,7 @@
"mov v9.s[2], w25",
"mov v9.s[1], w20",
"mov v9.s[0], w22",
"ldr x0, [x28, #1712]",
"ldr x0, [x28, #1752]",
"ldr q10, [x0, #224]",
"tbl v4.16b, {v4.16b}, v10.16b",
"mov w20, v9.s[1]",
unittests/InstructionCountCI/FlagM/VEX_map1.json
+1 -1
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@@ -72,7 +72,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2224]",
"ldr q2, [x28, #2272]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/Secondary.json
+8 -8
View File
@@ -646,7 +646,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2096]",
"ldr q3, [x28, #2144]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -657,7 +657,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2096]",
"ldr q3, [x28, #2144]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -1041,7 +1041,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr x0, [x28, #1696]",
"ldr x0, [x28, #1736]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #768]"
@@ -1052,7 +1052,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"ldr x0, [x28, #1696]",
"ldr x0, [x28, #1736]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #768]"
@@ -3306,7 +3306,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1720]",
"ldr x0, [x28, #1760]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
]
@@ -3315,7 +3315,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1720]",
"ldr x0, [x28, #1760]",
"ldr q2, [x0, #16]",
"mov v0.16b, v17.16b",
"mov v1.16b, v16.16b",
@@ -3327,7 +3327,7 @@
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #1720]",
"ldr x0, [x28, #1760]",
"ldr q3, [x0, #16]",
"mov v0.16b, v16.16b",
"mov v1.16b, v2.16b",
@@ -3425,7 +3425,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #2224]",
"ldr d3, [x28, #2272]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",