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68 Commits
Author SHA1 Message Date
Ryan Houdek 217bbf423b FEXCore: Switch constant emission to default to NoPad 
Most constants don't need to be padded for relocations. So now that
these have all been audited, switch to defaulting to NoPad to reduce
verbosity.

The number of constant that need to be explicitly padded are now marked
and with all the prior changes, this allows bisecting if something has
gone wrong.
 2025-12-29 11:45:51 -08:00
Ryan Houdek c2d5ee43c6 Passes/x87StackOptimizationPass: _Constant audit 2025-12-29 11:04:35 -08:00
Paulo Matos f91ac09f87 Set current code block in x87 pass 
This resets the constant pool in IREmit used by SelectAddressMode().

Fixes #5084.
 2025-12-02 15:33:08 +01:00
Paulo Matos 39dbf46422 Refactoring of storing code in x87 opt. stack pass 
Enables memcpy optimization of 80bit floats on reduced precision.

Also uncovered a bug where if we had done 80bit memcpy
optimization, we wouldn't have properly stored the 80bits.
This was caught by the existing tests when we enabled the optimization.
 2025-11-17 10:14:29 +01:00
Paulo Matos 6ee9984280 f80 stack xchg optimization for fast path 2025-11-05 11:20:02 +01:00
Paulo Matos 70b6bc2bae Remove InterpretAsFloat from x87StackOptimizationPass 
The InterpretAsFloat was never properly made use of. There's a couple of issues
that are fixed more easily with this gone, so lets remove it.

If there's a specific optimization that requires this, we can bring it back
at a later time. This should not have any effect on the current code generation.
 2025-10-28 11:26:28 +01:00
Paulo Matos eb1689e79f instcountci: Revert Fix quiet and signalling nan propagation 2025-10-16 09:11:01 +02:00
Paulo Matos bc6295a78d Revert "Fix quiet and signalling nan propagation" 
This reverts commit e7a47a647c.
 2025-10-16 08:53:44 +02:00
Lioncache c1cfd4db83 Addressing: Shave 8 bytes off AddressMode 
Just a trivial rearrangement, Drops the struct down to 40 bytes.
We can also make some functions take it by const reference so we
aren't churning some copies.

Before:
   text     data      bss      dec      hex  filename
4160559  1471360  4336824  9968743   981c67  Bin/FEX

After:
   text     data      bss      dec      hex  filename
4159927  1471360  4336824  9968111   9819ef  Bin/FEX
 2025-10-06 15:52:15 -04:00
Lioncache 0258e914e0 IR: Convert RegisterClassType to an enum class 
Removes the last of the wrapper value types in favor of enum classes.
 2025-10-03 03:54:56 -04:00
Lioncache fc63dcedb6 IR: Migrate to new helpers 
Reduces a bunch of noise related to the register classes and hoists them
out so that converting the classes over to enums should be fairly
straightforward.
 2025-10-03 00:53:02 -04:00
Lioncache f76e8c7185 IR: Convert MemOffsetType to enum class 
Gets rid of another wrapper struct.
 2025-10-02 00:24:42 -04:00
Lioncache 530821fc4a IR: Convert rounding modes to enum class 
Same behavior, but more compact
 2025-10-01 23:37:57 -04:00
Lioncache a798880ac8 IR: Convert CondClassType over to enum class 
Instead of having this sort of odd indirection through a struct type,
we can add support for defining custom enums in the IR description.

This lets us both get strong typing (and allow for weak typing, should
any enum in the future need it), without needing a struct for a basic
value type.

Even then, if we do need a struct for anything in the future, then
we still allow strong typing for values themselves while allowing
them to be used in various ways.
 2025-10-01 10:45:00 -04:00
Ryan Houdek e5680e031d Merge pull request #4835 from pmatos/fix/classify 
Fix quiet and signalling nan propagation
 2025-09-23 11:17:37 -07:00
Paulo Matos e7a47a647c Fix quiet and signalling nan propagation 
This adds a new mode X87StrictReducedPrecision.
The strict reduced precision is like the reduced precision but adds extra checks,
like the currently implemented nan and snan propagations.

Fix for __builtin_issignaling() test of SPEC2017 classify test.
 2025-09-23 13:48:45 +02:00
Paulo Matos 21e29af48b Remove unused IsZero; NFC 2025-09-22 14:22:14 +02:00
Billy Laws 6789919fca X87StackOptimization: Don't flush to mem when entering slow path 2025-09-09 21:29:12 +01:00
Billy Laws 6a1eb0e508 X87StackOptimization: Defer FTW valid bits calculation 2025-09-09 21:29:12 +01:00
Billy Laws 984b0260d5 X87StackOptimization: Cache stack values 2025-09-09 21:29:12 +01:00
Billy Laws 785e59e889 X87StackOptimization: Cache AbridgedFTW 2025-09-09 21:29:12 +01:00
Billy Laws 671be5b191 X87StackOptimization: Cache half-formed stack register context addresses 2025-09-09 21:29:12 +01:00
Billy Laws 2128943b57 X87StackOptimization: Use the x87 stack offset cache in SynchronizeStackValues 2025-09-09 21:29:12 +01:00
Billy Laws 6ddb1094b6 X87StackOptimization: Don't invalidate the x87 stack offset cache on push/pop 2025-09-09 21:29:12 +01:00
Billy Laws b9d93b19d4 X87StackOptimization: Defer writeback of the x87 stack pointer 2025-09-09 21:29:12 +01:00
Alyssa Rosenzweig f336261d6b IR: introduce & use more add helpers 
so we can stash all the opts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-08-06 20:40:49 -04:00
Ryan Houdek 14c1ee10b6 x87StackOptimizationPass: Removes pair usage 
NFC
 2025-07-28 16:14:49 -07:00
Ryan Houdek 6ebbd91245 JIT: Optimize x87 FSINCOS 
Turns out Bayonetta hammers SINCOS, our splitting the operation is
actually harming the performance of games that heavily use FSINCOS. We
instead can actually combine the operation which improves performance.
Not enough to get the game running full speed consistently on my Radxa,
but good numbers in my microbenchmark.

```
Test, Total Cycles, Total Runs, Cycles Average, Internal Loops, Average cycles per internal, per/second

64-bit:
Before:
FSIN, 2691031290, 50000, 53820.6, 1000, 53.8206, 18580.237319
FCOS, 2719397120, 50000, 54387.9, 1000, 54.3879, 18386.428239
FSINCOS, 5586917530, 50000, 111738, 1000, 111.738, 8949.478801

After:
FSIN, 2669959250, 50000, 53399.2, 1000, 53.3992, 18726.877573
FCOS, 2740942260, 50000, 54818.8, 1000, 54.8188, 18241.901965
FSINCOS, 3189472870, 50000, 63789.5, 1000, 63.7895, 15676.571659

80-bit:
Before:
FSIN, 24702939380, 50000, 494059, 1000, 494.059, 2024.050629
FCOS, 19127131020, 50000, 382543, 1000, 382.543, 2614.087808
FSINCOS, 40386785260, 50000, 807736, 1000, 807.736, 1238.028719

After:
FSIN, 24869980710, 50000, 497400, 1000, 497.4, 2010.455922
FCOS, 19131849590, 50000, 382637, 1000, 382.637, 2613.443084
FSINCOS, 38329985570, 50000, 766600, 1000, 766.6, 1304.461749

Improvement 64-bit: 1.75x
Improvement 80-bit: 1.05x
```

Only a minor improvement at 80-bit precision since cephes doesn't provide a combined sincos operation, but the f64 implementation is significantly improved, allowing 75% more operations per second.

Disabled in the simulator because we can't easily support pairs of
vector registers being returned.
 2025-07-03 18:05:51 -07:00
Ryan Houdek cebcf50c65 x87OptimizationPass: Fixes {Inc,Dec}StackPop 
On the slow path these were pushing and popping in the wrong direction.
Switch them around to ensure the unittests work.
 2025-04-02 14:25:02 -07:00
Ryan Houdek feab0bce4b x87StackOptimizationPass: Initialize a couple of arrays 
Just to silence some warnings that think these aren't zero initialized
before using.
 2025-03-29 14:02:46 -07:00
Paulo Matos 4565f2b689 Initialize class fields to null/zero 
Silence a couple of static analyzer warnings.
 2025-03-27 15:35:40 +01:00
Paulo Matos b18f148575 Abstract AddressMode into its own header 
Also refactor usage of utility functions into x87 Stack Optimization Pass.
 2025-03-20 11:41:26 +01:00
Paulo Matos e18a661b50 Refactor OP_STORESTACKMEM case in x87 Stack Opt Pass 2025-03-18 18:34:06 +01:00
Ryan Houdek 031afbfb18 Various: Adds missing SPDX file headers 
NFC
 2025-03-07 11:34:31 -08:00
Paulo Matos 0bccb1ece5 Ensure predicate cache is reset when control flow leaves block 
Whenever the control float leaves the block, it might clobber the
predicate register so we reset the cache whenever that happens.

Fixes #4264
 2025-01-27 20:12:43 +01:00
Tony Wasserka e54b9237c6 Drop use of assume-asserting logging macros 2025-01-21 12:01:33 +01:00
Paulo Matos 2d53867668 x87 fst/fld optimization for different addrmodes 
Includes tests and instcountci files and tests.
When the x87 optimizations were implement, we missed
optimizing different addressing modes. This commit addresses this issue.

Discussed in #4252.
 2025-01-14 16:20:33 +01:00
Paulo Matos cbda688e29 Revert "Cache predicate register generation from pattern" 
This reverts commit 72a4063651.

Caused #4264
 2025-01-10 12:52:11 +01:00
Ryan Houdek a47ed105e7 x87StackOptimizationPass: Minor opt to f80 fchs and fabs 
It's faster to load the f80 sign mask from our named vector constants
than synthesizing the values. Changes a 4 instruction sequence to
synthesize to be 1 load.
 2025-01-03 13:47:10 -08:00
Paulo Matos 72a4063651 Cache predicate register generation from pattern 2024-12-06 10:15:38 +01:00
Paulo Matos 1d3ce30e50 Generate SVE for 80bit load/stores when possible 
Fixes #4166.
 2024-12-06 10:15:29 +01:00
Ryan Houdek 9b6cc8f7e0 IR: Convert OpSize over to enum class 
NFC

Do the final mopping up to convert the OpSize enum to an enum class!
 2024-10-29 16:52:16 -07:00
Ryan Houdek 034b62292b Passes/x86StackOptimization: Fixes implicit conversion of OpSize 2024-10-28 19:26:02 -07:00
Ryan Houdek 2dd0a82059 IR: Change F80CVTTo to use IR::OpSize 2024-10-28 02:23:47 -07:00
Ryan Houdek eccfb53bd5 IR: Change StoreStackMemory to use IR::OpSize 2024-10-28 02:01:47 -07:00
Ryan Houdek 44f9df062e IR: Change Vector_FToI to use IR::OpSize 2024-10-28 01:50:23 -07:00
Ryan Houdek 30317ac979 IR: Change Float_FToF to use IR::OpSize 2024-10-28 01:22:45 -07:00
Ryan Houdek 65439956bf IR: Change VCastFromGPR to use IR::OpSize 2024-10-28 01:18:21 -07:00
Ryan Houdek 4e21177988 IR: Change VBSL to use IR::OpSize 2024-10-28 01:13:53 -07:00
Ryan Houdek 365d8b9508 IR: Change VInsGPR to use IR::OpSize 2024-10-28 01:07:16 -07:00