Merge pull request #3120 from Sonicadvance1/more_optimal_x87

FEXCore: Support preserve_all ABI for interpreter fallbacks

FEXCore/CMakeLists.txt

@@ -33,6 +33,22 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
 
 include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
+include(CheckCXXSourceCompiles)
+
+set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
+check_cxx_source_compiles(
+  "
+  __attribute__((preserve_all))
+  void Testy() {
+  }
+  int main() {
+  return 0;
+  }"
+  HAS_CLANG_PRESERVE_ALL)
+unset(CMAKE_REQUIRED_FLAGS)
+if (HAS_CLANG_PRESERVE_ALL)
+  message(STATUS "Has clang::preserve_all")
+endif ()
 
 if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
     # Useful to have for freestanding libFEXCore

FEXCore/Source/CMakeLists.txt

@@ -214,6 +214,15 @@ if (ENABLE_JIT_ARM64)
     )
 endif()
 
+if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+  list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1")
+else()
+  list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=;-DFEXCORE_HAS_PRESERVE_ALL_ATTR=0")
+endif()
+
+# Some defines for the softfloat library
+list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ")
+
 set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils)
 
 if (NOT MINGW_BUILD)

FEXCore/Source/Common/SoftFloat-3e/extF80_add.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_div.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_eq( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_lt( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sqrt( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float128_t extF80_to_f128( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t extF80_to_f32( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t extF80_to_f64( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
  extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
  extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t
  extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f128_to_extF80( float128_t a )
 {
     union ui128_f128 uA;

FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f32_to_extF80( float32_t a )
 {
     union ui32_f32 uA;

FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f64_to_extF80( float64_t a )
 {
     union ui64_f64 uA;

FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t i32_to_extF80( int32_t a )
 {
     uint_fast16_t uiZ64;

FEXCore/Source/Common/SoftFloat-3e/internals.h

@@ -68,9 +68,11 @@ uint_fast64_t
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
  softfloat_roundToI64(
      bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
@@ -109,8 +111,10 @@ float16_t
 #define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
 
 struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
 float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );
 
@@ -130,8 +134,10 @@ float32_t
 #define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
 
 struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
 float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );
 
@@ -155,11 +161,14 @@ float64_t
 *----------------------------------------------------------------------------*/
 
 struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_roundPackToExtF80(
      bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_normRoundPackToExtF80(
      bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
@@ -181,6 +190,7 @@ extFloat80_t
 #define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
 
 struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig128
  softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
 

FEXCore/Source/Common/SoftFloat-3e/primitives.h

@@ -53,6 +53,7 @@ INLINE
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
     { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 #endif
 #endif
@@ -74,6 +75,7 @@ INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
         (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
 #endif
 #endif
@@ -95,6 +97,7 @@ INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
         (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
 #endif
 #endif
@@ -148,6 +151,7 @@ INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
     return count;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
 #endif
 #endif
@@ -157,6 +161,7 @@ uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
 | Returns the number of leading 0 bits before the most-significant 1 bit of
 | 'a'.  If 'a' is zero, 64 is returned.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros64( uint64_t a );
 #endif
 
@@ -178,6 +183,7 @@ extern const uint16_t softfloat_approxRecip_1k1s[16];
 #ifdef SOFTFLOAT_FAST_DIV64TO32
 #define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a)))
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecip32_1( uint32_t a );
 #endif
 #endif
@@ -204,6 +210,7 @@ extern const uint16_t softfloat_approxRecipSqrt_1k1s[16];
 | returned is also always within the range 0.5 to 1; thus, the most-
 | significant bit of the result is always set.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
 #endif
 
@@ -240,6 +247,7 @@ INLINE
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
     { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
@@ -255,6 +263,7 @@ INLINE
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
     { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
@@ -275,6 +284,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
@@ -296,6 +306,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
@@ -413,6 +424,7 @@ struct uint64_extra
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint64_extra
  softfloat_shiftRightJam64Extra(
      uint64_t a, uint64_t extra, uint_fast32_t dist );
@@ -492,6 +504,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -528,6 +541,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -562,6 +576,7 @@ INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
 #endif
 #endif
@@ -570,6 +585,7 @@ struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
 /*----------------------------------------------------------------------------
 | Returns the 128-bit product of 'a' and 'b'.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
 #endif
 

FEXCore/Source/Common/SoftFloat-3e/s_add128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_add128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
 {

FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 extern const uint16_t softfloat_approxRecip_1k0s[16];
 extern const uint16_t softfloat_approxRecip_1k1s[16];
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecip32_1( uint32_t a )
 {
     int index;

FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 extern const uint16_t softfloat_approxRecipSqrt_1k0s[];
 extern const uint16_t softfloat_approxRecipSqrt_1k1s[];
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a )
 {
     int index;

FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c

@@ -44,6 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;

FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF128UI.c

@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;

FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF32UI.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF64UI.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros32.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 #include "primitives.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
 {
     uint_fast8_t count;

FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros64.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 #include "primitives.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
 {
     uint_fast8_t count;

FEXCore/Source/Common/SoftFloat-3e/s_extF80UIToCommonNaN.c

@@ -46,6 +46,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void
  softfloat_extF80UIToCommonNaN(
      uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )

FEXCore/Source/Common/SoftFloat-3e/s_f128UIToCommonNaN.c

@@ -47,6 +47,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void
  softfloat_f128UIToCommonNaN(
      uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )

FEXCore/Source/Common/SoftFloat-3e/s_f32UIToCommonNaN.c

@@ -45,6 +45,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_f64UIToCommonNaN.c

@@ -45,6 +45,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_le128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_le128
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_lt128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_lt128
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_mul64ByShifted32To128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_mul64ByShifted32To128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
 {
     uint_fast64_t mid;

FEXCore/Source/Common/SoftFloat-3e/s_mul64To128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_mul64To128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
 {
     uint32_t a32, a0, b32, b0;

FEXCore/Source/Common/SoftFloat-3e/s_normRoundPackToExtF80.c

@@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "platform.h"
 #include "internals.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_normRoundPackToExtF80(
      bool sign,

FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalExtF80Sig.c

@@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "platform.h"
 #include "internals.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t sig )
 {
     int_fast8_t shiftDist;

FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF128Sig.c

@@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "platform.h"
 #include "internals.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig128
  softfloat_normSubnormalF128Sig( uint_fast64_t sig64, uint_fast64_t sig0 )
 {

FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF32Sig.c

@@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "platform.h"
 #include "internals.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig )
 {
     int_fast8_t shiftDist;

FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF64Sig.c

@@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "platform.h"
 #include "internals.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig )
 {
     int_fast8_t shiftDist;

FEXCore/Source/Common/SoftFloat-3e/s_propagateNaNExtF80UI.c

@@ -50,6 +50,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_propagateNaNExtF80UI(
      uint_fast16_t uiA64,

FEXCore/Source/Common/SoftFloat-3e/s_roundPackToExtF80.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_roundPackToExtF80(
      bool sign,

FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF32.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t
  softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
 {

FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF64.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t
  softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
 {

FEXCore/Source/Common/SoftFloat-3e/s_roundToI32.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
  softfloat_roundToI32(
      bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )

FEXCore/Source/Common/SoftFloat-3e/s_roundToI64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
  softfloat_roundToI64(
      bool sign,

FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam32.c

@@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shiftRightJam32
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64.c

@@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shiftRightJam64
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64Extra.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shiftRightJam64Extra
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint64_extra
  softfloat_shiftRightJam64Extra(
      uint64_t a, uint64_t extra, uint_fast32_t dist )

FEXCore/Source/Common/SoftFloat-3e/s_shortShiftLeft128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shortShiftLeft128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
 {

FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRight128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shortShiftRight128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
 {

FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRightJam64.c

@@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_shortShiftRightJam64
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
 {
 

FEXCore/Source/Common/SoftFloat-3e/s_sub128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_sub128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
 {

FEXCore/Source/Common/SoftFloat-3e/softfloat.h

@@ -92,6 +92,7 @@ enum {
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_raiseFlags( uint_fast8_t );
 
 /*----------------------------------------------------------------------------
@@ -110,6 +111,7 @@ float16_t ui64_to_f16( uint64_t );
 float32_t ui64_to_f32( uint64_t );
 float64_t ui64_to_f64( uint64_t );
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t ui64_to_extF80( uint64_t );
 float128_t ui64_to_f128( uint64_t );
 #endif
@@ -119,6 +121,7 @@ float16_t i32_to_f16( int32_t );
 float32_t i32_to_f32( int32_t );
 float64_t i32_to_f64( int32_t );
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t i32_to_extF80( int32_t );
 float128_t i32_to_f128( int32_t );
 #endif
@@ -183,6 +186,7 @@ int_fast64_t f32_to_i64_r_minMag( float32_t, bool );
 float16_t f32_to_f16( float32_t );
 float64_t f32_to_f64( float32_t );
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f32_to_extF80( float32_t );
 float128_t f32_to_f128( float32_t );
 #endif
@@ -218,6 +222,7 @@ int_fast64_t f64_to_i64_r_minMag( float64_t, bool );
 float16_t f64_to_f16( float64_t );
 float32_t f64_to_f32( float64_t );
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f64_to_extF80( float64_t );
 float128_t f64_to_f128( float64_t );
 #endif
@@ -250,26 +255,41 @@ extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision;
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_INT64
 uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool );
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool );
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool );
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool );
 uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool );
 uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool );
 int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool );
 int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool );
 float16_t extF80_to_f16( extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t extF80_to_f32( extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t extF80_to_f64( extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 float128_t extF80_to_f128( extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_add( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sub( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_mul( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_div( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_rem( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sqrt( extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_eq( extFloat80_t, extFloat80_t );
 bool extF80_le( extFloat80_t, extFloat80_t );
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_lt( extFloat80_t, extFloat80_t );
 bool extF80_eq_signaling( extFloat80_t, extFloat80_t );
 bool extF80_le_quiet( extFloat80_t, extFloat80_t );
@@ -320,6 +340,7 @@ int_fast64_t f128_to_i64_r_minMag( float128_t, bool );
 float16_t f128_to_f16( float128_t );
 float32_t f128_to_f32( float128_t );
 float64_t f128_to_f64( float128_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f128_to_extF80( float128_t );
 float128_t f128_roundToInt( float128_t, uint_fast8_t, bool );
 float128_t f128_add( float128_t, float128_t );

FEXCore/Source/Common/SoftFloat-3e/softfloat_raiseFlags.c

@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | to substitute a result value.  If traps are not implemented, this routine
 | should be simply `softfloat_exceptionFlags |= flags;'.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_raiseFlags( uint_fast8_t flags )
 {
 

FEXCore/Source/Common/SoftFloat-3e/specialize.h

@@ -135,12 +135,14 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
@@ -170,12 +172,14 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
@@ -215,6 +219,7 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void
  softfloat_extF80UIToCommonNaN(
      uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
@@ -224,6 +229,7 @@ void
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 
 /*----------------------------------------------------------------------------
@@ -235,6 +241,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_propagateNaNExtF80UI(
      uint_fast16_t uiA64,
@@ -264,6 +271,7 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 void
  softfloat_f128UIToCommonNaN(
      uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
@@ -272,6 +280,7 @@ void
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 
 /*----------------------------------------------------------------------------

FEXCore/Source/Common/SoftFloat-3e/ui64_to_extF80.c

@@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t ui64_to_extF80( uint64_t a )
 {
     uint_fast16_t uiZ64;

FEXCore/Source/Common/SoftFloat.h

@@ -63,6 +63,7 @@ struct FEX_PACKED X80SoftFloat {
   }
 
   // Ops
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FADD(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #ifdef DEBUG_X86_FLOAT
     BIGFLOAT Result;
@@ -84,6 +85,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FSUB(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #ifdef DEBUG_X86_FLOAT
     BIGFLOAT Result;
@@ -105,6 +107,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FMUL(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #ifdef DEBUG_X86_FLOAT
     BIGFLOAT Result;
@@ -126,6 +129,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FDIV(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #ifdef DEBUG_X86_FLOAT
     BIGFLOAT Result;
@@ -147,6 +151,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FREM(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #if defined(DEBUG_X86_FLOAT)
     BIGFLOAT Result;
@@ -169,6 +174,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FREM1(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
 #if defined(DEBUG_X86_FLOAT)
     BIGFLOAT Result;
@@ -191,14 +197,17 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) {
     return extF80_roundToInt(lhs, softfloat_roundingMode, false);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FRNDINT(X80SoftFloat const &lhs, uint_fast8_t RoundMode) {
     return extF80_roundToInt(lhs, RoundMode, false);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) {
 #if defined(DEBUG_X86_FLOAT)
     BIGFLOAT Result;
@@ -222,6 +231,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FXTRACT_EXP(X80SoftFloat const &lhs) {
 #if defined(DEBUG_X86_FLOAT)
     BIGFLOAT Result;
@@ -243,12 +253,14 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static void FCMP(X80SoftFloat const &lhs, X80SoftFloat const &rhs, bool *eq, bool *lt, bool *nan) {
     *eq = extF80_eq(lhs, rhs);
     *lt = extF80_lt(lhs, rhs);
     *nan = IsNan(lhs) || IsNan(rhs);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FSCALE(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
     WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -277,6 +289,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat F2XM1(X80SoftFloat const &lhs) {
     WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -300,6 +313,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FYL2X(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
     WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -325,6 +339,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FATAN(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
     WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -350,6 +365,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FTAN(X80SoftFloat const &lhs) {
     WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -373,6 +389,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FSIN(X80SoftFloat const &lhs) {
     WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -395,6 +412,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FCOS(X80SoftFloat const &lhs) {
     WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
@@ -417,6 +435,7 @@ struct FEX_PACKED X80SoftFloat {
 #endif
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat FSQRT(X80SoftFloat const &lhs) {
 #ifdef DEBUG_X86_FLOAT
     BIGFLOAT Result;

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -2,6 +2,7 @@
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Context/Context.h"
 #include "Interface/HLE/Thunks/Thunks.h"
@@ -79,6 +80,97 @@ namespace x64 {
     FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
     FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
   };
+
+  // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15.
+  // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI.
+  constexpr std::array<FEXCore::ARMEmitter::Register, 7> PreserveAll_SRA = {
+    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+    FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+    FEXCore::ARMEmitter::Reg::r8,
+    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+  };
+
+  constexpr uint32_t PreserveAll_SRAMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRA) {
+        switch (Reg.Idx()) {
+          case 0:
+          case 1:
+          case 2:
+          case 3:
+          case 4:
+          case 5:
+          case 6:
+          case 7:
+          case 8:
+          case 16:
+          case 17:
+            Mask |= (1U << Reg.Idx());
+            break;
+          default: break;
+        }
+      }
+
+      return Mask;
+    }()
+  };
+
+  // Dynamic GPRs
+  constexpr std::array<FEXCore::ARMEmitter::Register, 1> PreserveAll_Dynamic = {
+    // Only LR needs to get saved.
+    FEXCore::ARMEmitter::Reg::r30
+  };
+
+  // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI.
+  constexpr std::array<FEXCore::ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
+    // None.
+  };
+
+  constexpr uint32_t PreserveAll_SRAFPRMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRAFPR) {
+        Mask |= (1U << Reg.Idx());
+      }
+      return Mask;
+    }()
+  };
+
+  // Dynamic FPRs
+  // - v0-v7
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
+    // v0 ~ v1 are temps
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+  };
+
+  // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI.
+  // This is /all/ of the SRA registers
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> PreserveAll_SRAFPRSVE = SRAFPR;
+
+  constexpr uint32_t PreserveAll_SRAFPRSVEMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRAFPRSVE) {
+        Mask |= (1U << Reg.Idx());
+      }
+      return Mask;
+    }()
+  };
+
+  // Dynamic FPRs when the host supports SVE-256bit.
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> PreserveAll_DynamicFPRSVE = {
+    // v0 ~ v1 are used as temps.
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+  };
 }
 
 namespace x32 {
@@ -145,6 +237,101 @@ namespace x32 {
     FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
     FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
   };
+
+  // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15.
+  // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI.
+  constexpr std::array<FEXCore::ARMEmitter::Register, 5> PreserveAll_SRA = {
+    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+    FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+    FEXCore::ARMEmitter::Reg::r8,
+  };
+
+  constexpr uint32_t PreserveAll_SRAMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRA) {
+        switch (Reg.Idx()) {
+          case 0:
+          case 1:
+          case 2:
+          case 3:
+          case 4:
+          case 5:
+          case 6:
+          case 7:
+          case 8:
+          case 16:
+          case 17:
+            Mask |= (1U << Reg.Idx());
+            break;
+          default: break;
+        }
+      }
+
+      return Mask;
+    }()
+  };
+
+  // Dynamic GPRs
+  constexpr std::array<FEXCore::ARMEmitter::Register, 3> PreserveAll_Dynamic = {
+    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+    FEXCore::ARMEmitter::Reg::r30
+  };
+
+  // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI.
+  constexpr std::array<FEXCore::ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
+    // None.
+  };
+
+  constexpr uint32_t PreserveAll_SRAFPRMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRAFPR) {
+        Mask |= (1U << Reg.Idx());
+      }
+      return Mask;
+    }()
+  };
+
+  // Dynamic FPRs
+  // - v0-v7
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
+    // v0 ~ v1 are temps
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+  };
+
+  // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI.
+  // This is /all/ of the SRA registers
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 8> PreserveAll_SRAFPRSVE = SRAFPR;
+
+  constexpr uint32_t PreserveAll_SRAFPRSVEMask = {
+    []() -> uint32_t {
+      uint32_t Mask{};
+      for (auto Reg : PreserveAll_SRAFPRSVE) {
+        Mask |= (1U << Reg.Idx());
+      }
+      return Mask;
+    }()
+  };
+
+  // Dynamic FPRs when the host supports SVE-256bit.
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 22> PreserveAll_DynamicFPRSVE = {
+    // v0 ~ v1 are used as temps.
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+
+    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+    FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+    FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
+  };
 }
 
 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
@@ -533,6 +720,107 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
   }
 }
 
+void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs) {
+  if (SVERegs) {
+    size_t i = 0;
+
+    for (; i < (VRegs.size() % 4); i += 2) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0);
+      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2);
+    }
+
+    for (; i < VRegs.size(); i += 4) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      const auto Reg3 = VRegs[i + 2];
+      const auto Reg4 = VRegs[i + 3];
+      st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0);
+      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
+    }
+  }
+  else {
+    size_t i = 0;
+    for (; i < (VRegs.size() % 4); i += 2) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), TmpReg, 32);
+    }
+
+    for (; i < VRegs.size(); i += 4) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      const auto Reg3 = VRegs[i + 2];
+      const auto Reg4 = VRegs[i + 3];
+      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
+    }
+  }
+}
+
+void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span<const FEXCore::ARMEmitter::Register> Regs) {
+  size_t i = 0;
+  for (; i < (Regs.size() % 2); ++i) {
+    const auto Reg1 = Regs[i];
+    str<ARMEmitter::IndexType::POST>(Reg1.X(), TmpReg, 16);
+  }
+
+  for (; i < Regs.size(); i += 2) {
+    const auto Reg1 = Regs[i];
+    const auto Reg2 = Regs[i + 1];
+    stp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), TmpReg, 16);
+  }
+}
+
+void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs) {
+  if (SVERegs) {
+    size_t i = 0;
+    for (; i < (VRegs.size() % 4); i += 2) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2);
+    }
+
+    for (; i < VRegs.size(); i += 4) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      const auto Reg3 = VRegs[i + 2];
+      const auto Reg4 = VRegs[i + 3];
+      ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
+    }
+  } else {
+    size_t i = 0;
+    for (; i < (VRegs.size() % 4); i += 2) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32);
+    }
+
+    for (; i < VRegs.size(); i += 4) {
+      const auto Reg1 = VRegs[i];
+      const auto Reg2 = VRegs[i + 1];
+      const auto Reg3 = VRegs[i + 2];
+      const auto Reg4 = VRegs[i + 3];
+      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64);
+    }
+  }
+}
+
+void Arm64Emitter::PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Register> Regs) {
+  size_t i = 0;
+  for (; i < (Regs.size() % 2); ++i) {
+    const auto Reg1 = Regs[i];
+    ldr<ARMEmitter::IndexType::POST>(Reg1.X(), ARMEmitter::Reg::rsp, 16);
+  }
+  for (; i < Regs.size(); i += 2) {
+    const auto Reg1 = Regs[i];
+    const auto Reg2 = Regs[i + 1];
+    ldp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16);
+  }
+}
+
 void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
   const auto GPRSize = (ConfiguredDynamicRegisterBase.size() + 1) * Core::CPUState::GPR_REG_SIZE;
@@ -548,46 +836,11 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
 
   LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 2 == 0, "Needs to have multiple of 2 FPRs for RA");
 
-  if (CanUseSVE) {
-    size_t i = 0;
+  // Push the vector registers
+  PushVectorRegisters(TmpReg, CanUseSVE, GeneralFPRegisters);
 
-    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0);
-      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2);
-    }
-
-    for (; i < GeneralFPRegisters.size(); i += 4) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      const auto Reg3 = GeneralFPRegisters[i + 2];
-      const auto Reg4 = GeneralFPRegisters[i + 3];
-      st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0);
-      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
-    }
-  } else {
-    size_t i = 0;
-    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), TmpReg, 32);
-    }
-
-    for (; i < GeneralFPRegisters.size(); i += 4) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      const auto Reg3 = GeneralFPRegisters[i + 2];
-      const auto Reg4 = GeneralFPRegisters[i + 3];
-      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
-    }
-  }
-
-  for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) {
-    const auto Reg1 = ConfiguredDynamicRegisterBase[i];
-    const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
-    stp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), TmpReg, 16);
-  }
+  // Push the general registers.
+  PushGeneralRegisters(TmpReg, ConfiguredDynamicRegisterBase);
 
   str(ARMEmitter::XReg::lr, TmpReg, 0);
 }
@@ -595,49 +848,107 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
 void Arm64Emitter::PopDynamicRegsAndLR() {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
 
-  if (CanUseSVE) {
-    size_t i = 0;
-    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2);
-    }
+  // Pop vectors first
+  PopVectorRegisters(CanUseSVE, GeneralFPRegisters);
 
-    for (; i < GeneralFPRegisters.size(); i += 4) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      const auto Reg3 = GeneralFPRegisters[i + 2];
-      const auto Reg4 = GeneralFPRegisters[i + 3];
-      ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
-    }
-  } else {
-    size_t i = 0;
-    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32);
-    }
-
-    for (; i < GeneralFPRegisters.size(); i += 4) {
-      const auto Reg1 = GeneralFPRegisters[i];
-      const auto Reg2 = GeneralFPRegisters[i + 1];
-      const auto Reg3 = GeneralFPRegisters[i + 2];
-      const auto Reg4 = GeneralFPRegisters[i + 3];
-      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64);
-    }
-  }
-
-  for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) {
-    const auto Reg1 = ConfiguredDynamicRegisterBase[i];
-    const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
-    ldp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16);
-  }
+  // Pop GPRs second
+  PopGeneralRegisters(ConfiguredDynamicRegisterBase);
 
   ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
 }
 
+void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs) {
+  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
+  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
+                                    : Core::CPUState::XMM_SSE_REG_SIZE;
+
+  std::span<const FEXCore::ARMEmitter::Register> DynamicGPRs{};
+  std::span<const FEXCore::ARMEmitter::VRegister> DynamicFPRs{};
+  uint32_t PreserveSRAMask{};
+  uint32_t PreserveSRAFPRMask{};
+  if (EmitterCTX->Config.Is64BitMode()) {
+    DynamicGPRs = x64::PreserveAll_Dynamic;
+    DynamicFPRs = x64::PreserveAll_DynamicFPR;
+    PreserveSRAMask = x64::PreserveAll_SRAMask;
+    PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask;
+
+    if (CanUseSVE) {
+      DynamicFPRs = x64::PreserveAll_DynamicFPRSVE;
+      PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask;
+    }
+  }
+  else {
+    DynamicGPRs = x32::PreserveAll_Dynamic;
+    DynamicFPRs = x32::PreserveAll_DynamicFPR;
+    PreserveSRAMask = x32::PreserveAll_SRAMask;
+    PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask;
+
+    if (CanUseSVE) {
+      DynamicFPRs = x32::PreserveAll_DynamicFPRSVE;
+      PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask;
+    }
+  }
+
+  const auto GPRSize = AlignUp(DynamicGPRs.size(), 2) * Core::CPUState::GPR_REG_SIZE;
+  const auto FPRSize = DynamicFPRs.size() * FPRRegSize;
+  const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
+
+  // Spill the static registers.
+  SpillStaticRegs(TmpReg, true, PreserveSRAMask, PreserveSRAFPRMask);
+
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset);
+
+  // rsp capable move
+  add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);
+
+  // Push the vector registers.
+  PushVectorRegisters(TmpReg, CanUseSVE, DynamicFPRs);
+
+  // Push the general registers.
+  PushGeneralRegisters(TmpReg, DynamicGPRs);
+}
+
+void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
+  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
+
+  std::span<const FEXCore::ARMEmitter::Register> DynamicGPRs{};
+  std::span<const FEXCore::ARMEmitter::VRegister> DynamicFPRs{};
+  uint32_t PreserveSRAMask{};
+  uint32_t PreserveSRAFPRMask{};
+
+  if (EmitterCTX->Config.Is64BitMode()) {
+    DynamicGPRs = x64::PreserveAll_Dynamic;
+    DynamicFPRs = x64::PreserveAll_DynamicFPR;
+    PreserveSRAMask = x64::PreserveAll_SRAMask;
+    PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask;
+
+    if (CanUseSVE) {
+      DynamicFPRs = x64::PreserveAll_DynamicFPRSVE;
+      PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask;
+    }
+  }
+  else {
+    DynamicGPRs = x32::PreserveAll_Dynamic;
+    DynamicFPRs = x32::PreserveAll_DynamicFPR;
+    PreserveSRAMask = x32::PreserveAll_SRAMask;
+    PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask;
+
+    if (CanUseSVE) {
+      DynamicFPRs = x32::PreserveAll_DynamicFPRSVE;
+      PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask;
+    }
+  }
+
+  // Fill the static registers.
+  FillStaticRegs(true, PreserveSRAMask, PreserveSRAFPRMask);
+
+  // Pop the vector registers.
+  PopVectorRegisters(CanUseSVE, DynamicFPRs);
+
+  // Pop the general registers.
+  PopGeneralRegisters(DynamicGPRs);
+}
+
 void Arm64Emitter::Align16B() {
   uint64_t CurrentOffset = GetCursorAddress<uint64_t>();
   for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) {

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -98,12 +98,52 @@ protected:
   // We can't guarantee only the lower 64bits are used so flush everything
   static constexpr uint32_t CALLER_FPR_MASK = ~0U;
 
+  // Generic push and pop vector registers.
+  void PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
+  void PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span<const FEXCore::ARMEmitter::Register> Regs);
+
+  void PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
+  void PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Register> Regs);
+
   void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg);
   void PopDynamicRegsAndLR();
 
   void PushCalleeSavedRegisters();
   void PopCalleeSavedRegisters();
 
+  // Spills and fills SRA/Dynamic registers that are required for Arm64 `preserve_all` ABI.
+  // This ABI changes most registers to be callee saved.
+  // Caller Saved:
+  // - X0-X8, X16-X18.
+  // - v0-v7
+  // - For 256-bit SVE hosts: top 128-bits of v8-v31
+  //
+  // Callee Saved:
+  // - X9-X15, X19-X31
+  // - Low 128-bits of v8-v31
+  void SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true);
+  void FillForPreserveAllABICall(bool FPRs = true);
+
+  void SpillForABICall(bool SupportsPreserveAllABI, FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true) {
+    if (SupportsPreserveAllABI) {
+      SpillForPreserveAllABICall(TMP1, true);
+    }
+    else {
+      SpillStaticRegs(TMP1);
+      PushDynamicRegsAndLR(TMP1);
+    }
+  }
+
+  void FillForABICall(bool SupportsPreserveAllABI, bool FPRs = true) {
+    if (SupportsPreserveAllABI) {
+      FillForPreserveAllABICall(true);
+    }
+    else {
+      PopDynamicRegsAndLR();
+      FillStaticRegs();
+    }
+  }
+
   void Align16B();
 
 #ifdef VIXL_SIMULATOR

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h

@@ -7,6 +7,7 @@
 #include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
 
 namespace FEXCore::CPU {
+FEXCORE_PRESERVE_ALL_ATTR
 static void LoadDeferredFCW(uint16_t NewFCW) {
   auto PC = (NewFCW >> 8) & 3;
   switch(PC) {
@@ -35,11 +36,13 @@ static void LoadDeferredFCW(uint16_t NewFCW) {
 
 template<>
 struct OpHandlers<IR::OP_F80CVTTO> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle4(uint16_t NewFCW, float src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle8(uint16_t NewFCW, double src) {
     LoadDeferredFCW(NewFCW);
     return src;
@@ -49,6 +52,7 @@ struct OpHandlers<IR::OP_F80CVTTO> {
 template<>
 struct OpHandlers<IR::OP_F80CMP> {
   template<uint32_t Flags>
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint64_t handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
 
@@ -74,11 +78,13 @@ struct OpHandlers<IR::OP_F80CMP> {
 
 template<>
 struct OpHandlers<IR::OP_F80CVT> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static float handle4(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static double handle8(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return src;
@@ -87,22 +93,26 @@ struct OpHandlers<IR::OP_F80CVT> {
 
 template<>
 struct OpHandlers<IR::OP_F80CVTINT> {
-  static  int16_t handle2(uint16_t NewFCW, X80SoftFloat src) {
+  FEXCORE_PRESERVE_ALL_ATTR
+  static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int32_t handle4(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int64_t handle8(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
-  static  int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) {
+  FEXCORE_PRESERVE_ALL_ATTR
+  static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     auto rv = extF80_to_i32(src, softfloat_round_minMag, false);
 
@@ -115,11 +125,13 @@ struct OpHandlers<IR::OP_F80CVTINT> {
     }
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int32_t handle4t(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return extF80_to_i32(src, softfloat_round_minMag, false);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int64_t handle8t(uint16_t NewFCW, X80SoftFloat src) {
     LoadDeferredFCW(NewFCW);
     return extF80_to_i64(src, softfloat_round_minMag, false);
@@ -128,11 +140,13 @@ struct OpHandlers<IR::OP_F80CVTINT> {
 
 template<>
 struct OpHandlers<IR::OP_F80CVTTOINT> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle2(uint16_t NewFCW, int16_t src) {
     LoadDeferredFCW(NewFCW);
     return src;
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle4(uint16_t NewFCW, int32_t src) {
     LoadDeferredFCW(NewFCW);
     return src;
@@ -141,6 +155,7 @@ struct OpHandlers<IR::OP_F80CVTTOINT> {
 
 template<>
 struct OpHandlers<IR::OP_F80ROUND> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FRNDINT(Src1);
@@ -149,6 +164,7 @@ struct OpHandlers<IR::OP_F80ROUND> {
 
 template<>
 struct OpHandlers<IR::OP_F80F2XM1> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::F2XM1(Src1);
@@ -157,6 +173,7 @@ struct OpHandlers<IR::OP_F80F2XM1> {
 
 template<>
 struct OpHandlers<IR::OP_F80TAN> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FTAN(Src1);
@@ -165,6 +182,7 @@ struct OpHandlers<IR::OP_F80TAN> {
 
 template<>
 struct OpHandlers<IR::OP_F80SQRT> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FSQRT(Src1);
@@ -173,6 +191,7 @@ struct OpHandlers<IR::OP_F80SQRT> {
 
 template<>
 struct OpHandlers<IR::OP_F80SIN> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FSIN(Src1);
@@ -181,6 +200,7 @@ struct OpHandlers<IR::OP_F80SIN> {
 
 template<>
 struct OpHandlers<IR::OP_F80COS> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FCOS(Src1);
@@ -189,6 +209,7 @@ struct OpHandlers<IR::OP_F80COS> {
 
 template<>
 struct OpHandlers<IR::OP_F80XTRACT_EXP> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FXTRACT_EXP(Src1);
@@ -197,6 +218,7 @@ struct OpHandlers<IR::OP_F80XTRACT_EXP> {
 
 template<>
 struct OpHandlers<IR::OP_F80XTRACT_SIG> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FXTRACT_SIG(Src1);
@@ -205,6 +227,7 @@ struct OpHandlers<IR::OP_F80XTRACT_SIG> {
 
 template<>
 struct OpHandlers<IR::OP_F80ADD> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FADD(Src1, Src2);
@@ -213,6 +236,7 @@ struct OpHandlers<IR::OP_F80ADD> {
 
 template<>
 struct OpHandlers<IR::OP_F80SUB> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FSUB(Src1, Src2);
@@ -221,6 +245,7 @@ struct OpHandlers<IR::OP_F80SUB> {
 
 template<>
 struct OpHandlers<IR::OP_F80MUL> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FMUL(Src1, Src2);
@@ -229,6 +254,7 @@ struct OpHandlers<IR::OP_F80MUL> {
 
 template<>
 struct OpHandlers<IR::OP_F80DIV> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FDIV(Src1, Src2);
@@ -237,6 +263,7 @@ struct OpHandlers<IR::OP_F80DIV> {
 
 template<>
 struct OpHandlers<IR::OP_F80FYL2X> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FYL2X(Src1, Src2);
@@ -245,6 +272,7 @@ struct OpHandlers<IR::OP_F80FYL2X> {
 
 template<>
 struct OpHandlers<IR::OP_F80ATAN> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FATAN(Src1, Src2);
@@ -253,6 +281,7 @@ struct OpHandlers<IR::OP_F80ATAN> {
 
 template<>
 struct OpHandlers<IR::OP_F80FPREM1> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FREM1(Src1, Src2);
@@ -261,6 +290,7 @@ struct OpHandlers<IR::OP_F80FPREM1> {
 
 template<>
 struct OpHandlers<IR::OP_F80FPREM> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FREM(Src1, Src2);
@@ -269,6 +299,7 @@ struct OpHandlers<IR::OP_F80FPREM> {
 
 template<>
 struct OpHandlers<IR::OP_F80SCALE> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
     LoadDeferredFCW(NewFCW);
     return X80SoftFloat::FSCALE(Src1, Src2);
@@ -350,6 +381,7 @@ struct OpHandlers<IR::OP_F64SCALE> {
 
 template<>
 struct OpHandlers<IR::OP_F80BCDSTORE> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
     LoadDeferredFCW(NewFCW);
     bool Negative = Src1.Sign;
@@ -391,6 +423,7 @@ struct OpHandlers<IR::OP_F80BCDSTORE> {
 
 template<>
 struct OpHandlers<IR::OP_F80BCDLOAD> {
+  FEXCORE_PRESERVE_ALL_ATTR
   static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src) {
     LoadDeferredFCW(NewFCW);
     uint8_t *Src1 = reinterpret_cast<uint8_t *>(&Src);

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp

@@ -11,148 +11,78 @@ namespace FEXCore::CPU {
 
 template<typename R, typename... Args>
 static FallbackInfo GetFallbackInfo(R(*fn)(Args...), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_UNKNOWN, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_F32, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_F64, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_I16, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_I32, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(float(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F32_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_I16_F80, (void*)fn, HandlerIndex};
+  return {FABI_UNKNOWN, (void*)fn, HandlerIndex, false};
 }
 
 template<>
 FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_I16_F64, (void*)fn, HandlerIndex};
+  return {FABI_F64_I16_F64, (void*)fn, HandlerIndex, false};
 }
 
 template<>
 FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double,double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_I16_F64_F64, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int16_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I16_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int32_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int64_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I64_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint64_t(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I64_I16_F80_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16_F80_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint32_t(*fn)(uint64_t, uint64_t, __uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_I64_I64_I128_I128_I16, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_I128_I128_I16, (void*)fn, HandlerIndex};
+  return {FABI_F64_I16_F64_F64, (void*)fn, HandlerIndex, false};
 }
 
 void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
-  Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4).fn);
-  Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8).fn);
-  Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4).fn);
-  Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8).fn);
-  Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2).fn);
-  Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4).fn);
-  Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8).fn);
-  Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>, Core::OPINDEX_F80CMP_0).fn);
-  Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>, Core::OPINDEX_F80CMP_1).fn);
-  Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>, Core::OPINDEX_F80CMP_2).fn);
-  Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>, Core::OPINDEX_F80CMP_3).fn);
-  Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>, Core::OPINDEX_F80CMP_4).fn);
-  Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>, Core::OPINDEX_F80CMP_5).fn);
-  Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>, Core::OPINDEX_F80CMP_6).fn);
-  Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>, Core::OPINDEX_F80CMP_7).fn);
-  Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2).fn);
-  Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4).fn);
+  Info[Core::OPINDEX_F80CVTTO_4]  = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4);
+  Info[Core::OPINDEX_F80CVTTO_8]  = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8);
+  Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4);
+  Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8);
+  Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2);
+  Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4);
+  Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t);
+  Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>);
+  Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>);
+  Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>);
+  Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>);
+  Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>);
+  Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>);
+  Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>);
+  Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>);
+  Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2);
+  Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4);
 
   // Unary
-  Info[Core::OPINDEX_F80ROUND] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle, Core::OPINDEX_F80ROUND).fn);
-  Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle, Core::OPINDEX_F80F2XM1).fn);
-  Info[Core::OPINDEX_F80TAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle, Core::OPINDEX_F80TAN).fn);
-  Info[Core::OPINDEX_F80SQRT] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle, Core::OPINDEX_F80SQRT).fn);
-  Info[Core::OPINDEX_F80SIN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle, Core::OPINDEX_F80SIN).fn);
-  Info[Core::OPINDEX_F80COS] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle, Core::OPINDEX_F80COS).fn);
-  Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle, Core::OPINDEX_F80XTRACT_EXP).fn);
-  Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle, Core::OPINDEX_F80XTRACT_SIG).fn);
-  Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle, Core::OPINDEX_F80BCDSTORE).fn);
-  Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle, Core::OPINDEX_F80BCDLOAD).fn);
+  Info[Core::OPINDEX_F80ROUND] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle);
+  Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle);
+  Info[Core::OPINDEX_F80TAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle);
+  Info[Core::OPINDEX_F80SQRT] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle);
+  Info[Core::OPINDEX_F80SIN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle);
+  Info[Core::OPINDEX_F80COS] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle);
+  Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle);
+  Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle);
+  Info[Core::OPINDEX_F80BCDSTORE]   = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle);
+  Info[Core::OPINDEX_F80BCDLOAD]    = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle);
 
   // Binary
-  Info[Core::OPINDEX_F80ADD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle, Core::OPINDEX_F80ADD).fn);
-  Info[Core::OPINDEX_F80SUB] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle, Core::OPINDEX_F80SUB).fn);
-  Info[Core::OPINDEX_F80MUL] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle, Core::OPINDEX_F80MUL).fn);
-  Info[Core::OPINDEX_F80DIV] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle, Core::OPINDEX_F80DIV).fn);
-  Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle, Core::OPINDEX_F80FYL2X).fn);
-  Info[Core::OPINDEX_F80ATAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle, Core::OPINDEX_F80ATAN).fn);
-  Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle, Core::OPINDEX_F80FPREM1).fn);
-  Info[Core::OPINDEX_F80FPREM] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle, Core::OPINDEX_F80FPREM).fn);
-  Info[Core::OPINDEX_F80SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle, Core::OPINDEX_F80SCALE).fn);
+  Info[Core::OPINDEX_F80ADD] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle);
+  Info[Core::OPINDEX_F80SUB] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle);
+  Info[Core::OPINDEX_F80MUL] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle);
+  Info[Core::OPINDEX_F80DIV] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle);
+  Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle);
+  Info[Core::OPINDEX_F80ATAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle);
+  Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle);
+  Info[Core::OPINDEX_F80FPREM] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle);
+  Info[Core::OPINDEX_F80SCALE] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle);
 
   // Double Precision
-  Info[Core::OPINDEX_F64SIN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle, Core::OPINDEX_F64SIN).fn);
-  Info[Core::OPINDEX_F64COS] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle, Core::OPINDEX_F64COS).fn);
-  Info[Core::OPINDEX_F64TAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle, Core::OPINDEX_F64TAN).fn);
-  Info[Core::OPINDEX_F64ATAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle, Core::OPINDEX_F64ATAN).fn);
-  Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle, Core::OPINDEX_F64F2XM1).fn);
-  Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle, Core::OPINDEX_F64FYL2X).fn);
-  Info[Core::OPINDEX_F64FPREM] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle, Core::OPINDEX_F64FPREM).fn);
-  Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle, Core::OPINDEX_F64FPREM1).fn);
-  Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle, Core::OPINDEX_F64SCALE).fn);
+  Info[Core::OPINDEX_F64SIN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle);
+  Info[Core::OPINDEX_F64COS] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle);
+  Info[Core::OPINDEX_F64TAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle);
+  Info[Core::OPINDEX_F64ATAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle);
+  Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle);
+  Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle);
+  Info[Core::OPINDEX_F64FPREM] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle);
+  Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle);
+  Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle);
 
   // SSE4.2 string instructions
-  Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX).fn);
-  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX).fn);
+  Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle);
+  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle);
 }
 
 bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) {
@@ -163,11 +93,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
 
       switch (Op->SrcSize) {
         case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4);
+          *Info = {FABI_F80_I16_F32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
         case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8);
+          *Info = {FABI_F80_I16_F64, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
       default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -177,11 +107,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
     case IR::OP_F80CVT: {
       switch (OpSize) {
         case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4);
+          *Info = {FABI_F32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
         case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8);
+          *Info = {FABI_F64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
         default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -194,28 +124,28 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
       switch (OpSize) {
         case 2: {
           if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2);
+            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2);
+            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           return true;
         }
         case 4: {
           if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4);
+            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4);
+            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           return true;
         }
         case 8: {
           if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8);
+            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8);
+            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           }
           return true;
         }
@@ -237,7 +167,7 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
         &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
       };
 
-      *Info = GetFallbackInfo(handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags));
+      *Info = {FABI_I64_I16_F80_F80, (void*)handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags), FEXCORE_HAS_PRESERVE_ALL_ATTR};
       return true;
     }
 
@@ -246,11 +176,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
 
       switch (Op->SrcSize) {
         case 2: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2);
+          *Info = {FABI_F80_I16_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
         case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4);
+          *Info = {FABI_F80_I16_I32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
           return true;
         }
         default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -258,9 +188,15 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
       break;
     }
 
-#define COMMON_X87_OP(OP) \
+#define COMMON_UNARY_X87_OP(OP) \
     case IR::OP_F80##OP: { \
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP); \
+      *Info = {FABI_F80_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \
+      return true; \
+    }
+
+#define COMMON_BINARY_X87_OP(OP) \
+    case IR::OP_F80##OP: { \
+      *Info = {FABI_F80_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \
       return true; \
     }
 
@@ -271,27 +207,27 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
     }
 
     // Unary
-    COMMON_X87_OP(ROUND)
-    COMMON_X87_OP(F2XM1)
-    COMMON_X87_OP(TAN)
-    COMMON_X87_OP(SQRT)
-    COMMON_X87_OP(SIN)
-    COMMON_X87_OP(COS)
-    COMMON_X87_OP(XTRACT_EXP)
-    COMMON_X87_OP(XTRACT_SIG)
-    COMMON_X87_OP(BCDSTORE)
-    COMMON_X87_OP(BCDLOAD)
+    COMMON_UNARY_X87_OP(ROUND)
+    COMMON_UNARY_X87_OP(F2XM1)
+    COMMON_UNARY_X87_OP(TAN)
+    COMMON_UNARY_X87_OP(SQRT)
+    COMMON_UNARY_X87_OP(SIN)
+    COMMON_UNARY_X87_OP(COS)
+    COMMON_UNARY_X87_OP(XTRACT_EXP)
+    COMMON_UNARY_X87_OP(XTRACT_SIG)
+    COMMON_UNARY_X87_OP(BCDSTORE)
+    COMMON_UNARY_X87_OP(BCDLOAD)
 
     // Binary
-    COMMON_X87_OP(ADD)
-    COMMON_X87_OP(SUB)
-    COMMON_X87_OP(MUL)
-    COMMON_X87_OP(DIV)
-    COMMON_X87_OP(FYL2X)
-    COMMON_X87_OP(ATAN)
-    COMMON_X87_OP(FPREM1)
-    COMMON_X87_OP(FPREM)
-    COMMON_X87_OP(SCALE)
+    COMMON_BINARY_X87_OP(ADD)
+    COMMON_BINARY_X87_OP(SUB)
+    COMMON_BINARY_X87_OP(MUL)
+    COMMON_BINARY_X87_OP(DIV)
+    COMMON_BINARY_X87_OP(FYL2X)
+    COMMON_BINARY_X87_OP(ATAN)
+    COMMON_BINARY_X87_OP(FPREM1)
+    COMMON_BINARY_X87_OP(FPREM)
+    COMMON_BINARY_X87_OP(SCALE)
 
     // Double Precision Unary
     COMMON_F64_OP(F2XM1)
@@ -308,10 +244,10 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
 
     // SSE4.2 Fallbacks
     case IR::OP_VPCMPESTRX:
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX);
+      *Info = {FABI_I32_I64_I64_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR};
       return true;
     case IR::OP_VPCMPISTRX:
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX);
+      *Info = {FABI_I32_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR};
       return true;
 
     default:

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h

@@ -35,6 +35,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
     NegativeMasked,
   };
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t handle(uint64_t RAX, uint64_t RDX, __uint128_t lhs, __uint128_t rhs, uint16_t control) {
     // Subtract by 1 in order to make validity limits 0-based
     const auto valid_lhs = GetExplicitLength(RAX, control) - 1;
@@ -44,6 +45,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
   }
 
   // Main PCMPXSTRX algorithm body. Allows for reuse with both implicit and explicit length variants.
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t MainBody(const __uint128_t& lhs, int valid_lhs, const __uint128_t& rhs, int valid_rhs, uint16_t control) {
     const uint32_t aggregation = PerformAggregation(lhs, valid_lhs, rhs, valid_rhs, control);
     const int32_t upper_limit = (16 >> (control & 1)) - 1;
@@ -68,6 +70,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
     return result | (flags << 16);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int32_t GetExplicitLength(uint64_t reg, uint16_t control) {
     // Bit 8 controls whether or not the reg value is 64-bit or 32-bit.
     int64_t value = 0;
@@ -91,6 +94,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
     return std::abs(static_cast<int>(value));
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int32_t GetElement(const __uint128_t& vec, int32_t index, uint16_t control) {
     const auto* vec_ptr = reinterpret_cast<const uint8_t*>(&vec);
 
@@ -114,6 +118,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
     }
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t PerformAggregation(const __uint128_t& lhs, int32_t valid_lhs,
                                      const __uint128_t& rhs, int32_t valid_rhs,
                                      uint16_t control) {
@@ -130,6 +135,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
     }
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t HandlePolarity(uint32_t value, uint16_t control, int upper_limit, int valid_rhs) {
     switch (static_cast<Polarity>((control >> 4) & 0b11)) {
       case Polarity::Negative:
@@ -169,6 +175,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
   //                   │
   // 'c' match ────────┘
   //
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t HandleEqualAny(const __uint128_t& lhs, int32_t valid_lhs,
                                  const __uint128_t& rhs, int32_t valid_rhs,
                                  uint16_t control) {
@@ -215,6 +222,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
   //                                    │
   // 'Z' >= 'z' && 'A' <= 'z' ──────────┘
   //
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t HandleRanges(const __uint128_t& lhs, int32_t valid_lhs,
                                const __uint128_t& rhs, int32_t valid_rhs,
                                uint16_t control) {
@@ -267,6 +275,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
   //                      │
   // 'a' == 'a' ──────────┘
   //
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t HandleEqualEach(const __uint128_t& lhs, int32_t valid_lhs,
                                   const __uint128_t& rhs, int32_t valid_rhs,
                                   uint16_t control) {
@@ -321,6 +330,7 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {
   //                      │
   // At index 0 ──────────┘
   //
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t HandleEqualOrdered(const __uint128_t& lhs, int32_t valid_lhs,
                                      const __uint128_t& rhs, int32_t valid_rhs,
                                      uint16_t control) {
@@ -369,6 +379,7 @@ struct OpHandlers<IR::OP_VPCMPISTRX> {
   //      to be the max length possible for the given character size specified
   //      in the control flags (16 characters for 8-bit, and 8 characters for 16-bit).
   //
+  FEXCORE_PRESERVE_ALL_ATTR
   static uint32_t handle(__uint128_t lhs, __uint128_t rhs, uint16_t control) {
     // Subtract by 1 in order to make validity limits 0-based
     const auto valid_lhs = GetImplicitLength(lhs, control) - 1;
@@ -377,6 +388,7 @@ struct OpHandlers<IR::OP_VPCMPISTRX> {
     return OpHandlers<IR::OP_VPCMPESTRX>::MainBody(lhs, valid_lhs, rhs, valid_rhs, control);
   }
 
+  FEXCORE_PRESERVE_ALL_ATTR
   static int32_t GetImplicitLength(const __uint128_t& data, uint16_t control) {
     const auto* data_u8 = reinterpret_cast<const uint8_t*>(&data);
     const auto is_using_words = (control & 1) != 0;

FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -47,6 +47,7 @@ namespace FEXCore::CPU {
     FallbackABI ABI;
     void *fn;
     FEXCore::Core::FallbackHandlerIndex HandlerIndex;
+    bool SupportsPreserveAllABI;
   };
 
   class InterpreterOps {

FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp

@@ -85,9 +85,8 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
   } else {
     switch(Info.ABI) {
       case FABI_F80_I16_F32:{
-        SpillStaticRegs(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
-        PushDynamicRegsAndLR(TMP1);
         const auto Src1 = GetVReg(IROp->Args[0].ID());
         fmov(ARMEmitter::SReg::s0, Src1.S());
         ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
@@ -98,9 +97,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r1);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         eor(Dst.Q(), Dst.Q(), Dst.Q());
@@ -110,9 +107,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F80_I16_F64:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
         mov(ARMEmitter::DReg::d0, Src1.D());
@@ -124,9 +119,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r1);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         eor(Dst.Q(), Dst.Q(), Dst.Q());
@@ -137,9 +130,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
 
       case FABI_F80_I16_I16:
       case FABI_F80_I16_I32: {
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetReg(IROp->Args[0].ID());
         ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
@@ -156,9 +147,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r2);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         eor(Dst.Q(), Dst.Q(), Dst.Q());
@@ -168,9 +157,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F32_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -185,9 +172,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r3);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         fmov(Dst.S(), ARMEmitter::SReg::s0);
@@ -195,9 +180,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -212,9 +195,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r3);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         mov(Dst.D(), ARMEmitter::DReg::d0);
@@ -222,9 +203,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_I16_F64: {
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -237,9 +216,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r1);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         mov(Dst.D(), ARMEmitter::DReg::d0);
@@ -247,9 +224,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_I16_F64_F64: {
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
         const auto Src2 = GetVReg(IROp->Args[1].ID());
@@ -264,9 +239,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r1);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         mov(Dst.D(), ARMEmitter::DReg::d0);
@@ -274,9 +247,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_I16_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -291,18 +262,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r3);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         sxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
       }
       break;
       case FABI_I32_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -317,18 +284,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r3);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         mov(ARMEmitter::Size::i32Bit, Dst, ARMEmitter::Reg::r0);
       }
       break;
       case FABI_I64_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -342,19 +305,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
 #else
         blr(ARMEmitter::Reg::r3);
 #endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
       }
       break;
       case FABI_I64_I16_F80_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
         const auto Src2 = GetVReg(IROp->Args[1].ID());
@@ -372,18 +330,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
 #else
         blr(ARMEmitter::Reg::r5);
 #endif
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
       }
       break;
       case FABI_F80_I16_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
 
@@ -398,9 +352,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r3);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         eor(Dst.Q(), Dst.Q(), Dst.Q());
@@ -409,9 +361,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_F80_I16_F80_F80:{
-        SpillStaticRegs(TMP1);
-
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Src1 = GetVReg(IROp->Args[0].ID());
         const auto Src2 = GetVReg(IROp->Args[1].ID());
@@ -430,9 +380,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r5);
 #endif
 
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetVReg(Node);
         eor(Dst.Q(), Dst.Q(), Dst.Q());
@@ -441,8 +389,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_I32_I64_I64_I128_I128_I16: {
-        SpillStaticRegs(TMP1);
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
         const auto Control = Op->Control;
@@ -470,16 +417,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r7);
 #endif
 
-        PopDynamicRegsAndLR();
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         mov(Dst.W(), ARMEmitter::WReg::w0);
         break;
       }
       case FABI_I32_I128_I128_I16: {
-        SpillStaticRegs(TMP1);
-        PushDynamicRegsAndLR(TMP1);
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
 
         const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
 
@@ -502,8 +447,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         blr(ARMEmitter::Reg::r5);
 #endif
 
-        PopDynamicRegsAndLR();
-        FillStaticRegs();
+        FillForABICall(Info.SupportsPreserveAllABI, true);
 
         const auto Dst = GetReg(Node);
         mov(Dst.W(), ARMEmitter::WReg::w0);

FEXCore/include/FEXCore/Core/CoreState.h

@@ -158,8 +158,7 @@ namespace FEXCore::Core {
   struct InternalThreadState;
 
   enum FallbackHandlerIndex {
-    OPINDEX_F80LOADFCW = 0,
-    OPINDEX_F80CVTTO_4,
+    OPINDEX_F80CVTTO_4 = 0,
     OPINDEX_F80CVTTO_8,
     OPINDEX_F80CVT_4,
     OPINDEX_F80CVT_8,

FEXHeaderUtils/CMakeLists.txt

@@ -7,8 +7,8 @@ check_cxx_source_compiles(
   int main() {
   return ::getcpu(nullptr, nullptr);
   }"
-  compiles)
-if (compiles)
+  HAS_SYSCALL_GETCPU)
+if (HAS_SYSCALL_GETCPU)
   message(STATUS "Has getcpu helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETCPU=1)
 endif ()
@@ -19,8 +19,8 @@ check_cxx_source_compiles(
   int main() {
   return ::gettid();
   }"
-  compiles)
-if (compiles)
+  HAS_SYSCALL_GETTID)
+if (HAS_SYSCALL_GETTID)
   message(STATUS "Has gettid helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETTID=1)
 endif ()
@@ -31,8 +31,8 @@ check_cxx_source_compiles(
   int main() {
   return ::tgkill(0, 0, 0);
   }"
-  compiles)
-if (compiles)
+  HAS_SYSCALL_TGKILL)
+if (HAS_SYSCALL_TGKILL)
   message(STATUS "Has tgkill helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_TGKILL=1)
 endif ()
@@ -43,8 +43,8 @@ check_cxx_source_compiles(
   int main() {
   return ::statx(0, nullptr, 0, 0, nullptr);
   }"
-  compiles)
-if (compiles)
+  HAS_SYSCALL_STATX)
+if (HAS_SYSCALL_STATX)
   message(STATUS "Has statx helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_STATX=1)
 endif ()
@@ -55,8 +55,8 @@ check_cxx_source_compiles(
   int main() {
   return ::renameat2(0, nullptr, 0, nullptr, 0);
   }"
-  compiles)
-if (compiles)
+  HAS_SYSCALL_RENAMEAT2)
+if (HAS_SYSCALL_RENAMEAT2)
   message(STATUS "Has renameat2 helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_RENAMEAT2=1)
 endif ()

unittests/InstructionCountCI/H0F38.json

@@ -682,7 +682,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1552]",
+        "ldr x0, [x28, #1544]",
         "ldr q2, [x0]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",

unittests/InstructionCountCI/H0F3A.json

@@ -1556,7 +1556,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1608]",
+        "ldr x0, [x28, #1600]",
         "ldr q2, [x0]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
@@ -1571,7 +1571,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1608]",
+        "ldr x0, [x28, #1600]",
         "ldr q2, [x0]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",

unittests/InstructionCountCI/PrimaryGroup.json

@@ -3232,7 +3232,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #1920]",
+        "ldr x3, [x28, #1912]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -3243,7 +3243,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #1936]",
+        "ldr x3, [x28, #1928]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -3307,7 +3307,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #1928]",
+        "ldr x3, [x28, #1920]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -3320,7 +3320,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #1944]",
+        "ldr x3, [x28, #1936]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",

unittests/InstructionCountCI/Secondary.json

@@ -892,7 +892,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr x0, [x28, #1600]",
+        "ldr x0, [x28, #1592]",
         "ldr q3, [x0]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
@@ -905,7 +905,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr x0, [x28, #1600]",
+        "ldr x0, [x28, #1592]",
         "ldr q3, [x0]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
@@ -1335,7 +1335,7 @@
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #768]",
-        "ldr x0, [x28, #1616]",
+        "ldr x0, [x28, #1608]",
         "ldr d3, [x0, #16]",
         "tbl v2.8b, {v2.16b}, v3.8b",
         "str d2, [x28, #752]"
@@ -1347,7 +1347,7 @@
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
         "ldr d2, [x4]",
-        "ldr x0, [x28, #1616]",
+        "ldr x0, [x28, #1608]",
         "ldr d3, [x0, #16]",
         "tbl v2.8b, {v2.16b}, v3.8b",
         "str d2, [x28, #752]"
@@ -4139,7 +4139,7 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
       ]
@@ -4149,7 +4149,7 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q2, [x0, #16]",
         "mov v0.16b, v17.16b",
         "mov v1.16b, v16.16b",
@@ -4162,7 +4162,7 @@
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q3, [x0, #16]",
         "mov v0.16b, v16.16b",
         "mov v1.16b, v2.16b",

unittests/InstructionCountCI/Secondary_OpSize.json

@@ -592,7 +592,7 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1632]",
+        "ldr x0, [x28, #1624]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -607,7 +607,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #1632]",
+        "ldr x0, [x28, #1624]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v2.16b}, v3.16b"
       ]
@@ -1134,7 +1134,7 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1584]",
+        "ldr x0, [x28, #1576]",
         "ldr q2, [x0]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"

unittests/InstructionCountCI/Secondary_REP.json

@@ -390,7 +390,7 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1624]",
+        "ldr x0, [x28, #1616]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]

unittests/InstructionCountCI/Secondary_REPNE.json

@@ -335,7 +335,7 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1616]",
+        "ldr x0, [x28, #1608]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -515,7 +515,7 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #1568]",
+        "ldr x0, [x28, #1560]",
         "ldr q2, [x0]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"

unittests/InstructionCountCI/VEX_map1.json

@@ -3230,7 +3230,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q4, [x0, #16]",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
         "mov v2.16b, v2.16b",
@@ -3292,7 +3292,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q4, [x0, #32]",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
         "mov v2.16b, v2.16b",
@@ -3354,7 +3354,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1640]",
+        "ldr x0, [x28, #1632]",
         "ldr q4, [x0, #48]",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
         "mov v2.16b, v2.16b",
@@ -5103,7 +5103,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1584]",
+        "ldr x0, [x28, #1576]",
         "ldr q4, [x0]",
         "eor v3.16b, v3.16b, v4.16b",
         "fadd v2.2d, v2.2d, v3.2d",
@@ -5120,7 +5120,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1584]",
+        "ldr x0, [x28, #1576]",
         "ld1b {z4.b}, p7/z, [x0]",
         "eor z3.d, z3.d, z4.d",
         "fadd z2.d, z2.d, z3.d",
@@ -5136,7 +5136,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1568]",
+        "ldr x0, [x28, #1560]",
         "ldr q4, [x0]",
         "eor v3.16b, v3.16b, v4.16b",
         "fadd v2.4s, v2.4s, v3.4s",
@@ -5153,7 +5153,7 @@
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
         "mov z3.d, p7/m, z18.d",
-        "ldr x0, [x28, #1568]",
+        "ldr x0, [x28, #1560]",
         "ld1b {z4.b}, p7/z, [x0]",
         "eor z3.d, z3.d, z4.d",
         "fadd z2.s, z2.s, z3.s",

unittests/InstructionCountCI/VEX_map2.json

@@ -1834,7 +1834,7 @@
       ],
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
-        "ldr x0, [x28, #1552]",
+        "ldr x0, [x28, #1544]",
         "ldr q3, [x0]",
         "zip1 v4.8h, v3.8h, v2.8h",
         "zip2 v2.8h, v3.8h, v2.8h",

unittests/InstructionCountCI/VEX_map3.json

@@ -5381,7 +5381,7 @@
       ],
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
-        "ldr x0, [x28, #1608]",
+        "ldr x0, [x28, #1600]",
         "ldr q3, [x0]",
         "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
@@ -5398,7 +5398,7 @@
       ],
       "ExpectedArm64ASM": [
         "mov z2.d, p7/m, z17.d",
-        "ldr x0, [x28, #1608]",
+        "ldr x0, [x28, #1600]",
         "ldr q3, [x0]",
         "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",