From da21fc937b6456716fa8fbd39546b695fe8239c4 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:05:40 -0700 Subject: [PATCH 1/7] FHU: Fixes syscall helper caching check_cxx_source_compiles caches by variable name, so `compiles` was getting cached and breaking future checks. --- FEXHeaderUtils/CMakeLists.txt | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/FEXHeaderUtils/CMakeLists.txt b/FEXHeaderUtils/CMakeLists.txt index 264229bce..cecffc153 100644 --- a/FEXHeaderUtils/CMakeLists.txt +++ b/FEXHeaderUtils/CMakeLists.txt @@ -7,8 +7,8 @@ check_cxx_source_compiles( int main() { return ::getcpu(nullptr, nullptr); }" - compiles) -if (compiles) + HAS_SYSCALL_GETCPU) +if (HAS_SYSCALL_GETCPU) message(STATUS "Has getcpu helper") target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETCPU=1) endif () @@ -19,8 +19,8 @@ check_cxx_source_compiles( int main() { return ::gettid(); }" - compiles) -if (compiles) + HAS_SYSCALL_GETTID) +if (HAS_SYSCALL_GETTID) message(STATUS "Has gettid helper") target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETTID=1) endif () @@ -31,8 +31,8 @@ check_cxx_source_compiles( int main() { return ::tgkill(0, 0, 0); }" - compiles) -if (compiles) + HAS_SYSCALL_TGKILL) +if (HAS_SYSCALL_TGKILL) message(STATUS "Has tgkill helper") target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_TGKILL=1) endif () @@ -43,8 +43,8 @@ check_cxx_source_compiles( int main() { return ::statx(0, nullptr, 0, 0, nullptr); }" - compiles) -if (compiles) + HAS_SYSCALL_STATX) +if (HAS_SYSCALL_STATX) message(STATUS "Has statx helper") target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_STATX=1) endif () @@ -55,8 +55,8 @@ check_cxx_source_compiles( int main() { return ::renameat2(0, nullptr, 0, nullptr, 0); }" - compiles) -if (compiles) + HAS_SYSCALL_RENAMEAT2) +if (HAS_SYSCALL_RENAMEAT2) message(STATUS "Has renameat2 helper") target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_RENAMEAT2=1) endif () From 838293c2f0b1699d47d1697f072c596e7a6f66bf Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:06:46 -0700 Subject: [PATCH 2/7] FEXCore: Remove unused FallbackhandlerIndex LoadFCW We removed this once passing in FCW explicitly. --- FEXCore/include/FEXCore/Core/CoreState.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/FEXCore/include/FEXCore/Core/CoreState.h b/FEXCore/include/FEXCore/Core/CoreState.h index 911b54778..8e0880c74 100644 --- a/FEXCore/include/FEXCore/Core/CoreState.h +++ b/FEXCore/include/FEXCore/Core/CoreState.h @@ -157,8 +157,7 @@ namespace FEXCore::Core { struct InternalThreadState; enum FallbackHandlerIndex { - OPINDEX_F80LOADFCW = 0, - OPINDEX_F80CVTTO_4, + OPINDEX_F80CVTTO_4 = 0, OPINDEX_F80CVTTO_8, OPINDEX_F80CVT_4, OPINDEX_F80CVT_8, From 95e5d37e4c6a1762411b86b638038c2326786a56 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:07:30 -0700 Subject: [PATCH 3/7] FEXCore: Adds compile time check support for preserve_all --- FEXCore/CMakeLists.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/FEXCore/CMakeLists.txt b/FEXCore/CMakeLists.txt index 4b0d12190..2dc062499 100644 --- a/FEXCore/CMakeLists.txt +++ b/FEXCore/CMakeLists.txt @@ -33,6 +33,22 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON) include(CheckCXXCompilerFlag) include(CheckIncludeFileCXX) +include(CheckCXXSourceCompiles) + +set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes") +check_cxx_source_compiles( + " + __attribute__((preserve_all)) + void Testy() { + } + int main() { + return 0; + }" + HAS_CLANG_PRESERVE_ALL) +unset(CMAKE_REQUIRED_FLAGS) +if (HAS_CLANG_PRESERVE_ALL) + message(STATUS "Has clang::preserve_all") +endif () if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/) # Useful to have for freestanding libFEXCore From 745729cdc27cf18e18f365676683937ebaabac63 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:15:15 -0700 Subject: [PATCH 4/7] SoftFloat-3e: Adds preserve_all attribute to all functions used This will let FEX's JIT be more optimal --- FEXCore/Source/CMakeLists.txt | 9 ++++++++ .../Source/Common/SoftFloat-3e/extF80_add.c | 1 + .../Source/Common/SoftFloat-3e/extF80_div.c | 1 + .../Source/Common/SoftFloat-3e/extF80_eq.c | 1 + .../Source/Common/SoftFloat-3e/extF80_lt.c | 1 + .../Source/Common/SoftFloat-3e/extF80_mul.c | 1 + .../Source/Common/SoftFloat-3e/extF80_rem.c | 1 + .../Common/SoftFloat-3e/extF80_roundToInt.c | 1 + .../Source/Common/SoftFloat-3e/extF80_sqrt.c | 1 + .../Source/Common/SoftFloat-3e/extF80_sub.c | 1 + .../Common/SoftFloat-3e/extF80_to_f128.c | 1 + .../Common/SoftFloat-3e/extF80_to_f32.c | 1 + .../Common/SoftFloat-3e/extF80_to_f64.c | 1 + .../Common/SoftFloat-3e/extF80_to_i32.c | 1 + .../Common/SoftFloat-3e/extF80_to_i64.c | 1 + .../Common/SoftFloat-3e/extF80_to_ui64.c | 1 + .../Common/SoftFloat-3e/f128_to_extF80.c | 1 + .../Common/SoftFloat-3e/f32_to_extF80.c | 1 + .../Common/SoftFloat-3e/f64_to_extF80.c | 1 + .../Common/SoftFloat-3e/i32_to_extF80.c | 1 + .../Source/Common/SoftFloat-3e/internals.h | 10 +++++++++ .../Source/Common/SoftFloat-3e/primitives.h | 16 ++++++++++++++ FEXCore/Source/Common/SoftFloat-3e/s_add128.c | 1 + .../Common/SoftFloat-3e/s_approxRecip32_1.c | 1 + .../SoftFloat-3e/s_approxRecipSqrt32_1.c | 1 + .../SoftFloat-3e/s_commonNaNToExtF80UI.c | 1 + .../Common/SoftFloat-3e/s_commonNaNToF128UI.c | 1 + .../Common/SoftFloat-3e/s_commonNaNToF32UI.c | 1 + .../Common/SoftFloat-3e/s_commonNaNToF64UI.c | 1 + .../SoftFloat-3e/s_countLeadingZeros32.c | 1 + .../SoftFloat-3e/s_countLeadingZeros64.c | 1 + .../SoftFloat-3e/s_extF80UIToCommonNaN.c | 1 + .../Common/SoftFloat-3e/s_f128UIToCommonNaN.c | 1 + .../Common/SoftFloat-3e/s_f32UIToCommonNaN.c | 1 + .../Common/SoftFloat-3e/s_f64UIToCommonNaN.c | 1 + FEXCore/Source/Common/SoftFloat-3e/s_le128.c | 1 + FEXCore/Source/Common/SoftFloat-3e/s_lt128.c | 1 + .../SoftFloat-3e/s_mul64ByShifted32To128.c | 1 + .../Source/Common/SoftFloat-3e/s_mul64To128.c | 1 + .../SoftFloat-3e/s_normRoundPackToExtF80.c | 1 + .../SoftFloat-3e/s_normSubnormalExtF80Sig.c | 1 + .../SoftFloat-3e/s_normSubnormalF128Sig.c | 1 + .../SoftFloat-3e/s_normSubnormalF32Sig.c | 1 + .../SoftFloat-3e/s_normSubnormalF64Sig.c | 1 + .../SoftFloat-3e/s_propagateNaNExtF80UI.c | 1 + .../Common/SoftFloat-3e/s_roundPackToExtF80.c | 1 + .../Common/SoftFloat-3e/s_roundPackToF32.c | 1 + .../Common/SoftFloat-3e/s_roundPackToF64.c | 1 + .../Source/Common/SoftFloat-3e/s_roundToI32.c | 1 + .../Source/Common/SoftFloat-3e/s_roundToI64.c | 1 + .../Common/SoftFloat-3e/s_shiftRightJam32.c | 1 + .../Common/SoftFloat-3e/s_shiftRightJam64.c | 1 + .../SoftFloat-3e/s_shiftRightJam64Extra.c | 1 + .../Common/SoftFloat-3e/s_shortShiftLeft128.c | 1 + .../SoftFloat-3e/s_shortShiftRight128.c | 1 + .../SoftFloat-3e/s_shortShiftRightJam64.c | 1 + FEXCore/Source/Common/SoftFloat-3e/s_sub128.c | 1 + .../Source/Common/SoftFloat-3e/softfloat.h | 21 +++++++++++++++++++ .../SoftFloat-3e/softfloat_raiseFlags.c | 1 + .../Source/Common/SoftFloat-3e/specialize.h | 9 ++++++++ .../Common/SoftFloat-3e/ui64_to_extF80.c | 1 + 61 files changed, 121 insertions(+) diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index 3e2e4b232..1d915a207 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -231,6 +231,15 @@ if (ENABLE_JIT_ARM64) ) endif() +if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL) + list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1") +else() + list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=;-DFEXCORE_HAS_PRESERVE_ALL_ATTR=0") +endif() + +# Some defines for the softfloat library +list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ") + set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils) if (NOT MINGW_BUILD) diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_add.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_add.c index e331d01e9..476921c88 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_add.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_add.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_div.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_div.c index 28dfb13de..f84c17d7a 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_div.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_div.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c index efcbc3714..c2e6f85b5 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR bool extF80_eq( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c index a4ac69fa6..937bbbbf5 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR bool extF80_lt( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c index 39ce4012c..205dfaa89 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c index 5ad977526..333443cbf 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c index 10b6d5dd8..79213ee00 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c index af8c496e1..e94e20ff4 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_sqrt( extFloat80_t a ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c index 770c7563a..077937af9 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c index 4de90ae31..b1e0c4a6d 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR float128_t extF80_to_f128( extFloat80_t a ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c index 77fcfdc11..413c3f353 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR float32_t extF80_to_f32( extFloat80_t a ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c index 410d6622c..531552483 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR float64_t extF80_to_f64( extFloat80_t a ) { union { struct extFloat80M s; extFloat80_t f; } uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c index 9acdc3c9b..c3fb69651 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR int_fast32_t extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c index ba307a61c..6faa51603 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR int_fast64_t extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c index 490b26aaf..c2dd8e238 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR uint_fast64_t extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c b/FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c index ec169c0ff..845f68a1f 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f128_to_extF80( float128_t a ) { union ui128_f128 uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c b/FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c index 742ed649c..fe73de85b 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f32_to_extF80( float32_t a ) { union ui32_f32 uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c b/FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c index 2799d9b07..1b04abc2f 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f64_to_extF80( float64_t a ) { union ui64_f64 uA; diff --git a/FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c b/FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c index 8036fa9f1..3e36bac6d 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t i32_to_extF80( int32_t a ) { uint_fast16_t uiZ64; diff --git a/FEXCore/Source/Common/SoftFloat-3e/internals.h b/FEXCore/Source/Common/SoftFloat-3e/internals.h index 020b3402f..271e08e46 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/internals.h +++ b/FEXCore/Source/Common/SoftFloat-3e/internals.h @@ -68,9 +68,11 @@ uint_fast64_t uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool ); #endif +FEXCORE_PRESERVE_ALL_ATTR int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool ); #ifdef SOFTFLOAT_FAST_INT64 +FEXCORE_PRESERVE_ALL_ATTR int_fast64_t softfloat_roundToI64( bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool ); @@ -109,8 +111,10 @@ float16_t #define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF)) struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; }; +FEXCORE_PRESERVE_ALL_ATTR struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t ); +FEXCORE_PRESERVE_ALL_ATTR float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t ); float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t ); @@ -130,8 +134,10 @@ float32_t #define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF ))) struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; }; +FEXCORE_PRESERVE_ALL_ATTR struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t ); +FEXCORE_PRESERVE_ALL_ATTR float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t ); float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t ); @@ -155,11 +161,14 @@ float64_t *----------------------------------------------------------------------------*/ struct exp32_sig64 { int_fast32_t exp; uint64_t sig; }; +FEXCORE_PRESERVE_ALL_ATTR struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t softfloat_roundPackToExtF80( bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t softfloat_normRoundPackToExtF80( bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); @@ -181,6 +190,7 @@ extFloat80_t #define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF )))) struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; }; +FEXCORE_PRESERVE_ALL_ATTR struct exp32_sig128 softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t ); diff --git a/FEXCore/Source/Common/SoftFloat-3e/primitives.h b/FEXCore/Source/Common/SoftFloat-3e/primitives.h index 863ab45b5..3d7dac3b5 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/primitives.h +++ b/FEXCore/Source/Common/SoftFloat-3e/primitives.h @@ -53,6 +53,7 @@ INLINE uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) { return a>>dist | ((a & (((uint_fast64_t) 1<>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0); } #else +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ); #endif #endif @@ -95,6 +97,7 @@ INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0); } #else +FEXCORE_PRESERVE_ALL_ATTR uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ); #endif #endif @@ -148,6 +151,7 @@ INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) return count; } #else +FEXCORE_PRESERVE_ALL_ATTR uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ); #endif #endif @@ -157,6 +161,7 @@ uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ); | Returns the number of leading 0 bits before the most-significant 1 bit of | 'a'. If 'a' is zero, 64 is returned. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ); #endif @@ -178,6 +183,7 @@ extern const uint16_t softfloat_approxRecip_1k1s[16]; #ifdef SOFTFLOAT_FAST_DIV64TO32 #define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a))) #else +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_approxRecip32_1( uint32_t a ); #endif #endif @@ -204,6 +210,7 @@ extern const uint16_t softfloat_approxRecipSqrt_1k1s[16]; | returned is also always within the range 0.5 to 1; thus, the most- | significant bit of the result is always set. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ); #endif @@ -240,6 +247,7 @@ INLINE bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); } #else +FEXCORE_PRESERVE_ALL_ATTR bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); #endif #endif @@ -255,6 +263,7 @@ INLINE bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); } #else +FEXCORE_PRESERVE_ALL_ATTR bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); #endif #endif @@ -275,6 +284,7 @@ struct uint128 return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); #endif @@ -296,6 +306,7 @@ struct uint128 return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); #endif @@ -413,6 +424,7 @@ struct uint64_extra return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint64_extra softfloat_shiftRightJam64Extra( uint64_t a, uint64_t extra, uint_fast32_t dist ); @@ -492,6 +504,7 @@ struct uint128 return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); #endif @@ -528,6 +541,7 @@ struct uint128 return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); #endif @@ -562,6 +576,7 @@ INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) return z; } #else +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ); #endif #endif @@ -570,6 +585,7 @@ struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ); /*---------------------------------------------------------------------------- | Returns the 128-bit product of 'a' and 'b'. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ); #endif diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_add128.c b/FEXCore/Source/Common/SoftFloat-3e/s_add128.c index 5a9d5082a..af999a46d 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_add128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_add128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_add128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c b/FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c index 4a326a438..612c2bc11 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. extern const uint16_t softfloat_approxRecip_1k0s[16]; extern const uint16_t softfloat_approxRecip_1k1s[16]; +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_approxRecip32_1( uint32_t a ) { int index; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c b/FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c index b3fdeba68..ea8747dca 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. extern const uint16_t softfloat_approxRecipSqrt_1k0s[]; extern const uint16_t softfloat_approxRecipSqrt_1k1s[]; +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ) { int index; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c index cb7424f43..b0d4a50ca 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c @@ -44,6 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) { struct uint128 uiZ; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF128UI.c b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF128UI.c index 7a9423bea..d4dff12fe 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF128UI.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF128UI.c @@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) { struct uint128 uiZ; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF32UI.c b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF32UI.c index ed6c2268f..f6165e451 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF32UI.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF32UI.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF64UI.c b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF64UI.c index 1182be3c9..86bbc92e0 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF64UI.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToF64UI.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros32.c b/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros32.c index 53ab22824..9de8341e3 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros32.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32 #include "primitives.h" +FEXCORE_PRESERVE_ALL_ATTR uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) { uint_fast8_t count; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros64.c b/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros64.c index 13a222463..bbc8ab0ab 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_countLeadingZeros64.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64 #include "primitives.h" +FEXCORE_PRESERVE_ALL_ATTR uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ) { uint_fast8_t count; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_extF80UIToCommonNaN.c b/FEXCore/Source/Common/SoftFloat-3e/s_extF80UIToCommonNaN.c index ab6311ef2..840e019e0 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_extF80UIToCommonNaN.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_extF80UIToCommonNaN.c @@ -46,6 +46,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_extF80UIToCommonNaN( uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_f128UIToCommonNaN.c b/FEXCore/Source/Common/SoftFloat-3e/s_f128UIToCommonNaN.c index f838f02aa..4de7cb926 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_f128UIToCommonNaN.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_f128UIToCommonNaN.c @@ -47,6 +47,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f128UIToCommonNaN( uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_f32UIToCommonNaN.c b/FEXCore/Source/Common/SoftFloat-3e/s_f32UIToCommonNaN.c index b21ba6603..67cfc30f6 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_f32UIToCommonNaN.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_f32UIToCommonNaN.c @@ -45,6 +45,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_f64UIToCommonNaN.c b/FEXCore/Source/Common/SoftFloat-3e/s_f64UIToCommonNaN.c index 6529d2ee5..c02f920ab 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_f64UIToCommonNaN.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_f64UIToCommonNaN.c @@ -45,6 +45,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_le128.c b/FEXCore/Source/Common/SoftFloat-3e/s_le128.c index 1fce7af98..15ca6f58c 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_le128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_le128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_le128 +FEXCORE_PRESERVE_ALL_ATTR bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_lt128.c b/FEXCore/Source/Common/SoftFloat-3e/s_lt128.c index d7ce3b997..d9a11c672 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_lt128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_lt128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_lt128 +FEXCORE_PRESERVE_ALL_ATTR bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_mul64ByShifted32To128.c b/FEXCore/Source/Common/SoftFloat-3e/s_mul64ByShifted32To128.c index 57e528888..c84a0fe62 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_mul64ByShifted32To128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_mul64ByShifted32To128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_mul64ByShifted32To128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) { uint_fast64_t mid; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_mul64To128.c b/FEXCore/Source/Common/SoftFloat-3e/s_mul64To128.c index 5d360aa4b..2ab3c77c7 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_mul64To128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_mul64To128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_mul64To128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ) { uint32_t a32, a0, b32, b0; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_normRoundPackToExtF80.c b/FEXCore/Source/Common/SoftFloat-3e/s_normRoundPackToExtF80.c index 76e791d91..e958105c4 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_normRoundPackToExtF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_normRoundPackToExtF80.c @@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "platform.h" #include "internals.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t softfloat_normRoundPackToExtF80( bool sign, diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalExtF80Sig.c b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalExtF80Sig.c index c1d7788b1..df0d9eaa5 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalExtF80Sig.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalExtF80Sig.c @@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "platform.h" #include "internals.h" +FEXCORE_PRESERVE_ALL_ATTR struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t sig ) { int_fast8_t shiftDist; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF128Sig.c b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF128Sig.c index 597d558cc..74c99d859 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF128Sig.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF128Sig.c @@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "platform.h" #include "internals.h" +FEXCORE_PRESERVE_ALL_ATTR struct exp32_sig128 softfloat_normSubnormalF128Sig( uint_fast64_t sig64, uint_fast64_t sig0 ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF32Sig.c b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF32Sig.c index d4bff9b41..b84572a9d 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF32Sig.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF32Sig.c @@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "platform.h" #include "internals.h" +FEXCORE_PRESERVE_ALL_ATTR struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig ) { int_fast8_t shiftDist; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF64Sig.c b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF64Sig.c index 0c63b97d5..33544e7fb 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF64Sig.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_normSubnormalF64Sig.c @@ -38,6 +38,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "platform.h" #include "internals.h" +FEXCORE_PRESERVE_ALL_ATTR struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig ) { int_fast8_t shiftDist; diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_propagateNaNExtF80UI.c b/FEXCore/Source/Common/SoftFloat-3e/s_propagateNaNExtF80UI.c index cc3f0f42c..4a2b6a8db 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_propagateNaNExtF80UI.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_propagateNaNExtF80UI.c @@ -50,6 +50,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_propagateNaNExtF80UI( uint_fast16_t uiA64, diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToExtF80.c b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToExtF80.c index 0cc7af985..1c8adcc04 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToExtF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToExtF80.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t softfloat_roundPackToExtF80( bool sign, diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF32.c b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF32.c index d1975e845..2a2c2296c 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF32.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR float32_t softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF64.c b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF64.c index 0345529cf..4ec560874 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_roundPackToF64.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR float64_t softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_roundToI32.c b/FEXCore/Source/Common/SoftFloat-3e/s_roundToI32.c index a3e727dc7..23977ce27 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_roundToI32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_roundToI32.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR int_fast32_t softfloat_roundToI32( bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_roundToI64.c b/FEXCore/Source/Common/SoftFloat-3e/s_roundToI64.c index 773c82cfc..ff6d93f56 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_roundToI64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_roundToI64.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "specialize.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR int_fast64_t softfloat_roundToI64( bool sign, diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam32.c b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam32.c index 2533fcd95..2ecdda079 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam32.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam32.c @@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shiftRightJam32 +FEXCORE_PRESERVE_ALL_ATTR uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64.c b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64.c index 4b40e3de6..c24bcdcd0 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64.c @@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shiftRightJam64 +FEXCORE_PRESERVE_ALL_ATTR uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64Extra.c b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64Extra.c index b93fad39c..833183247 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64Extra.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shiftRightJam64Extra.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shiftRightJam64Extra +FEXCORE_PRESERVE_ALL_ATTR struct uint64_extra softfloat_shiftRightJam64Extra( uint64_t a, uint64_t extra, uint_fast32_t dist ) diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftLeft128.c b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftLeft128.c index 7513bc627..94654fbde 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftLeft128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftLeft128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shortShiftLeft128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRight128.c b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRight128.c index 8f5c650b2..83f083013 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRight128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRight128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shortShiftRight128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRightJam64.c b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRightJam64.c index d3044c853..ebbb5577d 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRightJam64.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_shortShiftRightJam64.c @@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_shortShiftRightJam64 +FEXCORE_PRESERVE_ALL_ATTR uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/s_sub128.c b/FEXCore/Source/Common/SoftFloat-3e/s_sub128.c index 9bf346391..239ca6d33 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/s_sub128.c +++ b/FEXCore/Source/Common/SoftFloat-3e/s_sub128.c @@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef softfloat_sub128 +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/softfloat.h b/FEXCore/Source/Common/SoftFloat-3e/softfloat.h index b33374cd6..a36aa0771 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/softfloat.h +++ b/FEXCore/Source/Common/SoftFloat-3e/softfloat.h @@ -92,6 +92,7 @@ enum { /*---------------------------------------------------------------------------- | Routine to raise any or all of the software floating-point exception flags. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_raiseFlags( uint_fast8_t ); /*---------------------------------------------------------------------------- @@ -110,6 +111,7 @@ float16_t ui64_to_f16( uint64_t ); float32_t ui64_to_f32( uint64_t ); float64_t ui64_to_f64( uint64_t ); #ifdef SOFTFLOAT_FAST_INT64 +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t ui64_to_extF80( uint64_t ); float128_t ui64_to_f128( uint64_t ); #endif @@ -119,6 +121,7 @@ float16_t i32_to_f16( int32_t ); float32_t i32_to_f32( int32_t ); float64_t i32_to_f64( int32_t ); #ifdef SOFTFLOAT_FAST_INT64 +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t i32_to_extF80( int32_t ); float128_t i32_to_f128( int32_t ); #endif @@ -183,6 +186,7 @@ int_fast64_t f32_to_i64_r_minMag( float32_t, bool ); float16_t f32_to_f16( float32_t ); float64_t f32_to_f64( float32_t ); #ifdef SOFTFLOAT_FAST_INT64 +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f32_to_extF80( float32_t ); float128_t f32_to_f128( float32_t ); #endif @@ -218,6 +222,7 @@ int_fast64_t f64_to_i64_r_minMag( float64_t, bool ); float16_t f64_to_f16( float64_t ); float32_t f64_to_f32( float64_t ); #ifdef SOFTFLOAT_FAST_INT64 +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f64_to_extF80( float64_t ); float128_t f64_to_f128( float64_t ); #endif @@ -250,26 +255,41 @@ extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision; *----------------------------------------------------------------------------*/ #ifdef SOFTFLOAT_FAST_INT64 uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool ); +FEXCORE_PRESERVE_ALL_ATTR uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool ); +FEXCORE_PRESERVE_ALL_ATTR int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool ); +FEXCORE_PRESERVE_ALL_ATTR int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool ); uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool ); uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool ); int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool ); int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool ); float16_t extF80_to_f16( extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR float32_t extF80_to_f32( extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR float64_t extF80_to_f64( extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR float128_t extF80_to_f128( extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_add( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_sub( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_mul( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_div( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_rem( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t extF80_sqrt( extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR bool extF80_eq( extFloat80_t, extFloat80_t ); bool extF80_le( extFloat80_t, extFloat80_t ); +FEXCORE_PRESERVE_ALL_ATTR bool extF80_lt( extFloat80_t, extFloat80_t ); bool extF80_eq_signaling( extFloat80_t, extFloat80_t ); bool extF80_le_quiet( extFloat80_t, extFloat80_t ); @@ -320,6 +340,7 @@ int_fast64_t f128_to_i64_r_minMag( float128_t, bool ); float16_t f128_to_f16( float128_t ); float32_t f128_to_f32( float128_t ); float64_t f128_to_f64( float128_t ); +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t f128_to_extF80( float128_t ); float128_t f128_roundToInt( float128_t, uint_fast8_t, bool ); float128_t f128_add( float128_t, float128_t ); diff --git a/FEXCore/Source/Common/SoftFloat-3e/softfloat_raiseFlags.c b/FEXCore/Source/Common/SoftFloat-3e/softfloat_raiseFlags.c index 3115306be..0ba2871ea 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/softfloat_raiseFlags.c +++ b/FEXCore/Source/Common/SoftFloat-3e/softfloat_raiseFlags.c @@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | to substitute a result value. If traps are not implemented, this routine | should be simply `softfloat_exceptionFlags |= flags;'. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_raiseFlags( uint_fast8_t flags ) { diff --git a/FEXCore/Source/Common/SoftFloat-3e/specialize.h b/FEXCore/Source/Common/SoftFloat-3e/specialize.h index 5fe119a1e..8db0b2725 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/specialize.h +++ b/FEXCore/Source/Common/SoftFloat-3e/specialize.h @@ -135,12 +135,14 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); /*---------------------------------------------------------------------------- @@ -170,12 +172,14 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); /*---------------------------------------------------------------------------- @@ -215,6 +219,7 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_extF80UIToCommonNaN( uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); @@ -224,6 +229,7 @@ void | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); /*---------------------------------------------------------------------------- @@ -235,6 +241,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_propagateNaNExtF80UI( uint_fast16_t uiA64, @@ -264,6 +271,7 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR void softfloat_f128UIToCommonNaN( uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); @@ -272,6 +280,7 @@ void | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ +FEXCORE_PRESERVE_ALL_ATTR struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); /*---------------------------------------------------------------------------- diff --git a/FEXCore/Source/Common/SoftFloat-3e/ui64_to_extF80.c b/FEXCore/Source/Common/SoftFloat-3e/ui64_to_extF80.c index b0e932fed..fc976bb30 100644 --- a/FEXCore/Source/Common/SoftFloat-3e/ui64_to_extF80.c +++ b/FEXCore/Source/Common/SoftFloat-3e/ui64_to_extF80.c @@ -39,6 +39,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "internals.h" #include "softfloat.h" +FEXCORE_PRESERVE_ALL_ATTR extFloat80_t ui64_to_extF80( uint64_t a ) { uint_fast16_t uiZ64; From 8aa8d597f67744a995662593a2838014c074cc8e Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:17:12 -0700 Subject: [PATCH 5/7] Arm64: Supports jumping out of the JIT with preserve_all ABI This improves perferformance when jumping out of the Arm64 JIT by reducing the number of registers we need to save. --- .../Core/ArchHelpers/Arm64Emitter.cpp | 465 +++++++++++++++--- .../Interface/Core/ArchHelpers/Arm64Emitter.h | 40 ++ .../Core/Interpreter/InterpreterOps.h | 1 + .../Source/Interface/Core/JIT/Arm64/JIT.cpp | 116 ++--- 4 files changed, 459 insertions(+), 163 deletions(-) diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp index 25e89b8fe..f8284b536 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp @@ -1,6 +1,7 @@ #include "Interface/Core/ArchHelpers/Arm64Emitter.h" #include "FEXCore/Utils/AllocatorHooks.h" #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" +#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Context/Context.h" #include "Interface/HLE/Thunks/Thunks.h" @@ -78,6 +79,97 @@ namespace x64 { FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, }; + + // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15. + // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI. + constexpr std::array PreserveAll_SRA = { + FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, + FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7, + FEXCore::ARMEmitter::Reg::r8, + FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, + }; + + constexpr uint32_t PreserveAll_SRAMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRA) { + switch (Reg.Idx()) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 16: + case 17: + Mask |= (1U << Reg.Idx()); + break; + default: break; + } + } + + return Mask; + }() + }; + + // Dynamic GPRs + constexpr std::array PreserveAll_Dynamic = { + // Only LR needs to get saved. + FEXCore::ARMEmitter::Reg::r30 + }; + + // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI. + constexpr std::array PreserveAll_SRAFPR = { + // None. + }; + + constexpr uint32_t PreserveAll_SRAFPRMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRAFPR) { + Mask |= (1U << Reg.Idx()); + } + return Mask; + }() + }; + + // Dynamic FPRs + // - v0-v7 + constexpr std::array PreserveAll_DynamicFPR = { + // v0 ~ v1 are temps + FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, + FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, + FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + }; + + // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI. + // This is /all/ of the SRA registers + constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; + + constexpr uint32_t PreserveAll_SRAFPRSVEMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRAFPRSVE) { + Mask |= (1U << Reg.Idx()); + } + return Mask; + }() + }; + + // Dynamic FPRs when the host supports SVE-256bit. + constexpr std::array PreserveAll_DynamicFPRSVE = { + // v0 ~ v1 are used as temps. + FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, + FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, + FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, + FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, + FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, + FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + }; } namespace x32 { @@ -144,6 +236,101 @@ namespace x32 { FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31 }; + + // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15. + // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI. + constexpr std::array PreserveAll_SRA = { + FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, + FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7, + FEXCore::ARMEmitter::Reg::r8, + }; + + constexpr uint32_t PreserveAll_SRAMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRA) { + switch (Reg.Idx()) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 16: + case 17: + Mask |= (1U << Reg.Idx()); + break; + default: break; + } + } + + return Mask; + }() + }; + + // Dynamic GPRs + constexpr std::array PreserveAll_Dynamic = { + FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, + FEXCore::ARMEmitter::Reg::r30 + }; + + // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI. + constexpr std::array PreserveAll_SRAFPR = { + // None. + }; + + constexpr uint32_t PreserveAll_SRAFPRMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRAFPR) { + Mask |= (1U << Reg.Idx()); + } + return Mask; + }() + }; + + // Dynamic FPRs + // - v0-v7 + constexpr std::array PreserveAll_DynamicFPR = { + // v0 ~ v1 are temps + FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, + FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, + FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + }; + + // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI. + // This is /all/ of the SRA registers + constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; + + constexpr uint32_t PreserveAll_SRAFPRSVEMask = { + []() -> uint32_t { + uint32_t Mask{}; + for (auto Reg : PreserveAll_SRAFPRSVE) { + Mask |= (1U << Reg.Idx()); + } + return Mask; + }() + }; + + // Dynamic FPRs when the host supports SVE-256bit. + constexpr std::array PreserveAll_DynamicFPRSVE = { + // v0 ~ v1 are used as temps. + FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, + FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, + FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, + FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, + FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, + FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + + FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, + FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, + FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, + FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31 + }; } // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one. @@ -532,6 +719,107 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF } } +void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs) { + if (SVERegs) { + size_t i = 0; + + for (; i < (VRegs.size() % 4); i += 2) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0); + add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2); + } + + for (; i < VRegs.size(); i += 4) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + const auto Reg3 = VRegs[i + 2]; + const auto Reg4 = VRegs[i + 3]; + st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0); + add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4); + } + } + else { + size_t i = 0; + for (; i < (VRegs.size() % 4); i += 2) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + st1(Reg1.Q(), Reg2.Q(), TmpReg, 32); + } + + for (; i < VRegs.size(); i += 4) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + const auto Reg3 = VRegs[i + 2]; + const auto Reg4 = VRegs[i + 3]; + st1(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64); + } + } +} + +void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span Regs) { + size_t i = 0; + for (; i < (Regs.size() % 2); ++i) { + const auto Reg1 = Regs[i]; + str(Reg1.X(), TmpReg, 16); + } + + for (; i < Regs.size(); i += 2) { + const auto Reg1 = Regs[i]; + const auto Reg2 = Regs[i + 1]; + stp(Reg1.X(), Reg2.X(), TmpReg, 16); + } +} + +void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span VRegs) { + if (SVERegs) { + size_t i = 0; + for (; i < (VRegs.size() % 4); i += 2) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp); + add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2); + } + + for (; i < VRegs.size(); i += 4) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + const auto Reg3 = VRegs[i + 2]; + const auto Reg4 = VRegs[i + 3]; + ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp); + add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4); + } + } else { + size_t i = 0; + for (; i < (VRegs.size() % 4); i += 2) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + ld1(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32); + } + + for (; i < VRegs.size(); i += 4) { + const auto Reg1 = VRegs[i]; + const auto Reg2 = VRegs[i + 1]; + const auto Reg3 = VRegs[i + 2]; + const auto Reg4 = VRegs[i + 3]; + ld1(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64); + } + } +} + +void Arm64Emitter::PopGeneralRegisters(std::span Regs) { + size_t i = 0; + for (; i < (Regs.size() % 2); ++i) { + const auto Reg1 = Regs[i]; + ldr(Reg1.X(), ARMEmitter::Reg::rsp, 16); + } + for (; i < Regs.size(); i += 2) { + const auto Reg1 = Regs[i]; + const auto Reg2 = Regs[i + 1]; + ldp(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16); + } +} + void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) { const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; const auto GPRSize = (ConfiguredDynamicRegisterBase.size() + 1) * Core::CPUState::GPR_REG_SIZE; @@ -547,46 +835,11 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) { LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 2 == 0, "Needs to have multiple of 2 FPRs for RA"); - if (CanUseSVE) { - size_t i = 0; + // Push the vector registers + PushVectorRegisters(TmpReg, CanUseSVE, GeneralFPRegisters); - for (; i < (GeneralFPRegisters.size() % 4); i += 2) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0); - add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2); - } - - for (; i < GeneralFPRegisters.size(); i += 4) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - const auto Reg3 = GeneralFPRegisters[i + 2]; - const auto Reg4 = GeneralFPRegisters[i + 3]; - st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0); - add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4); - } - } else { - size_t i = 0; - for (; i < (GeneralFPRegisters.size() % 4); i += 2) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - st1(Reg1.Q(), Reg2.Q(), TmpReg, 32); - } - - for (; i < GeneralFPRegisters.size(); i += 4) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - const auto Reg3 = GeneralFPRegisters[i + 2]; - const auto Reg4 = GeneralFPRegisters[i + 3]; - st1(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64); - } - } - - for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) { - const auto Reg1 = ConfiguredDynamicRegisterBase[i]; - const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1]; - stp(Reg1.X(), Reg2.X(), TmpReg, 16); - } + // Push the general registers. + PushGeneralRegisters(TmpReg, ConfiguredDynamicRegisterBase); str(ARMEmitter::XReg::lr, TmpReg, 0); } @@ -594,49 +847,107 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) { void Arm64Emitter::PopDynamicRegsAndLR() { const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; - if (CanUseSVE) { - size_t i = 0; - for (; i < (GeneralFPRegisters.size() % 4); i += 2) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp); - add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2); - } + // Pop vectors first + PopVectorRegisters(CanUseSVE, GeneralFPRegisters); - for (; i < GeneralFPRegisters.size(); i += 4) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - const auto Reg3 = GeneralFPRegisters[i + 2]; - const auto Reg4 = GeneralFPRegisters[i + 3]; - ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp); - add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4); - } - } else { - size_t i = 0; - for (; i < (GeneralFPRegisters.size() % 4); i += 2) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - ld1(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32); - } - - for (; i < GeneralFPRegisters.size(); i += 4) { - const auto Reg1 = GeneralFPRegisters[i]; - const auto Reg2 = GeneralFPRegisters[i + 1]; - const auto Reg3 = GeneralFPRegisters[i + 2]; - const auto Reg4 = GeneralFPRegisters[i + 3]; - ld1(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64); - } - } - - for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) { - const auto Reg1 = ConfiguredDynamicRegisterBase[i]; - const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1]; - ldp(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16); - } + // Pop GPRs second + PopGeneralRegisters(ConfiguredDynamicRegisterBase); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); } +void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs) { + const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; + const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE + : Core::CPUState::XMM_SSE_REG_SIZE; + + std::span DynamicGPRs{}; + std::span DynamicFPRs{}; + uint32_t PreserveSRAMask{}; + uint32_t PreserveSRAFPRMask{}; + if (EmitterCTX->Config.Is64BitMode()) { + DynamicGPRs = x64::PreserveAll_Dynamic; + DynamicFPRs = x64::PreserveAll_DynamicFPR; + PreserveSRAMask = x64::PreserveAll_SRAMask; + PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask; + + if (CanUseSVE) { + DynamicFPRs = x64::PreserveAll_DynamicFPRSVE; + PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask; + } + } + else { + DynamicGPRs = x32::PreserveAll_Dynamic; + DynamicFPRs = x32::PreserveAll_DynamicFPR; + PreserveSRAMask = x32::PreserveAll_SRAMask; + PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask; + + if (CanUseSVE) { + DynamicFPRs = x32::PreserveAll_DynamicFPRSVE; + PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask; + } + } + + const auto GPRSize = AlignUp(DynamicGPRs.size(), 2) * Core::CPUState::GPR_REG_SIZE; + const auto FPRSize = DynamicFPRs.size() * FPRRegSize; + const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16); + + // Spill the static registers. + SpillStaticRegs(TmpReg, true, PreserveSRAMask, PreserveSRAFPRMask); + + sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset); + + // rsp capable move + add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0); + + // Push the vector registers. + PushVectorRegisters(TmpReg, CanUseSVE, DynamicFPRs); + + // Push the general registers. + PushGeneralRegisters(TmpReg, DynamicGPRs); +} + +void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) { + const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; + + std::span DynamicGPRs{}; + std::span DynamicFPRs{}; + uint32_t PreserveSRAMask{}; + uint32_t PreserveSRAFPRMask{}; + + if (EmitterCTX->Config.Is64BitMode()) { + DynamicGPRs = x64::PreserveAll_Dynamic; + DynamicFPRs = x64::PreserveAll_DynamicFPR; + PreserveSRAMask = x64::PreserveAll_SRAMask; + PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask; + + if (CanUseSVE) { + DynamicFPRs = x64::PreserveAll_DynamicFPRSVE; + PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask; + } + } + else { + DynamicGPRs = x32::PreserveAll_Dynamic; + DynamicFPRs = x32::PreserveAll_DynamicFPR; + PreserveSRAMask = x32::PreserveAll_SRAMask; + PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask; + + if (CanUseSVE) { + DynamicFPRs = x32::PreserveAll_DynamicFPRSVE; + PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask; + } + } + + // Fill the static registers. + FillStaticRegs(true, PreserveSRAMask, PreserveSRAFPRMask); + + // Pop the vector registers. + PopVectorRegisters(CanUseSVE, DynamicFPRs); + + // Pop the general registers. + PopGeneralRegisters(DynamicGPRs); +} + void Arm64Emitter::Align16B() { uint64_t CurrentOffset = GetCursorAddress(); for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) { diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h index 14357394e..860ac6074 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h @@ -97,12 +97,52 @@ protected: // We can't guarantee only the lower 64bits are used so flush everything static constexpr uint32_t CALLER_FPR_MASK = ~0U; + // Generic push and pop vector registers. + void PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs); + void PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span Regs); + + void PopVectorRegisters(bool SVERegs, std::span VRegs); + void PopGeneralRegisters(std::span Regs); + void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg); void PopDynamicRegsAndLR(); void PushCalleeSavedRegisters(); void PopCalleeSavedRegisters(); + // Spills and fills SRA/Dynamic registers that are required for Arm64 `preserve_all` ABI. + // This ABI changes most registers to be callee saved. + // Caller Saved: + // - X0-X8, X16-X18. + // - v0-v7 + // - For 256-bit SVE hosts: top 128-bits of v8-v31 + // + // Callee Saved: + // - X9-X15, X19-X31 + // - Low 128-bits of v8-v31 + void SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true); + void FillForPreserveAllABICall(bool FPRs = true); + + void SpillForABICall(bool SupportsPreserveAllABI, FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true) { + if (SupportsPreserveAllABI) { + SpillForPreserveAllABICall(TMP1, true); + } + else { + SpillStaticRegs(TMP1); + PushDynamicRegsAndLR(TMP1); + } + } + + void FillForABICall(bool SupportsPreserveAllABI, bool FPRs = true) { + if (SupportsPreserveAllABI) { + FillForPreserveAllABICall(true); + } + else { + PopDynamicRegsAndLR(); + FillStaticRegs(); + } + } + void Align16B(); #ifdef VIXL_SIMULATOR diff --git a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h index 3ff425f60..c47ae435c 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h +++ b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h @@ -46,6 +46,7 @@ namespace FEXCore::CPU { FallbackABI ABI; void *fn; FEXCore::Core::FallbackHandlerIndex HandlerIndex; + bool SupportsPreserveAllABI; }; class InterpreterOps { diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index 802a016d1..edd9f186c 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -84,9 +84,8 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } else { switch(Info.ABI) { case FABI_F80_I16_F32:{ - SpillStaticRegs(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); - PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); fmov(ARMEmitter::SReg::s0, Src1.S()); ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); @@ -97,9 +96,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r1); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); eor(Dst.Q(), Dst.Q(), Dst.Q()); @@ -109,9 +106,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_F80_I16_F64:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); mov(ARMEmitter::DReg::d0, Src1.D()); @@ -123,9 +118,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r1); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); eor(Dst.Q(), Dst.Q(), Dst.Q()); @@ -136,9 +129,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { case FABI_F80_I16_I16: case FABI_F80_I16_I32: { - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetReg(IROp->Args[0].ID()); ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); @@ -155,9 +146,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r2); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); eor(Dst.Q(), Dst.Q(), Dst.Q()); @@ -167,9 +156,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_F32_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -184,9 +171,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r3); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); fmov(Dst.S(), ARMEmitter::SReg::s0); @@ -194,9 +179,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_F64_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -211,9 +194,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r3); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); mov(Dst.D(), ARMEmitter::DReg::d0); @@ -221,9 +202,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_F64_I16_F64: { - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -236,9 +215,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r1); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); mov(Dst.D(), ARMEmitter::DReg::d0); @@ -246,9 +223,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_F64_I16_F64_F64: { - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); const auto Src2 = GetVReg(IROp->Args[1].ID()); @@ -263,9 +238,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r1); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); mov(Dst.D(), ARMEmitter::DReg::d0); @@ -273,9 +246,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { break; case FABI_I16_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -290,18 +261,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r3); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); sxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; case FABI_I32_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -316,18 +283,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r3); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); mov(ARMEmitter::Size::i32Bit, Dst, ARMEmitter::Reg::r0); } break; case FABI_I64_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -341,19 +304,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { #else blr(ARMEmitter::Reg::r3); #endif - - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; case FABI_I64_I16_F80_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); const auto Src2 = GetVReg(IROp->Args[1].ID()); @@ -371,18 +329,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { #else blr(ARMEmitter::Reg::r5); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; case FABI_F80_I16_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); @@ -397,9 +351,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r3); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); eor(Dst.Q(), Dst.Q(), Dst.Q()); @@ -408,9 +360,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; case FABI_F80_I16_F80_F80:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Src1 = GetVReg(IROp->Args[0].ID()); const auto Src2 = GetVReg(IROp->Args[1].ID()); @@ -429,9 +379,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r5); #endif - PopDynamicRegsAndLR(); - - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetVReg(Node); eor(Dst.Q(), Dst.Q(), Dst.Q()); @@ -440,8 +388,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; case FABI_I32_I64_I64_I128_I128_I16: { - SpillStaticRegs(TMP1); - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Op = IROp->C(); const auto Control = Op->Control; @@ -469,16 +416,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r7); #endif - PopDynamicRegsAndLR(); - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); mov(Dst.W(), ARMEmitter::WReg::w0); break; } case FABI_I32_I128_I128_I16: { - SpillStaticRegs(TMP1); - PushDynamicRegsAndLR(TMP1); + SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true); const auto Op = IROp->C(); @@ -501,8 +446,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { blr(ARMEmitter::Reg::r5); #endif - PopDynamicRegsAndLR(); - FillStaticRegs(); + FillForABICall(Info.SupportsPreserveAllABI, true); const auto Dst = GetReg(Node); mov(Dst.W(), ARMEmitter::WReg::w0); From d588d41ab9d41357718d8e6e5a57e3f8c54af2bb Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:18:23 -0700 Subject: [PATCH 6/7] InterpreterFallbacks: Converts X87 and String ops to preserve_all This improves performance! --- FEXCore/Source/Common/SoftFloat.h | 19 ++ .../Core/Interpreter/Fallbacks/F80Fallbacks.h | 37 ++- .../Fallbacks/InterpreterFallbacks.cpp | 254 +++++++----------- .../Interpreter/Fallbacks/VectorFallbacks.h | 12 + 4 files changed, 161 insertions(+), 161 deletions(-) diff --git a/FEXCore/Source/Common/SoftFloat.h b/FEXCore/Source/Common/SoftFloat.h index 31c35d0ad..aebcc78eb 100644 --- a/FEXCore/Source/Common/SoftFloat.h +++ b/FEXCore/Source/Common/SoftFloat.h @@ -62,6 +62,7 @@ struct FEX_PACKED X80SoftFloat { } // Ops + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #ifdef DEBUG_X86_FLOAT BIGFLOAT Result; @@ -83,6 +84,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #ifdef DEBUG_X86_FLOAT BIGFLOAT Result; @@ -104,6 +106,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #ifdef DEBUG_X86_FLOAT BIGFLOAT Result; @@ -125,6 +128,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #ifdef DEBUG_X86_FLOAT BIGFLOAT Result; @@ -146,6 +150,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #if defined(DEBUG_X86_FLOAT) BIGFLOAT Result; @@ -168,6 +173,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { #if defined(DEBUG_X86_FLOAT) BIGFLOAT Result; @@ -190,14 +196,17 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) { return extF80_roundToInt(lhs, softfloat_roundingMode, false); } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(X80SoftFloat const &lhs, uint_fast8_t RoundMode) { return extF80_roundToInt(lhs, RoundMode, false); } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) { #if defined(DEBUG_X86_FLOAT) BIGFLOAT Result; @@ -221,6 +230,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_EXP(X80SoftFloat const &lhs) { #if defined(DEBUG_X86_FLOAT) BIGFLOAT Result; @@ -242,12 +252,14 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static void FCMP(X80SoftFloat const &lhs, X80SoftFloat const &rhs, bool *eq, bool *lt, bool *nan) { *eq = extF80_eq(lhs, rhs); *lt = extF80_lt(lhs, rhs); *nan = IsNan(lhs) || IsNan(rhs); } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -276,6 +288,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat F2XM1(X80SoftFloat const &lhs) { WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -299,6 +312,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -324,6 +338,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(X80SoftFloat const &lhs, X80SoftFloat const &rhs) { WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -349,6 +364,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(X80SoftFloat const &lhs) { WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -372,6 +388,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(X80SoftFloat const &lhs) { WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -394,6 +411,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(X80SoftFloat const &lhs) { WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems"); #ifdef DEBUG_X86_FLOAT @@ -416,6 +434,7 @@ struct FEX_PACKED X80SoftFloat { #endif } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(X80SoftFloat const &lhs) { #ifdef DEBUG_X86_FLOAT BIGFLOAT Result; diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h index a31b5f657..69ee572d3 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h @@ -7,6 +7,7 @@ #include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h" namespace FEXCore::CPU { +FEXCORE_PRESERVE_ALL_ATTR static void LoadDeferredFCW(uint16_t NewFCW) { auto PC = (NewFCW >> 8) & 3; switch(PC) { @@ -35,11 +36,13 @@ static void LoadDeferredFCW(uint16_t NewFCW) { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t NewFCW, float src) { LoadDeferredFCW(NewFCW); return src; } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle8(uint16_t NewFCW, double src) { LoadDeferredFCW(NewFCW); return src; @@ -49,6 +52,7 @@ struct OpHandlers { template<> struct OpHandlers { template + FEXCORE_PRESERVE_ALL_ATTR static uint64_t handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); @@ -74,11 +78,13 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static float handle4(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return src; } + FEXCORE_PRESERVE_ALL_ATTR static double handle8(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return src; @@ -87,22 +93,26 @@ struct OpHandlers { template<> struct OpHandlers { - static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) { + FEXCORE_PRESERVE_ALL_ATTR + static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return src; } + FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return src; } + FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return src; } - static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) { + FEXCORE_PRESERVE_ALL_ATTR + static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); auto rv = extF80_to_i32(src, softfloat_round_minMag, false); @@ -115,11 +125,13 @@ struct OpHandlers { } } + FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4t(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return extF80_to_i32(src, softfloat_round_minMag, false); } + FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8t(uint16_t NewFCW, X80SoftFloat src) { LoadDeferredFCW(NewFCW); return extF80_to_i64(src, softfloat_round_minMag, false); @@ -128,11 +140,13 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle2(uint16_t NewFCW, int16_t src) { LoadDeferredFCW(NewFCW); return src; } + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t NewFCW, int32_t src) { LoadDeferredFCW(NewFCW); return src; @@ -141,6 +155,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FRNDINT(Src1); @@ -149,6 +164,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::F2XM1(Src1); @@ -157,6 +173,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FTAN(Src1); @@ -165,6 +182,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FSQRT(Src1); @@ -173,6 +191,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FSIN(Src1); @@ -181,6 +200,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FCOS(Src1); @@ -189,6 +209,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FXTRACT_EXP(Src1); @@ -197,6 +218,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FXTRACT_SIG(Src1); @@ -205,6 +227,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FADD(Src1, Src2); @@ -213,6 +236,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FSUB(Src1, Src2); @@ -221,6 +245,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FMUL(Src1, Src2); @@ -229,6 +254,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FDIV(Src1, Src2); @@ -237,6 +263,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FYL2X(Src1, Src2); @@ -245,6 +272,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FATAN(Src1, Src2); @@ -253,6 +281,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FREM1(Src1, Src2); @@ -261,6 +290,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FREM(Src1, Src2); @@ -269,6 +299,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { LoadDeferredFCW(NewFCW); return X80SoftFloat::FSCALE(Src1, Src2); @@ -350,6 +381,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { LoadDeferredFCW(NewFCW); bool Negative = Src1.Sign; @@ -391,6 +423,7 @@ struct OpHandlers { template<> struct OpHandlers { + FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src) { LoadDeferredFCW(NewFCW); uint8_t *Src1 = reinterpret_cast(&Src); diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp index 460ec227f..69b06d30e 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp @@ -11,148 +11,78 @@ namespace FEXCore::CPU { template static FallbackInfo GetFallbackInfo(R(*fn)(Args...), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_UNKNOWN, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_F32, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_F64, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_I16, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_I32, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(float(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F32_I16_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_I16_F80, (void*)fn, HandlerIndex}; + return {FABI_UNKNOWN, (void*)fn, HandlerIndex, false}; } template<> FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_I16_F64, (void*)fn, HandlerIndex}; + return {FABI_F64_I16_F64, (void*)fn, HandlerIndex, false}; } template<> FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double,double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_I16_F64_F64, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(int16_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I16_I16_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(int32_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I32_I16_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(int64_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I64_I16_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(uint64_t(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I64_I16_F80_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16_F80_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(uint32_t(*fn)(uint64_t, uint64_t, __uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I32_I64_I64_I128_I128_I16, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I32_I128_I128_I16, (void*)fn, HandlerIndex}; + return {FABI_F64_I16_F64_F64, (void*)fn, HandlerIndex, false}; } void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) { - Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTO_4).fn); - Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTTO_8).fn); - Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVT_4).fn); - Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVT_8).fn); - Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTINT_2).fn); - Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTINT_4).fn); - Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTINT_8).fn); - Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2).fn); - Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4).fn); - Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8).fn); - Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<0>, Core::OPINDEX_F80CMP_0).fn); - Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<1>, Core::OPINDEX_F80CMP_1).fn); - Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<2>, Core::OPINDEX_F80CMP_2).fn); - Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<3>, Core::OPINDEX_F80CMP_3).fn); - Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<4>, Core::OPINDEX_F80CMP_4).fn); - Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<5>, Core::OPINDEX_F80CMP_5).fn); - Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<6>, Core::OPINDEX_F80CMP_6).fn); - Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle<7>, Core::OPINDEX_F80CMP_7).fn); - Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTTOINT_2).fn); - Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTOINT_4).fn); + Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle4); + Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle8); + Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle4); + Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle8); + Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle2); + Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle4); + Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle8); + Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle2t); + Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle4t); + Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle8t); + Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<0>); + Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<1>); + Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<2>); + Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<3>); + Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<4>); + Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<5>); + Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<6>); + Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle<7>); + Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle2); + Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle4); // Unary - Info[Core::OPINDEX_F80ROUND] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80ROUND).fn); - Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80F2XM1).fn); - Info[Core::OPINDEX_F80TAN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80TAN).fn); - Info[Core::OPINDEX_F80SQRT] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80SQRT).fn); - Info[Core::OPINDEX_F80SIN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80SIN).fn); - Info[Core::OPINDEX_F80COS] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80COS).fn); - Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80XTRACT_EXP).fn); - Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80XTRACT_SIG).fn); - Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80BCDSTORE).fn); - Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80BCDLOAD).fn); + Info[Core::OPINDEX_F80ROUND] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80TAN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80SQRT] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80SIN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80COS] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); // Binary - Info[Core::OPINDEX_F80ADD] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80ADD).fn); - Info[Core::OPINDEX_F80SUB] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80SUB).fn); - Info[Core::OPINDEX_F80MUL] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80MUL).fn); - Info[Core::OPINDEX_F80DIV] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80DIV).fn); - Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80FYL2X).fn); - Info[Core::OPINDEX_F80ATAN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80ATAN).fn); - Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80FPREM1).fn); - Info[Core::OPINDEX_F80FPREM] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80FPREM).fn); - Info[Core::OPINDEX_F80SCALE] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80SCALE).fn); + Info[Core::OPINDEX_F80ADD] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80SUB] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80MUL] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80DIV] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80ATAN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80FPREM] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F80SCALE] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); // Double Precision - Info[Core::OPINDEX_F64SIN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64SIN).fn); - Info[Core::OPINDEX_F64COS] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64COS).fn); - Info[Core::OPINDEX_F64TAN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64TAN).fn); - Info[Core::OPINDEX_F64ATAN] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64ATAN).fn); - Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64F2XM1).fn); - Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64FYL2X).fn); - Info[Core::OPINDEX_F64FPREM] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64FPREM).fn); - Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64FPREM1).fn); - Info[Core::OPINDEX_F64SCALE] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F64SCALE).fn); + Info[Core::OPINDEX_F64SIN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64COS] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64TAN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64ATAN] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64FPREM] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_F64SCALE] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); // SSE4.2 string instructions - Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPESTRX).fn); - Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPISTRX).fn); + Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); + Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast(&FEXCore::CPU::OpHandlers::handle); } bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) { @@ -163,11 +93,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf switch (Op->SrcSize) { case 4: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTO_4); + *Info = {FABI_F80_I16_F32, (void*)&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTO_4, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } case 8: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTTO_8); + *Info = {FABI_F80_I16_F64, (void*)&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTTO_8, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize); @@ -177,11 +107,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf case IR::OP_F80CVT: { switch (OpSize) { case 4: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVT_4); + *Info = {FABI_F32_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } case 8: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVT_8); + *Info = {FABI_F64_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize); @@ -194,28 +124,28 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf switch (OpSize) { case 2: { if (Op->Truncate) { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2); + *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } else { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTINT_2); + *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } return true; } case 4: { if (Op->Truncate) { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4); + *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } else { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTINT_4); + *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } return true; } case 8: { if (Op->Truncate) { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8); + *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } else { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTINT_8); + *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTINT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR}; } return true; } @@ -237,7 +167,7 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf &FEXCore::CPU::OpHandlers::handle<7>, }; - *Info = GetFallbackInfo(handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags)); + *Info = {FABI_I64_I16_F80_F80, (void*)handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags), FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } @@ -246,11 +176,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf switch (Op->SrcSize) { case 2: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTTOINT_2); + *Info = {FABI_F80_I16_I16, (void*)&FEXCore::CPU::OpHandlers::handle2, Core::OPINDEX_F80CVTTOINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } case 4: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTOINT_4); + *Info = {FABI_F80_I16_I32, (void*)&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTOINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; } default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize); @@ -258,9 +188,15 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf break; } -#define COMMON_X87_OP(OP) \ +#define COMMON_UNARY_X87_OP(OP) \ case IR::OP_F80##OP: { \ - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80##OP); \ + *Info = {FABI_F80_I16_F80, (void*)&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \ + return true; \ + } + +#define COMMON_BINARY_X87_OP(OP) \ + case IR::OP_F80##OP: { \ + *Info = {FABI_F80_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \ return true; \ } @@ -271,27 +207,27 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf } // Unary - COMMON_X87_OP(ROUND) - COMMON_X87_OP(F2XM1) - COMMON_X87_OP(TAN) - COMMON_X87_OP(SQRT) - COMMON_X87_OP(SIN) - COMMON_X87_OP(COS) - COMMON_X87_OP(XTRACT_EXP) - COMMON_X87_OP(XTRACT_SIG) - COMMON_X87_OP(BCDSTORE) - COMMON_X87_OP(BCDLOAD) + COMMON_UNARY_X87_OP(ROUND) + COMMON_UNARY_X87_OP(F2XM1) + COMMON_UNARY_X87_OP(TAN) + COMMON_UNARY_X87_OP(SQRT) + COMMON_UNARY_X87_OP(SIN) + COMMON_UNARY_X87_OP(COS) + COMMON_UNARY_X87_OP(XTRACT_EXP) + COMMON_UNARY_X87_OP(XTRACT_SIG) + COMMON_UNARY_X87_OP(BCDSTORE) + COMMON_UNARY_X87_OP(BCDLOAD) // Binary - COMMON_X87_OP(ADD) - COMMON_X87_OP(SUB) - COMMON_X87_OP(MUL) - COMMON_X87_OP(DIV) - COMMON_X87_OP(FYL2X) - COMMON_X87_OP(ATAN) - COMMON_X87_OP(FPREM1) - COMMON_X87_OP(FPREM) - COMMON_X87_OP(SCALE) + COMMON_BINARY_X87_OP(ADD) + COMMON_BINARY_X87_OP(SUB) + COMMON_BINARY_X87_OP(MUL) + COMMON_BINARY_X87_OP(DIV) + COMMON_BINARY_X87_OP(FYL2X) + COMMON_BINARY_X87_OP(ATAN) + COMMON_BINARY_X87_OP(FPREM1) + COMMON_BINARY_X87_OP(FPREM) + COMMON_BINARY_X87_OP(SCALE) // Double Precision Unary COMMON_F64_OP(F2XM1) @@ -308,10 +244,10 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf // SSE4.2 Fallbacks case IR::OP_VPCMPESTRX: - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPESTRX); + *Info = {FABI_I32_I64_I64_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPESTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; case IR::OP_VPCMPISTRX: - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPISTRX); + *Info = {FABI_I32_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_VPCMPISTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR}; return true; default: diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h index 373f84b95..1adb6a4dc 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h @@ -35,6 +35,7 @@ struct OpHandlers { NegativeMasked, }; + FEXCORE_PRESERVE_ALL_ATTR static uint32_t handle(uint64_t RAX, uint64_t RDX, __uint128_t lhs, __uint128_t rhs, uint16_t control) { // Subtract by 1 in order to make validity limits 0-based const auto valid_lhs = GetExplicitLength(RAX, control) - 1; @@ -44,6 +45,7 @@ struct OpHandlers { } // Main PCMPXSTRX algorithm body. Allows for reuse with both implicit and explicit length variants. + FEXCORE_PRESERVE_ALL_ATTR static uint32_t MainBody(const __uint128_t& lhs, int valid_lhs, const __uint128_t& rhs, int valid_rhs, uint16_t control) { const uint32_t aggregation = PerformAggregation(lhs, valid_lhs, rhs, valid_rhs, control); const int32_t upper_limit = (16 >> (control & 1)) - 1; @@ -68,6 +70,7 @@ struct OpHandlers { return result | (flags << 16); } + FEXCORE_PRESERVE_ALL_ATTR static int32_t GetExplicitLength(uint64_t reg, uint16_t control) { // Bit 8 controls whether or not the reg value is 64-bit or 32-bit. int64_t value = 0; @@ -91,6 +94,7 @@ struct OpHandlers { return std::abs(static_cast(value)); } + FEXCORE_PRESERVE_ALL_ATTR static int32_t GetElement(const __uint128_t& vec, int32_t index, uint16_t control) { const auto* vec_ptr = reinterpret_cast(&vec); @@ -114,6 +118,7 @@ struct OpHandlers { } } + FEXCORE_PRESERVE_ALL_ATTR static uint32_t PerformAggregation(const __uint128_t& lhs, int32_t valid_lhs, const __uint128_t& rhs, int32_t valid_rhs, uint16_t control) { @@ -130,6 +135,7 @@ struct OpHandlers { } } + FEXCORE_PRESERVE_ALL_ATTR static uint32_t HandlePolarity(uint32_t value, uint16_t control, int upper_limit, int valid_rhs) { switch (static_cast((control >> 4) & 0b11)) { case Polarity::Negative: @@ -169,6 +175,7 @@ struct OpHandlers { // │ // 'c' match ────────┘ // + FEXCORE_PRESERVE_ALL_ATTR static uint32_t HandleEqualAny(const __uint128_t& lhs, int32_t valid_lhs, const __uint128_t& rhs, int32_t valid_rhs, uint16_t control) { @@ -215,6 +222,7 @@ struct OpHandlers { // │ // 'Z' >= 'z' && 'A' <= 'z' ──────────┘ // + FEXCORE_PRESERVE_ALL_ATTR static uint32_t HandleRanges(const __uint128_t& lhs, int32_t valid_lhs, const __uint128_t& rhs, int32_t valid_rhs, uint16_t control) { @@ -267,6 +275,7 @@ struct OpHandlers { // │ // 'a' == 'a' ──────────┘ // + FEXCORE_PRESERVE_ALL_ATTR static uint32_t HandleEqualEach(const __uint128_t& lhs, int32_t valid_lhs, const __uint128_t& rhs, int32_t valid_rhs, uint16_t control) { @@ -321,6 +330,7 @@ struct OpHandlers { // │ // At index 0 ──────────┘ // + FEXCORE_PRESERVE_ALL_ATTR static uint32_t HandleEqualOrdered(const __uint128_t& lhs, int32_t valid_lhs, const __uint128_t& rhs, int32_t valid_rhs, uint16_t control) { @@ -369,6 +379,7 @@ struct OpHandlers { // to be the max length possible for the given character size specified // in the control flags (16 characters for 8-bit, and 8 characters for 16-bit). // + FEXCORE_PRESERVE_ALL_ATTR static uint32_t handle(__uint128_t lhs, __uint128_t rhs, uint16_t control) { // Subtract by 1 in order to make validity limits 0-based const auto valid_lhs = GetImplicitLength(lhs, control) - 1; @@ -377,6 +388,7 @@ struct OpHandlers { return OpHandlers::MainBody(lhs, valid_lhs, rhs, valid_rhs, control); } + FEXCORE_PRESERVE_ALL_ATTR static int32_t GetImplicitLength(const __uint128_t& data, uint16_t control) { const auto* data_u8 = reinterpret_cast(&data); const auto is_using_words = (control & 1) != 0; From 0a0865eb1c1c959e6e7cfb256d0e434ea412b5df Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 18 Sep 2023 17:32:48 -0700 Subject: [PATCH 7/7] InstCountCI: Update for minor change --- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 4 +- .../InstructionCountCI/PrimaryGroup.json | 8 +- unittests/InstructionCountCI/Secondary.json | 14 +- .../InstructionCountCI/Secondary_OpSize.json | 6 +- .../InstructionCountCI/Secondary_REP.json | 2 +- .../InstructionCountCI/Secondary_REPNE.json | 4 +- unittests/InstructionCountCI/VEX_map1.json | 14 +- unittests/InstructionCountCI/VEX_map2.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 2814 ++++++++--------- 11 files changed, 1437 insertions(+), 1437 deletions(-) diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index aaf59a234..0b2c19c3a 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -682,7 +682,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1552]", + "ldr x0, [x28, #1544]", "ldr q2, [x0]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index e3e9e8b9b..9a784780b 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -1556,7 +1556,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1608]", + "ldr x0, [x28, #1600]", "ldr q2, [x0]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", @@ -1571,7 +1571,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1608]", + "ldr x0, [x28, #1600]", "ldr q2, [x0]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 4488e4bfc..99da8c8a7 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -3232,7 +3232,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1920]", + "ldr x3, [x28, #1912]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3243,7 +3243,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1936]", + "ldr x3, [x28, #1928]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3307,7 +3307,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1928]", + "ldr x3, [x28, #1920]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3320,7 +3320,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1944]", + "ldr x3, [x28, #1936]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 6f6fc4ac3..dfa076a77 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -898,7 +898,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr x0, [x28, #1600]", + "ldr x0, [x28, #1592]", "ldr q3, [x0]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", @@ -911,7 +911,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr x0, [x28, #1600]", + "ldr x0, [x28, #1592]", "ldr q3, [x0]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", @@ -1341,7 +1341,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x28, #768]", - "ldr x0, [x28, #1616]", + "ldr x0, [x28, #1608]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #752]" @@ -1353,7 +1353,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "ldr x0, [x28, #1616]", + "ldr x0, [x28, #1608]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #752]" @@ -3986,7 +3986,7 @@ "Optimal": "No", "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3996,7 +3996,7 @@ "Optimal": "No", "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -4009,7 +4009,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 6c4a0b3c1..fb43aaf8b 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -592,7 +592,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1632]", + "ldr x0, [x28, #1624]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -607,7 +607,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1632]", + "ldr x0, [x28, #1624]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1134,7 +1134,7 @@ "Optimal": "Yes", "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1584]", + "ldr x0, [x28, #1576]", "ldr q2, [x0]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 5d9aa76ae..b7a072ab7 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -390,7 +390,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1624]", + "ldr x0, [x28, #1616]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 412eea8bd..1230a4622 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -335,7 +335,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1616]", + "ldr x0, [x28, #1608]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -515,7 +515,7 @@ "Optimal": "Yes", "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1568]", + "ldr x0, [x28, #1560]", "ldr q2, [x0]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 475ad0217..9d9a0da45 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -3230,7 +3230,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q4, [x0, #16]", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", "mov v2.16b, v2.16b", @@ -3292,7 +3292,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q4, [x0, #32]", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", "mov v2.16b, v2.16b", @@ -3354,7 +3354,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1640]", + "ldr x0, [x28, #1632]", "ldr q4, [x0, #48]", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", "mov v2.16b, v2.16b", @@ -5103,7 +5103,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1584]", + "ldr x0, [x28, #1576]", "ldr q4, [x0]", "eor v3.16b, v3.16b, v4.16b", "fadd v2.2d, v2.2d, v3.2d", @@ -5120,7 +5120,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1584]", + "ldr x0, [x28, #1576]", "ld1b {z4.b}, p7/z, [x0]", "eor z3.d, z3.d, z4.d", "fadd z2.d, z2.d, z3.d", @@ -5136,7 +5136,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1568]", + "ldr x0, [x28, #1560]", "ldr q4, [x0]", "eor v3.16b, v3.16b, v4.16b", "fadd v2.4s, v2.4s, v3.4s", @@ -5153,7 +5153,7 @@ "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", "mov z3.d, p7/m, z18.d", - "ldr x0, [x28, #1568]", + "ldr x0, [x28, #1560]", "ld1b {z4.b}, p7/z, [x0]", "eor z3.d, z3.d, z4.d", "fadd z2.s, z2.s, z3.s", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 28e7eea45..d2e11b4e1 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1834,7 +1834,7 @@ ], "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", - "ldr x0, [x28, #1552]", + "ldr x0, [x28, #1544]", "ldr q3, [x0]", "zip1 v4.8h, v3.8h, v2.8h", "zip2 v2.8h, v3.8h, v2.8h", diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 3b36a1f64..9ce7ead0d 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -5381,7 +5381,7 @@ ], "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", - "ldr x0, [x28, #1608]", + "ldr x0, [x28, #1600]", "ldr q3, [x0]", "movi v4.2d, #0x0", "unimplemented (Unimplemented)", @@ -5398,7 +5398,7 @@ ], "ExpectedArm64ASM": [ "mov z2.d, p7/m, z17.d", - "ldr x0, [x28, #1608]", + "ldr x0, [x28, #1600]", "ldr q3, [x0]", "movi v4.2d, #0x0", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index f2f89c9da..11a6104b7 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -39,7 +39,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -89,7 +89,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -147,7 +147,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -197,7 +197,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -255,7 +255,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -305,7 +305,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -369,7 +369,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -419,7 +419,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -491,7 +491,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -541,7 +541,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -599,7 +599,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -649,7 +649,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -707,7 +707,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -757,7 +757,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -815,7 +815,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -865,7 +865,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -931,7 +931,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -997,7 +997,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1063,7 +1063,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1129,7 +1129,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1195,7 +1195,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1261,7 +1261,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1327,7 +1327,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1393,7 +1393,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1459,7 +1459,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1525,7 +1525,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1591,7 +1591,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1657,7 +1657,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1723,7 +1723,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1789,7 +1789,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1855,7 +1855,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1921,7 +1921,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1988,7 +1988,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2059,7 +2059,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2131,7 +2131,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2203,7 +2203,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2275,7 +2275,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2347,7 +2347,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2419,7 +2419,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2491,7 +2491,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2564,7 +2564,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2644,7 +2644,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2723,7 +2723,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2803,7 +2803,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2883,7 +2883,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2963,7 +2963,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3043,7 +3043,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3123,7 +3123,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3203,7 +3203,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3269,7 +3269,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3335,7 +3335,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3401,7 +3401,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3467,7 +3467,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3533,7 +3533,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3599,7 +3599,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3665,7 +3665,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3731,7 +3731,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3797,7 +3797,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3863,7 +3863,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3929,7 +3929,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3995,7 +3995,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4061,7 +4061,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4127,7 +4127,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4193,7 +4193,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4259,7 +4259,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4325,7 +4325,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4391,7 +4391,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4457,7 +4457,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4523,7 +4523,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4589,7 +4589,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4655,7 +4655,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4721,7 +4721,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4787,7 +4787,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4853,7 +4853,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4919,7 +4919,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4985,7 +4985,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5051,7 +5051,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5117,7 +5117,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5183,7 +5183,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5249,7 +5249,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5307,7 +5307,7 @@ "str x30, [x0]", "fmov s0, s2", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldr x1, [x28, #1144]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5375,7 +5375,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1160]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5432,7 +5432,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1160]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6074,7 +6074,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6346,7 +6346,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", + "ldr x3, [x28, #1312]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6418,7 +6418,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6486,7 +6486,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", + "ldr x3, [x28, #1320]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6566,7 +6566,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1432]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6634,7 +6634,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1360]", + "ldr x3, [x28, #1352]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6680,7 +6680,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1368]", + "ldr x3, [x28, #1360]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6748,7 +6748,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1440]", + "ldr x5, [x28, #1432]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6842,7 +6842,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1448]", + "ldr x5, [x28, #1440]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6920,7 +6920,7 @@ "umov w2, v2.h[4]", "mov x3, v4.d[0]", "umov w4, v4.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6968,7 +6968,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7028,7 +7028,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1336]", + "ldr x3, [x28, #1328]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7096,7 +7096,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", + "ldr x3, [x28, #1336]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7142,7 +7142,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", + "ldr x3, [x28, #1344]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7206,7 +7206,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1304]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7272,7 +7272,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1456]", + "ldr x5, [x28, #1448]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7332,7 +7332,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", + "ldr x3, [x28, #1336]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7394,7 +7394,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", + "ldr x3, [x28, #1344]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7454,7 +7454,459 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "mov w1, w21", - "ldr x2, [x28, #1304]", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fimul dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "ficom dword [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xda !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp dword [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xda !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7531,11 +7983,11 @@ "str q2, [x0, #752]" ] }, - "fimul dword [rax]": { + "fisubr dword [rax]": { "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ - "0xda !11b /1" + "0xda !11b /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", @@ -7562,7 +8014,115 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "mov w1, w21", - "ldr x2, [x28, #1304]", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidiv dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7639,566 +8199,6 @@ "str q2, [x0, #752]" ] }, - "ficom dword [rax]": { - "ExpectedInstructionCount": 105, - "Optimal": "No", - "Comment": [ - "0xda !11b /2" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1304]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", - "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", - "orr w22, w22, w20", - "strb w21, [x28, #744]", - "mov w21, #0x0", - "strb w21, [x28, #745]", - "strb w20, [x28, #746]", - "strb w22, [x28, #750]" - ] - }, - "ficomp dword [rax]": { - "ExpectedInstructionCount": 113, - "Optimal": "No", - "Comment": [ - "0xda !11b /3" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1304]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #744]", - "mov w22, #0x0", - "strb w22, [x28, #745]", - "strb w21, [x28, #746]", - "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]" - ] - }, - "fisub dword [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xda !11b /4" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1304]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fisubr dword [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xda !11b /5" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1304]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fidiv dword [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xda !11b /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1304]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, "fidivr dword [rax]": { "ExpectedInstructionCount": 99, "Optimal": "No", @@ -8230,7 +8230,7 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "mov w1, w21", - "ldr x2, [x28, #1304]", + "ldr x2, [x28, #1296]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8280,7 +8280,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9243,7 +9243,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9364,7 +9364,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1216]", + "ldr x3, [x28, #1208]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9429,7 +9429,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1192]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9486,7 +9486,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1192]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10523,7 +10523,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10595,7 +10595,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10667,7 +10667,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10739,7 +10739,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10811,7 +10811,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10883,7 +10883,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10955,7 +10955,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11027,7 +11027,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11099,7 +11099,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11171,7 +11171,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11243,7 +11243,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11315,7 +11315,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11387,7 +11387,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11459,7 +11459,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11531,7 +11531,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11603,7 +11603,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11667,7 +11667,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11717,7 +11717,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11775,7 +11775,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11825,7 +11825,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11883,7 +11883,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11933,7 +11933,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11997,7 +11997,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12047,7 +12047,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12119,7 +12119,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12169,7 +12169,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12227,7 +12227,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12277,7 +12277,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12335,7 +12335,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12385,7 +12385,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12443,7 +12443,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12493,7 +12493,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12561,7 +12561,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12627,7 +12627,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12693,7 +12693,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12759,7 +12759,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12825,7 +12825,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12891,7 +12891,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12957,7 +12957,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13023,7 +13023,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13091,7 +13091,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13157,7 +13157,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13223,7 +13223,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13289,7 +13289,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13355,7 +13355,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13421,7 +13421,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13487,7 +13487,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13553,7 +13553,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13621,7 +13621,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13687,7 +13687,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13753,7 +13753,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13819,7 +13819,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13885,7 +13885,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13951,7 +13951,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14017,7 +14017,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14083,7 +14083,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14151,7 +14151,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14217,7 +14217,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14283,7 +14283,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14349,7 +14349,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14415,7 +14415,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14481,7 +14481,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14547,7 +14547,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14613,7 +14613,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14681,7 +14681,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14747,7 +14747,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14813,7 +14813,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14879,7 +14879,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14945,7 +14945,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15011,7 +15011,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15077,7 +15077,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15143,7 +15143,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15211,7 +15211,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15277,7 +15277,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15343,7 +15343,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15409,7 +15409,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15475,7 +15475,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15541,7 +15541,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15607,7 +15607,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15673,7 +15673,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15731,7 +15731,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1160]", + "ldr x1, [x28, #1152]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15799,7 +15799,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1224]", + "ldr x3, [x28, #1216]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15864,7 +15864,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1168]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15921,7 +15921,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1168]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16743,7 +16743,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16814,7 +16814,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16886,7 +16886,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16958,7 +16958,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17030,7 +17030,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17102,7 +17102,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17174,7 +17174,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17246,7 +17246,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17319,7 +17319,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17399,7 +17399,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17478,7 +17478,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17558,7 +17558,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17638,7 +17638,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17718,7 +17718,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17798,7 +17798,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17878,7 +17878,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17950,7 +17950,459 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "sxth w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fimul word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "ficom word [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xde !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp word [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xde !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18027,11 +18479,11 @@ "str q2, [x0, #752]" ] }, - "fimul word [rax]": { + "fisubr word [rax]": { "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ - "0xde !11b /1" + "0xde !11b /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", @@ -18058,7 +18510,115 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "sxth w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidiv word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18135,566 +18695,6 @@ "str q2, [x0, #752]" ] }, - "ficom word [rax]": { - "ExpectedInstructionCount": 105, - "Optimal": "No", - "Comment": [ - "0xde !11b /2" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrh w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "sxth w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", - "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", - "orr w22, w22, w20", - "strb w21, [x28, #744]", - "mov w21, #0x0", - "strb w21, [x28, #745]", - "strb w20, [x28, #746]", - "strb w22, [x28, #750]" - ] - }, - "ficomp word [rax]": { - "ExpectedInstructionCount": 113, - "Optimal": "No", - "Comment": [ - "0xde !11b /3" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrh w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "sxth w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #744]", - "mov w22, #0x0", - "strb w22, [x28, #745]", - "strb w21, [x28, #746]", - "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]" - ] - }, - "fisub word [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xde !11b /4" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrh w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "sxth w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fisubr word [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xde !11b /5" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrh w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "sxth w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fidiv word [rax]": { - "ExpectedInstructionCount": 99, - "Optimal": "No", - "Comment": [ - "0xde !11b /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrh w21, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "sxth w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, "fidivr word [rax]": { "ExpectedInstructionCount": 99, "Optimal": "No", @@ -18726,7 +18726,7 @@ "str x30, [x0]", "ldrh w0, [x28, #1008]", "sxth w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1288]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18776,7 +18776,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18842,7 +18842,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18917,7 +18917,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18990,7 +18990,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19064,7 +19064,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19138,7 +19138,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19212,7 +19212,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19286,7 +19286,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19360,7 +19360,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1384]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19434,7 +19434,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19509,7 +19509,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19582,7 +19582,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19656,7 +19656,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19730,7 +19730,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19804,7 +19804,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19878,7 +19878,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19952,7 +19952,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20027,7 +20027,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20114,7 +20114,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20189,7 +20189,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20262,7 +20262,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20336,7 +20336,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20410,7 +20410,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20484,7 +20484,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20558,7 +20558,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20632,7 +20632,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20708,7 +20708,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20783,7 +20783,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20856,7 +20856,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20930,7 +20930,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21004,7 +21004,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21078,7 +21078,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21152,7 +21152,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21226,7 +21226,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1392]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21302,7 +21302,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21377,7 +21377,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21450,7 +21450,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21524,7 +21524,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21598,7 +21598,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21672,7 +21672,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21746,7 +21746,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21820,7 +21820,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21896,7 +21896,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21971,7 +21971,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22044,7 +22044,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22118,7 +22118,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22192,7 +22192,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22266,7 +22266,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22340,7 +22340,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22414,7 +22414,7 @@ "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22524,7 +22524,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1208]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22589,7 +22589,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22646,7 +22646,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22718,7 +22718,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1384]", + "ldr x3, [x28, #1376]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22778,7 +22778,7 @@ "ldrh w0, [x28, #1008]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1376]", + "ldr x3, [x28, #1368]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22983,7 +22983,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23064,7 +23064,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23143,7 +23143,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23223,7 +23223,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23303,7 +23303,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23383,7 +23383,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23463,7 +23463,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23543,7 +23543,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23623,7 +23623,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23704,7 +23704,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23783,7 +23783,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23863,7 +23863,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23943,7 +23943,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24023,7 +24023,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24103,7 +24103,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24183,7 +24183,7 @@ "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1288]", + "ldr x5, [x28, #1280]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",