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Merge pull request #5716 from lioncash/vec
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@@ -598,14 +598,14 @@ Ref OpDispatchBuilder::InsertScalarFCMPOpImpl(OpSize Size, IR::OpSize OpDstSize,
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}
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void OpDispatchBuilder::InsertScalarFCMPOp(OpcodeArgs, IR::OpSize ElementSize) {
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const uint8_t CompType = Op->Src[1].Literal();
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const uint8_t CompType = Op->Src[1].Literal() & 0b111;
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const auto DstSize = GetGuestVectorLength();
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const auto SrcSize = OpSizeFromSrc(Op);
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Ref Src1 = LoadSourceFPR_WithOpSize(Op, Op->Dest, DstSize, Op->Flags);
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Ref Src2 = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags, {.AllowUpperGarbage = true});
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Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType & 0b111, false);
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Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType, false);
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// ARM doesn't have any instructions that handle the semantics of NLT and NLE directly.
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// In fact, these are the two SSE compatison types where we cannot use VFCMPScalarInsert
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@@ -623,7 +623,7 @@ void OpDispatchBuilder::InsertScalarFCMPOp(OpcodeArgs, IR::OpSize ElementSize) {
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}
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void OpDispatchBuilder::AVXInsertScalarFCMPOp(OpcodeArgs, IR::OpSize ElementSize) {
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const uint8_t CompType = Op->Src[2].Literal();
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const uint8_t CompType = Op->Src[2].Literal() & 0b11111;
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const auto DstSize = GetGuestVectorLength();
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const auto SrcSize = OpSizeFromSrc(Op);
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@@ -633,7 +633,7 @@ void OpDispatchBuilder::AVXInsertScalarFCMPOp(OpcodeArgs, IR::OpSize ElementSize
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Ref Src1 = LoadSourceFPR_WithOpSize(Op, Op->Src[0], DstSize, Op->Flags);
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Ref Src2 = LoadSourceFPR_WithOpSize(Op, Op->Src[1], SrcSize, Op->Flags, {.AllowUpperGarbage = true});
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Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType & 0b11111, true);
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Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType, true);
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StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
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}
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