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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2025-08-06 20:42:36 -04:00
1 parent 40beef061f
commit f99b42da5e
36 files changed
+3450 -3450
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unittests/InstructionCountCI/AVX128/VEX_map1.json
+4 -4
View File
@@ -2702,8 +2702,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -2715,8 +2715,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -2728,8 +2728,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -2741,8 +2741,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+4 -4
View File
@@ -19,8 +19,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -31,8 +31,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -43,8 +43,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -55,8 +55,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
}
unittests/InstructionCountCI/AVX128/VEX_map2.json
+8 -8
View File
@@ -512,12 +512,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -529,8 +529,6 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"mov w27, #0x0",
"mov w26, #0x1",
"and v4.16b, v17.16b, v16.16b",
"and v5.16b, v3.16b, v2.16b",
"ushr v4.4s, v4.4s, #31",
@@ -545,11 +543,13 @@
"add v2.4s, v2.4s, v4.4s",
"addv s2, v2.4s",
"mov w21, v2.s[0]",
"mov w27, #0x0",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -570,12 +570,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -587,8 +587,6 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"mov w27, #0x0",
"mov w26, #0x1",
"and v4.16b, v17.16b, v16.16b",
"and v5.16b, v3.16b, v2.16b",
"ushr v4.2d, v4.2d, #63",
@@ -603,11 +601,13 @@
"add v2.2d, v2.2d, v4.2d",
"addp v2.2d, v2.2d, v2.2d",
"mov x21, v2.d[0]",
"mov w27, #0x0",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -676,12 +676,12 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -704,12 +704,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+16 -16
View File
@@ -30,11 +30,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestps ymm0, ymm1": {
@@ -45,8 +45,6 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"mov w27, #0x0",
"mov w26, #0x1",
"and v4.16b, v17.16b, v16.16b",
"and v5.16b, v3.16b, v2.16b",
"ushr v4.4s, v4.4s, #31",
@@ -61,10 +59,12 @@
"add v2.4s, v2.4s, v4.4s",
"addv s2, v2.4s",
"mov w21, v2.s[0]",
"mov w27, #0x0",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestpd xmm0, xmm1": {
@@ -84,11 +84,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestpd ymm0, ymm1": {
@@ -99,8 +99,6 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"mov w27, #0x0",
"mov w26, #0x1",
"and v4.16b, v17.16b, v16.16b",
"and v5.16b, v3.16b, v2.16b",
"ushr v4.2d, v4.2d, #63",
@@ -115,10 +113,12 @@
"add v2.2d, v2.2d, v4.2d",
"addp v2.2d, v2.2d, v2.2d",
"mov x21, v2.d[0]",
"mov w27, #0x0",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vptest xmm0, xmm1": {
@@ -134,11 +134,11 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vptest ymm0, ymm1": {
@@ -160,11 +160,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vmaskmovps xmm0, xmm1, [rax]": {
@@ -642,7 +642,7 @@
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
@@ -658,7 +658,7 @@
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
unittests/InstructionCountCI/Atomics.json
+8 -8
View File
@@ -1477,7 +1477,7 @@
"mov w20, #0xff",
"ldaddalb w20, w27, [x4]",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
@@ -1575,7 +1575,7 @@
"mov w20, #0xffff",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
@@ -1590,7 +1590,7 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"cset x20, hs",
"subs w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -1603,7 +1603,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"cset x20, hs",
"subs x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -1616,7 +1616,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
@@ -1631,7 +1631,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
@@ -1646,7 +1646,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"cset x20, hs",
"adds w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -1659,7 +1659,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"cset x20, hs",
"adds x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+3 -3
View File
@@ -171,7 +171,7 @@
"mov w20, #0x5",
"movk w20, #0x1, lsl #16",
"str x20, [x28, #24]",
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -182,7 +182,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -1574,7 +1574,7 @@
"mov v16.s[0], v0.s[0]",
"mov w7, #0x0",
"fcmp s16, s18",
"cset w26, vc",
"cset x26, vc",
"axflag",
"mov x27, x7"
]
unittests/InstructionCountCI/FlagM/Atomics.json
+4 -4
View File
@@ -1389,7 +1389,7 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"cset x20, hs",
"subs w26, w27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
@@ -1400,7 +1400,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"cset x20, hs",
"subs x26, x27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
@@ -1435,7 +1435,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"cset x20, hs",
"adds w26, w27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
@@ -1446,7 +1446,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"cset x20, hs",
"adds x26, x27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
unittests/InstructionCountCI/FlagM/FlagOpts.json
+4 -4
View File
@@ -94,7 +94,7 @@
],
"ExpectedArm64ASM": [
"adds x4, x4, x6",
"cset w20, lo",
"cset x20, lo",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -125,7 +125,7 @@
],
"ExpectedArm64ASM": [
"subs x4, x4, x6",
"cset w20, hs",
"cset x20, hs",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -212,7 +212,7 @@
"and x20, x7, #0x3f",
"cbz x20, #+0x20",
"lsr x20, x4, x7",
"cset w21, lo",
"cset x21, lo",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
@@ -304,7 +304,7 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset w26, vc",
"cset x26, vc",
"bfxil x7, x26, #0, #8",
"subs x26, x4, #0x0 (0)"
]
unittests/InstructionCountCI/FlagM/H0F38.json
+2 -2
View File
@@ -25,11 +25,11 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"adcx eax, ebx": {
unittests/InstructionCountCI/FlagM/Primary.json
+5 -5
View File
@@ -1665,7 +1665,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -1676,7 +1676,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -1710,7 +1710,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -1721,7 +1721,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -1815,7 +1815,7 @@
"ExpectedInstructionCount": 14,
"Comment": "0x9f",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+80 -80
View File
@@ -908,22 +908,22 @@
"Comment": "GROUP2 0xC0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x0",
"cset w22, lo",
"bfi x21, x20, #55, #8",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #46, #8",
"bfi x21, x22, #54, #1",
"bfi x21, x20, #37, #8",
"bfi x21, x22, #45, #1",
"bfi x21, x20, #28, #8",
"bfi x21, x22, #36, #1",
"bfi x21, x20, #19, #8",
"bfi x21, x22, #27, #1",
"bfxil x21, x20, #0, #8",
"ror x20, x21, #62",
"cset x21, lo",
"mov w22, #0x0",
"bfi x22, x20, #55, #8",
"bfi x22, x21, #63, #1",
"bfi x22, x20, #46, #8",
"bfi x22, x21, #54, #1",
"bfi x22, x20, #37, #8",
"bfi x22, x21, #45, #1",
"bfi x22, x20, #28, #8",
"bfi x22, x21, #36, #1",
"bfi x22, x20, #19, #8",
"bfi x22, x21, #27, #1",
"bfxil x22, x20, #0, #8",
"ror x20, x22, #62",
"bfxil x4, x20, #0, #8",
"ror x20, x21, #61",
"ror x20, x22, #61",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
@@ -932,7 +932,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xC0 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"uxtb w21, w4",
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
@@ -1044,18 +1044,18 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov w21, #0x0",
"cset w22, lo",
"bfi x21, x20, #47, #16",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #30, #16",
"bfi x21, x22, #46, #1",
"bfi x21, x20, #13, #16",
"bfi x21, x22, #29, #1",
"bfxil x21, x20, #0, #16",
"ror x20, x21, #62",
"cset x21, lo",
"mov w22, #0x0",
"bfi x22, x20, #47, #16",
"bfi x22, x21, #63, #1",
"bfi x22, x20, #30, #16",
"bfi x22, x21, #46, #1",
"bfi x22, x20, #13, #16",
"bfi x22, x21, #29, #1",
"bfxil x22, x20, #0, #16",
"ror x20, x22, #62",
"bfxil x4, x20, #0, #16",
"ror x20, x21, #61",
"ror x20, x22, #61",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
@@ -1065,7 +1065,7 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl w20, w4, #2",
"cset w21, lo",
"cset x21, lo",
"orr w20, w20, w4, lsr #31",
"eor x22, x4, #0x40000000",
"rmif x22, #29, #nzCv",
@@ -1077,7 +1077,7 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl x20, x4, #2",
"cset w21, lo",
"cset x21, lo",
"orr x20, x20, x4, lsr #63",
"eor x22, x4, #0x4000000000000000",
"rmif x22, #61, #nzCv",
@@ -1088,7 +1088,7 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"uxth w21, w4",
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
@@ -1104,7 +1104,7 @@
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr w20, w4, #2",
"cset w21, lo",
"cset x21, lo",
"orr w20, w20, w4, lsl #31",
"eor x22, x4, #0x2",
"rmif x22, #0, #nzCv",
@@ -1116,7 +1116,7 @@
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr x20, x4, #2",
"cset w21, lo",
"cset x21, lo",
"orr x20, x20, x4, lsl #63",
"eor x22, x4, #0x2",
"rmif x22, #0, #nzCv",
@@ -1257,7 +1257,7 @@
"Comment": "GROUP2 0xd0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w21, w21, w20, lsl #1",
"eor x22, x20, #0x80",
"rmif x22, #6, #nzCv",
@@ -1271,7 +1271,7 @@
"Comment": "GROUP2 0xd0 /3",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"eor x22, x20, #0x1",
"rmif x22, #63, #nzCv",
"ubfx w20, w20, #1, #7",
@@ -1396,7 +1396,7 @@
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w21, w21, w20, lsl #1",
"eor x22, x20, #0x8000",
"rmif x22, #14, #nzCv",
@@ -1410,7 +1410,7 @@
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w4, w21, w20, lsl #1",
"eor x21, x20, #0x80000000",
"rmif x21, #30, #nzCv",
@@ -1422,7 +1422,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"orr x20, x20, x4, lsl #1",
"eor x21, x4, #0x8000000000000000",
"rmif x21, #62, #nzCv",
@@ -1435,7 +1435,7 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"rmif x21, #63, #nzCv",
"ubfx w21, w4, #1, #15",
@@ -1449,7 +1449,7 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"rmif x21, #63, #nzCv",
"extr w4, w20, w4, #1",
@@ -1461,7 +1461,7 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"rmif x21, #63, #nzCv",
"extr x4, x20, x4, #1",
@@ -1622,25 +1622,25 @@
"cbz x20, #+0x68",
"and x20, x7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
"bfi x22, x21, #55, #8",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #46, #8",
"bfi x22, x23, #54, #1",
"bfi x22, x21, #37, #8",
"bfi x22, x23, #45, #1",
"bfi x22, x21, #28, #8",
"bfi x22, x23, #36, #1",
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"bfxil x22, x21, #0, #8",
"cset x22, lo",
"mov w23, #0x0",
"bfi x23, x21, #55, #8",
"bfi x23, x22, #63, #1",
"bfi x23, x21, #46, #8",
"bfi x23, x22, #54, #1",
"bfi x23, x21, #37, #8",
"bfi x23, x22, #45, #1",
"bfi x23, x21, #28, #8",
"bfi x23, x22, #36, #1",
"bfi x23, x21, #19, #8",
"bfi x23, x22, #27, #1",
"bfxil x23, x21, #0, #8",
"neg x21, x20",
"ror x21, x22, x21",
"ror x21, x23, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"mov w22, #0x3f",
"sub x20, x22, x20",
"ror x20, x23, x20",
"eor x22, x20, #0x1",
"rmif x22, #63, #nzCv",
"eor x20, x20, x21, lsr #7",
@@ -1654,7 +1654,7 @@
"and x20, x7, #0x1f",
"cbz x20, #+0x40",
"and x20, x7, #0x1f",
"cset w21, lo",
"cset x21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
"bfi x22, x22, #9, #9",
@@ -1817,21 +1817,21 @@
"cbz x20, #+0x58",
"and x20, x7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
"bfi x22, x21, #47, #16",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #30, #16",
"bfi x22, x23, #46, #1",
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"bfxil x22, x21, #0, #16",
"cset x22, lo",
"mov w23, #0x0",
"bfi x23, x21, #47, #16",
"bfi x23, x22, #63, #1",
"bfi x23, x21, #30, #16",
"bfi x23, x22, #46, #1",
"bfi x23, x21, #13, #16",
"bfi x23, x22, #29, #1",
"bfxil x23, x21, #0, #16",
"neg x21, x20",
"ror x21, x22, x21",
"ror x21, x23, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"mov w22, #0x3f",
"sub x20, x22, x20",
"ror x20, x23, x20",
"eor x22, x20, #0x1",
"rmif x22, #63, #nzCv",
"eor x20, x20, x21, lsr #15",
@@ -1845,7 +1845,7 @@
"and w20, w7, #0x1f",
"cbz x20, #+0x3c",
"lsl w20, w4, w7",
"cset w21, lo",
"cset x21, lo",
"neg w22, w7",
"lsr w23, w4, w22",
"orr w20, w20, w23, lsr #1",
@@ -1868,7 +1868,7 @@
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"lsl x20, x4, x7",
"cset w21, lo",
"cset x21, lo",
"neg x22, x7",
"lsr x23, x4, x22",
"orr x20, x20, x23, lsr #1",
@@ -1889,7 +1889,7 @@
"and x20, x7, #0x1f",
"cbz x20, #+0x3c",
"and x20, x7, #0x1f",
"cset w21, lo",
"cset x21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
"bfi x22, x22, #17, #17",
@@ -1911,7 +1911,7 @@
"and w20, w7, #0x1f",
"cbz x20, #+0x3c",
"lsr w20, w4, w7",
"cset w21, lo",
"cset x21, lo",
"neg w22, w7",
"lsl w23, w4, w22",
"orr w20, w20, w23, lsl #1",
@@ -1934,7 +1934,7 @@
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"lsr x20, x4, x7",
"cset w21, lo",
"cset x21, lo",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
@@ -2386,7 +2386,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -2397,7 +2397,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -2420,7 +2420,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -2431,7 +2431,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+8 -8
View File
@@ -107,7 +107,7 @@
"Comment": "0x27",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"cset x21, hs",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@@ -134,7 +134,7 @@
"Comment": "0x2f",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@@ -214,7 +214,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -251,7 +251,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@@ -310,7 +310,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -321,7 +321,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -355,7 +355,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -366,7 +366,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
unittests/InstructionCountCI/FlagM/Secondary.json
+2 -2
View File
@@ -18,8 +18,8 @@
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -28,8 +28,8 @@
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+6 -6
View File
@@ -739,9 +739,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndr",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
@@ -751,9 +751,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndr",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
@@ -762,9 +762,9 @@
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x4, rndr",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
@@ -774,9 +774,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
@@ -786,9 +786,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
@@ -797,9 +797,9 @@
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x4, rndrrs",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+2 -2
View File
@@ -18,8 +18,8 @@
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -28,8 +28,8 @@
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
unittests/InstructionCountCI/FlagM/VEX_map1.json
+4 -4
View File
@@ -21,8 +21,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -33,8 +33,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -45,8 +45,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
@@ -57,8 +57,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"axflag"
]
},
unittests/InstructionCountCI/FlagM/VEX_map2.json
+14 -14
View File
@@ -29,11 +29,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestps ymm0, ymm1": {
@@ -53,11 +53,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestpd xmm0, xmm1": {
@@ -77,11 +77,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vtestpd ymm0, ymm1": {
@@ -101,11 +101,11 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vptest xmm0, xmm1": {
@@ -121,11 +121,11 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vptest ymm0, ymm1": {
@@ -141,11 +141,11 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"mov w26, #0x1"
]
},
"vmaskmovps xmm0, xmm1, [rax]": {
@@ -375,7 +375,7 @@
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
@@ -391,7 +391,7 @@
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
unittests/InstructionCountCI/FlagM/VEX_map_group.json
+2 -2
View File
@@ -76,7 +76,7 @@
"neg w20, w6",
"and w4, w6, w20",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"cset x20, eq",
"rmif x20, #63, #nzCv"
]
},
@@ -89,7 +89,7 @@
"neg x20, x6",
"and x4, x6, x20",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"cset x20, eq",
"rmif x20, #63, #nzCv"
]
}
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+89 -89
View File
@@ -481,26 +481,26 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q4, [x0, #1040]",
"mov w21, #0x1",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q7, [x0, #1040]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q2, [x0, #1040]",
"add w22, w20, #0x3 (3)",
"and w22, w22, #0x7",
"mov w23, #0x8",
"sub w20, w23, w20",
"ldrb w23, [x28, #1426]",
"mov w12, #0x707",
"lsr w20, w12, w20",
"orr w20, w23, w20",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"mov w22, #0x8",
"sub w20, w22, w20",
"ldrb w22, [x28, #1426]",
"mov w23, #0x707",
"lsr w20, w23, w20",
"orr w20, w22, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1426]",
"lsl w21, w21, w22",
"mov w22, #0x1",
"lsl w21, w22, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1426]"
]
@@ -743,22 +743,22 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"mov w21, #0x1",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q2, [x0, #1040]",
"add w22, w20, #0x6 (6)",
"and w22, w22, #0x7",
"mov w23, #0x8",
"sub w20, w23, w20",
"ldrb w23, [x28, #1426]",
"mov w12, #0x303",
"lsr w20, w12, w20",
"orr w20, w23, w20",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"mov w22, #0x8",
"sub w20, w22, w20",
"ldrb w22, [x28, #1426]",
"mov w23, #0x303",
"lsr w20, w23, w20",
"orr w20, w22, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1426]",
"lsl w21, w21, w22",
"mov w22, #0x1",
"lsl w21, w22, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1426]"
]
@@ -1003,27 +1003,26 @@
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"ldrb w23, [x28, #1426]",
"lsl w20, w21, w20",
"orr w20, w23, w20",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"ldrb w22, [x28, #1426]",
"mov w23, #0x1",
"lsl w20, w23, w20",
"orr w20, w22, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1426]",
"lsl w21, w21, w22",
"lsl w21, w23, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x20, lsl #4",
"ldr q3, [x0, #1040]",
@@ -1035,12 +1034,13 @@
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add x0, x28, x22, lsl #4",
"add x0, x28, x21, lsl #4",
"str q2, [x0, #1040]",
"ldrb w22, [x28, #1426]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"strb w22, [x28, #1426]",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w23, w22, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1426]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
@@ -1054,9 +1054,9 @@
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x10]",
"ldrb w22, [x28, #1426]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"ldrb w21, [x28, #1426]",
"lsl w22, w22, w20",
"bic w21, w21, w22",
"strb w21, [x28, #1426]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
@@ -1876,30 +1876,30 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q5, [x0, #1040]",
"mov w21, #0x1",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q4, [x0, #1040]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1040]",
"add w22, w20, #0x3 (3)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"str q2, [x0, #1040]",
"add w22, w20, #0x7 (7)",
"and w22, w22, #0x7",
"mov w23, #0x8",
"sub w20, w23, w20",
"ldrb w23, [x28, #1426]",
"mov w12, #0xf0f",
"lsr w20, w12, w20",
"orr w20, w23, w20",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"mov w22, #0x8",
"sub w20, w22, w20",
"ldrb w22, [x28, #1426]",
"mov w23, #0xf0f",
"lsr w20, w23, w20",
"orr w20, w22, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1426]",
"lsl w21, w21, w22",
"mov w22, #0x1",
"lsl w21, w22, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1426]"
]
@@ -2147,27 +2147,26 @@
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"add w22, w20, #0x4 (4)",
"and w22, w22, #0x7",
"ldrb w23, [x28, #1426]",
"lsl w20, w21, w20",
"orr w20, w23, w20",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"ldrb w22, [x28, #1426]",
"mov w23, #0x1",
"lsl w20, w23, w20",
"orr w20, w22, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1426]",
"lsl w21, w21, w22",
"lsl w21, w23, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x0, x28, x22, lsl #4",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x20, lsl #4",
"ldr q3, [x0, #1040]",
@@ -2191,9 +2190,10 @@
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x11]",
"ldrb w22, [x28, #1426]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w22, w22, w20",
"bic w21, w21, w22",
"strb w21, [x28, #1426]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
@@ -2232,15 +2232,15 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1426]",
"lsl w20, w21, w20",
"bic w20, w22, w20",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@@ -2437,15 +2437,15 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1426]",
"lsl w20, w21, w20",
"bic w20, w22, w20",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1426]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+14 -14
View File
@@ -17712,12 +17712,12 @@
"sub w20, w20, w21",
"str w20, [x8, #-4]!",
"ldrb w21, [x28, #1019]",
"mov w22, #0x1",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"ldrb w23, [x28, #1426]",
"lsl w21, w22, w21",
"bic w21, w23, w21",
"ldrb w22, [x28, #1426]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"bic w21, w22, w21",
"strb w21, [x28, #1426]"
]
},
@@ -20226,7 +20226,7 @@
"mov w22, #0x0",
"cmp x20, #0x0 (0)",
"mov w23, #0x8000",
"csel x12, x23, xzr, lt",
"csel x12, x23, x22, lt",
"cneg x20, x20, mi",
"mov w13, #0x3f",
"mov x0, #0x3f",
@@ -20277,7 +20277,7 @@
"sxtw x20, w20",
"mrs x21, nzcv",
"cmp x20, #0x0 (0)",
"csel x23, x23, xzr, lt",
"csel x23, x23, x22, lt",
"cneg x20, x20, mi",
"mov x0, #0x3f",
"clz x12, x20",
@@ -26201,12 +26201,12 @@
"fmov s2, s0",
"str s2, [x7]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1426]",
"lsl w20, w21, w20",
"bic w20, w22, w20",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1426]"
]
},
@@ -26549,15 +26549,15 @@
"sub w20, w20, w21",
"str w20, [x8, #-4]!",
"ldrb w21, [x28, #1019]",
"mov w22, #0x1",
"sub w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1019]",
"add x0, x28, x21, lsl #4",
"str q2, [x0, #1040]",
"ldrb w23, [x28, #1426]",
"lsl w21, w22, w21",
"orr w21, w23, w21",
"ldrb w22, [x28, #1426]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"strb w21, [x28, #1426]"
]
},
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+1681 -1681
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+274 -274
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+401 -401
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/H0F38.json
+5 -5
View File
@@ -450,12 +450,12 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -734,7 +734,7 @@
"eor w21, w20, #0x20000000",
"msr nzcv, x21",
"adcs w4, w6, w4",
"cset w21, lo",
"cset x21, lo",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
@@ -749,7 +749,7 @@
"eor w21, w20, #0x20000000",
"msr nzcv, x21",
"adcs x4, x6, x4",
"cset w21, lo",
"cset x21, lo",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
@@ -763,7 +763,7 @@
"mrs x20, nzcv",
"ccmp wzr, #0, #nzcv, vs",
"adcs w4, w6, w4",
"cset w21, hs",
"cset x21, hs",
"bfi w20, w21, #28, #1",
"msr nzcv, x20"
]
@@ -777,7 +777,7 @@
"mrs x20, nzcv",
"ccmp wzr, #0, #nzcv, vs",
"adcs x4, x6, x4",
"cset w21, hs",
"cset x21, hs",
"bfi w20, w21, #28, #1",
"msr nzcv, x20"
]
unittests/InstructionCountCI/Primary.json
+5 -5
View File
@@ -2640,7 +2640,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -2651,7 +2651,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -2685,7 +2685,7 @@
"ExpectedInstructionCount": 39,
"Comment": "0x9c",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
@@ -2696,7 +2696,7 @@
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
@@ -2799,7 +2799,7 @@
"ExpectedInstructionCount": 14,
"Comment": "0x9f",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
unittests/InstructionCountCI/PrimaryGroup.json
+84 -84
View File
@@ -1017,22 +1017,22 @@
"Comment": "GROUP2 0xC0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x0",
"cset w22, lo",
"bfi x21, x20, #55, #8",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #46, #8",
"bfi x21, x22, #54, #1",
"bfi x21, x20, #37, #8",
"bfi x21, x22, #45, #1",
"bfi x21, x20, #28, #8",
"bfi x21, x22, #36, #1",
"bfi x21, x20, #19, #8",
"bfi x21, x22, #27, #1",
"bfxil x21, x20, #0, #8",
"ror x20, x21, #62",
"cset x21, lo",
"mov w22, #0x0",
"bfi x22, x20, #55, #8",
"bfi x22, x21, #63, #1",
"bfi x22, x20, #46, #8",
"bfi x22, x21, #54, #1",
"bfi x22, x20, #37, #8",
"bfi x22, x21, #45, #1",
"bfi x22, x20, #28, #8",
"bfi x22, x21, #36, #1",
"bfi x22, x20, #19, #8",
"bfi x22, x21, #27, #1",
"bfxil x22, x20, #0, #8",
"ror x20, x22, #62",
"bfxil x4, x20, #0, #8",
"ror x20, x21, #61",
"ror x20, x22, #61",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
@@ -1044,7 +1044,7 @@
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xC0 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"uxtb w21, w4",
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
@@ -1186,18 +1186,18 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov w21, #0x0",
"cset w22, lo",
"bfi x21, x20, #47, #16",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #30, #16",
"bfi x21, x22, #46, #1",
"bfi x21, x20, #13, #16",
"bfi x21, x22, #29, #1",
"bfxil x21, x20, #0, #16",
"ror x20, x21, #62",
"cset x21, lo",
"mov w22, #0x0",
"bfi x22, x20, #47, #16",
"bfi x22, x21, #63, #1",
"bfi x22, x20, #30, #16",
"bfi x22, x21, #46, #1",
"bfi x22, x20, #13, #16",
"bfi x22, x21, #29, #1",
"bfxil x22, x20, #0, #16",
"ror x20, x22, #62",
"bfxil x4, x20, #0, #16",
"ror x20, x21, #61",
"ror x20, x22, #61",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
@@ -1210,7 +1210,7 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl w20, w4, #2",
"cset w21, lo",
"cset x21, lo",
"orr w20, w20, w4, lsr #31",
"eor x22, x4, #0x40000000",
"ubfx x22, x22, #30, #1",
@@ -1225,7 +1225,7 @@
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl x20, x4, #2",
"cset w21, lo",
"cset x21, lo",
"orr x20, x20, x4, lsr #63",
"eor x22, x4, #0x4000000000000000",
"ubfx x22, x22, #62, #1",
@@ -1239,7 +1239,7 @@
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"uxth w21, w4",
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
@@ -1258,7 +1258,7 @@
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr w20, w4, #2",
"cset w21, lo",
"cset x21, lo",
"orr w20, w20, w4, lsl #31",
"eor x22, x4, #0x2",
"ubfx x22, x22, #1, #1",
@@ -1273,7 +1273,7 @@
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr x20, x4, #2",
"cset w21, lo",
"cset x21, lo",
"orr x20, x20, x4, lsl #63",
"eor x22, x4, #0x2",
"ubfx x22, x22, #1, #1",
@@ -1452,7 +1452,7 @@
"Comment": "GROUP2 0xd0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w21, w21, w20, lsl #1",
"eor x22, x20, #0x80",
"ubfx x22, x22, #7, #1",
@@ -1470,7 +1470,7 @@
"Comment": "GROUP2 0xd0 /3",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"eor x22, x20, #0x1",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
@@ -1634,7 +1634,7 @@
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w21, w21, w20, lsl #1",
"eor x22, x20, #0x8000",
"ubfx x22, x22, #15, #1",
@@ -1652,7 +1652,7 @@
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"cset w21, lo",
"cset x21, lo",
"orr w4, w21, w20, lsl #1",
"eor x21, x20, #0x80000000",
"ubfx x21, x21, #31, #1",
@@ -1668,7 +1668,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"orr x20, x20, x4, lsl #1",
"eor x21, x4, #0x8000000000000000",
"lsr x21, x21, #63",
@@ -1685,7 +1685,7 @@
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"ubfx x21, x21, #0, #1",
"mrs x22, nzcv",
@@ -1703,7 +1703,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"ubfx x21, x21, #0, #1",
"mrs x22, nzcv",
@@ -1719,7 +1719,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, lo",
"cset x20, lo",
"eor x21, x4, #0x1",
"ubfx x21, x21, #0, #1",
"mrs x22, nzcv",
@@ -1923,25 +1923,25 @@
"cbz x20, #+0x78",
"and x20, x7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
"bfi x22, x21, #55, #8",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #46, #8",
"bfi x22, x23, #54, #1",
"bfi x22, x21, #37, #8",
"bfi x22, x23, #45, #1",
"bfi x22, x21, #28, #8",
"bfi x22, x23, #36, #1",
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"bfxil x22, x21, #0, #8",
"cset x22, lo",
"mov w23, #0x0",
"bfi x23, x21, #55, #8",
"bfi x23, x22, #63, #1",
"bfi x23, x21, #46, #8",
"bfi x23, x22, #54, #1",
"bfi x23, x21, #37, #8",
"bfi x23, x22, #45, #1",
"bfi x23, x21, #28, #8",
"bfi x23, x22, #36, #1",
"bfi x23, x21, #19, #8",
"bfi x23, x22, #27, #1",
"bfxil x23, x21, #0, #8",
"neg x21, x20",
"ror x21, x22, x21",
"ror x21, x23, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"mov w22, #0x3f",
"sub x20, x22, x20",
"ror x20, x23, x20",
"eor x22, x20, #0x1",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
@@ -1959,7 +1959,7 @@
"and x20, x7, #0x1f",
"cbz x20, #+0x50",
"and x20, x7, #0x1f",
"cset w21, lo",
"cset x21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
"bfi x22, x22, #9, #9",
@@ -2153,21 +2153,21 @@
"cbz x20, #+0x68",
"and x20, x7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
"bfi x22, x21, #47, #16",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #30, #16",
"bfi x22, x23, #46, #1",
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"bfxil x22, x21, #0, #16",
"cset x22, lo",
"mov w23, #0x0",
"bfi x23, x21, #47, #16",
"bfi x23, x22, #63, #1",
"bfi x23, x21, #30, #16",
"bfi x23, x22, #46, #1",
"bfi x23, x21, #13, #16",
"bfi x23, x22, #29, #1",
"bfxil x23, x21, #0, #16",
"neg x21, x20",
"ror x21, x22, x21",
"ror x21, x23, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"mov w22, #0x3f",
"sub x20, x22, x20",
"ror x20, x23, x20",
"eor x22, x20, #0x1",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
@@ -2185,7 +2185,7 @@
"and w20, w7, #0x1f",
"cbz x20, #+0x4c",
"lsl w20, w4, w7",
"cset w21, lo",
"cset x21, lo",
"neg w22, w7",
"lsr w23, w4, w22",
"orr w20, w20, w23, lsr #1",
@@ -2212,7 +2212,7 @@
"and x20, x7, #0x3f",
"cbz x20, #+0x48",
"lsl x20, x4, x7",
"cset w21, lo",
"cset x21, lo",
"neg x22, x7",
"lsr x23, x4, x22",
"orr x20, x20, x23, lsr #1",
@@ -2237,7 +2237,7 @@
"and x20, x7, #0x1f",
"cbz x20, #+0x4c",
"and x20, x7, #0x1f",
"cset w21, lo",
"cset x21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
"bfi x22, x22, #17, #17",
@@ -2263,7 +2263,7 @@
"and w20, w7, #0x1f",
"cbz x20, #+0x4c",
"lsr w20, w4, w7",
"cset w21, lo",
"cset x21, lo",
"neg w22, w7",
"lsl w23, w4, w22",
"orr w20, w20, w23, lsl #1",
@@ -2290,7 +2290,7 @@
"and x20, x7, #0x3f",
"cbz x20, #+0x48",
"lsr x20, x4, x7",
"cset w21, lo",
"cset x21, lo",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
@@ -2856,7 +2856,7 @@
"ExpectedArm64ASM": [
"uxtb w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
@@ -2872,7 +2872,7 @@
"ExpectedArm64ASM": [
"uxtb w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
@@ -2888,7 +2888,7 @@
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
@@ -2902,7 +2902,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -2915,7 +2915,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -2930,7 +2930,7 @@
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
@@ -2944,7 +2944,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -2957,7 +2957,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
unittests/InstructionCountCI/Primary_32Bit.json
+6 -6
View File
@@ -106,7 +106,7 @@
"Comment": "0x27",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"cset x21, hs",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@@ -135,7 +135,7 @@
"Comment": "0x2f",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, lo",
"cset x21, lo",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@@ -207,7 +207,7 @@
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
@@ -221,7 +221,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -236,7 +236,7 @@
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x1",
"cset w21, hs",
"cset x21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
@@ -264,7 +264,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"cset x20, hs",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
unittests/InstructionCountCI/Secondary.json
+2 -2
View File
@@ -228,8 +228,8 @@
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -239,8 +239,8 @@
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
unittests/InstructionCountCI/SecondaryGroup.json
+6 -6
View File
@@ -941,9 +941,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndr",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
@@ -956,9 +956,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndr",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
@@ -970,9 +970,9 @@
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x4, rndr",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
@@ -985,9 +985,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
@@ -1000,9 +1000,9 @@
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
@@ -1014,9 +1014,9 @@
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x4, rndrrs",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
unittests/InstructionCountCI/Secondary_OpSize.json
+2 -2
View File
@@ -157,8 +157,8 @@
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -168,8 +168,8 @@
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
unittests/InstructionCountCI/VEX_map1.json
+4 -4
View File
@@ -3394,8 +3394,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -3407,8 +3407,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -3420,8 +3420,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
@@ -3433,8 +3433,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"cset x26, vc",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
unittests/InstructionCountCI/VEX_map2.json
+8 -8
View File
@@ -517,12 +517,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -543,12 +543,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -569,12 +569,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -595,12 +595,12 @@
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -675,12 +675,12 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -697,12 +697,12 @@
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w26, #0x1",
"msr nzcv, x20"
]
},
@@ -4925,7 +4925,7 @@
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
@@ -4943,7 +4943,7 @@
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cset x20, eq",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
unittests/InstructionCountCI/VEX_map_group.json
+2 -2
View File
@@ -680,7 +680,7 @@
"neg w20, w6",
"and w4, w6, w20",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"cset x20, eq",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
@@ -695,7 +695,7 @@
"neg x20, x6",
"and x4, x6, x20",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"cset x20, eq",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
unittests/InstructionCountCI/X87ldst-SVE.json
+4 -4
View File
@@ -175,15 +175,15 @@
"ExpectedArm64ASM": [
"ld1h {z2.h}, p2/z, [x4]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w22, [x28, #1426]",
"lsl w20, w21, w20",
"orr w20, w22, w20",
"ldrb w21, [x28, #1426]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1426]"
]
},
unittests/InstructionCountCI/x87.json
+278 -278
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+409 -409
View File
File diff suppressed because it is too large. Load diff