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Merge pull request #3083 from Sonicadvance1/optimize_nop_move

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OpcodeDispatcher: Optimize NOP vector move
This commit is contained in:
Mai authored and GitHub committed 2023-09-12 19:34:36 -04:00
2 parents 90f7937146 8a44be0c30
commit f7e652b616
4 files changed
+70 -18
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FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+5
View File
@@ -24,6 +24,11 @@ namespace FEXCore::IR {
#define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
void OpDispatchBuilder::MOVVectorOp(OpcodeArgs) {
if (Op->Dest.IsGPR() && Op->Src[0].IsGPR() &&
Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
// Nop
return;
}
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 1);
StoreResult(FPRClass, Op, Src, 1);
}
unittests/InstructionCountCI/DDD.json
+9 -18
View File
@@ -240,13 +240,10 @@
]
},
"pfrcpit1 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 0,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
"ExpectedArm64ASM": []
},
"pfrsqit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
@@ -258,13 +255,10 @@
]
},
"pfrsqit1 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 0,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
"ExpectedArm64ASM": []
},
"pfsubr mm0, mm1": {
"ExpectedInstructionCount": 4,
@@ -309,13 +303,10 @@
]
},
"pfrcpit2 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 0,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
"ExpectedArm64ASM": []
},
"db 0x0f, 0x0f, 0xc1, 0xb7": {
"ExpectedInstructionCount": 8,
unittests/InstructionCountCI/Secondary_OpSize.json
+6
View File
@@ -9,6 +9,12 @@
]
},
"Instructions": {
"movupd xmm0, xmm0": {
"ExpectedInstructionCount": 0,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x10",
"ExpectedArm64ASM": []
},
"movupd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
unittests/InstructionCountCI/VEX_map1.json
+50
View File
@@ -10,6 +10,19 @@
]
},
"Instructions": {
"vmovups xmm0, xmm0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"Spurious moves",
"Map 1 0b00 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vmovups xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
@@ -23,6 +36,18 @@
"mov z16.d, p7/m, z2.d"
]
},
"vmovups ymm0, ymm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Spurious moves",
"Map 1 0b00 0x10 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov z16.d, p7/m, z2.d"
]
},
"vmovups ymm0, [rax]": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
@@ -35,6 +60,19 @@
"mov z16.d, p7/m, z2.d"
]
},
"vmovupd xmm0, xmm0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"Spurious moves",
"Map 1 0b01 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vmovupd xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
@@ -48,6 +86,18 @@
"mov z16.d, p7/m, z2.d"
]
},
"vmovupd ymm0, ymm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Spurious moves",
"Map 1 0b01 0x10 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov z16.d, p7/m, z2.d"
]
},
"vmovupd ymm0, [rax]": {
"ExpectedInstructionCount": 2,
"Optimal": "No",