steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-15 00:00:42 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

OpcodeDispatcher: Don't use AddShift with no shift

Browse Source 
This accidentally removed optimizations elsewhere that was only checking
for Add.
This commit is contained in:
Ryan Houdek committed 2024-02-27 19:56:12 -08:00
1 parent 2f9449cb5a
commit f346f89678
1 file changed
+12 -2
Download Patch File Download Diff File Expand all files Collapse all files
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+12 -2
View File
@@ -4757,7 +4757,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
if (!IsVSIB && Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize);
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
if (Operand.Data.SIB.Scale == 1) {
Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index);
}
else {
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
}
}
else {
// NOTE: VSIB cannot have the index * scale portion calculated ahead of time,
@@ -5011,7 +5016,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize);
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
if (Operand.Data.SIB.Scale == 1) {
Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index);
}
else {
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
}
}
else {
if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID) {