From f346f89678cb0c701aaed4fa749f35c28e9c72bb Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 27 Feb 2024 19:56:12 -0800 Subject: [PATCH] OpcodeDispatcher: Don't use AddShift with no shift This accidentally removed optimizations elsewhere that was only checking for Add. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 47b29082d..0ac40e2f7 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4757,7 +4757,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X if (!IsVSIB && Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) { auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize); auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize); - Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale)); + if (Operand.Data.SIB.Scale == 1) { + Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index); + } + else { + Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale)); + } } else { // NOTE: VSIB cannot have the index * scale portion calculated ahead of time, @@ -5011,7 +5016,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) { auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize); auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize); - Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale)); + if (Operand.Data.SIB.Scale == 1) { + Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index); + } + else { + Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale)); + } } else { if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID) {