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https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 14:00:16 +02:00
OpcodeDispatcher: Match x86 overflow behaviour for F2I conversions
ARM behaviour here is to saturate on overflow or NaN inputs, whereas X86 returns a sentinel value of 2^(bitsize-1), explicitly emulate this.
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Billy Laws committed
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efd6e95059
6 files changed
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@@ -39,6 +39,14 @@ namespace CPU {
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{0xC90F'DAA2'2168'C235ULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_PI
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{0x9A20'9A84'FBCF'F799ULL, 0x0000'0000'0000'3FFDULL}, // NAMED_VECTOR_X87_LOG10_2
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{0xB172'17F7'D1CF'79ACULL, 0x0000'0000'0000'3FFEULL}, // NAMED_VECTOR_X87_LOG_2
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{0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32
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{0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32_UPPER
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{0x5F00'0000'5F00'0000ULL, 0x5F00'0000'5F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I64
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{0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32
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{0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32_UPPER
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{0x43E0'0000'0000'0000ULL, 0x43E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I64
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{0x8000'0000'8000'0000ULL, 0x8000'0000'8000'0000ULL}, // NAMED_VECTOR_CVTMAX_I32
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{0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_I64
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};
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constexpr static auto PSHUFLW_LUT {[]() consteval {
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@@ -1465,7 +1465,10 @@ private:
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Ref Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize,
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const X86Tables::DecodedOperand& Src1Op, const X86Tables::DecodedOperand& Src2Op);
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Ref Vector_CVT_Float_To_IntImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode);
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Ref CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSize SrcElementSize, bool HostRoundingMode);
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Ref Vector_CVT_Float_To_Int32Impl(OpcodeArgs, IR::OpSize DstSize, Ref Src, IR::OpSize SrcSize, IR::OpSize SrcElementSize,
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bool HostRoundingMode, bool ZeroUpperHalf);
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Ref Vector_CVT_Int_To_FloatImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool Widen);
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@@ -1058,18 +1058,8 @@ void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs) {
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Src.Low = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], OpSizeFromSrc(Op), Op->Flags);
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}
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// GPR size is determined by REX.W
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// Source Element size is determined by instruction
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const auto GPRSize = OpSizeFromDst(Op);
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Ref Result {};
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if constexpr (HostRoundingMode) {
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Result = _Float_ToGPR_S(GPRSize, SrcElementSize, Src.Low);
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} else {
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Result = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src.Low);
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}
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StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
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Ref Result = CVTFPR_To_GPRImpl(Op, Src.Low, SrcElementSize, HostRoundingMode);
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StoreResult(GPRClass, Op, Result, OpSize::iInvalid);
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}
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void OpDispatchBuilder::AVX128_VANDN(OpcodeArgs) {
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@@ -1614,38 +1604,20 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs) {
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auto Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, !Is128BitSrc);
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RefPair Result {};
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if (SrcElementSize == OpSize::i64Bit) {
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///< Special case for VCVTPD2DQ/CVTTPD2DQ because it has weird rounding requirements.
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Result.Low = _Vector_F64ToI32(OpSize::i128Bit, Src.Low, HostRoundingMode ? Round_Host : Round_Towards_Zero, Is128BitSrc);
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if (!Is128BitSrc) {
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// Also convert the upper 128-bit lane
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auto ResultHigh = _Vector_F64ToI32(OpSize::i128Bit, Src.High, HostRoundingMode ? Round_Host : Round_Towards_Zero, false);
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// Zip the two halves together in to the lower 128-bits
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Result.Low = _VZip(OpSize::i128Bit, OpSize::i64Bit, Result.Low, ResultHigh);
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}
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} else {
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auto Convert = [this](Ref Src) -> Ref {
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auto ElementSize = SrcElementSize;
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if (HostRoundingMode) {
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return _Vector_FToS(OpSize::i128Bit, ElementSize, Src);
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} else {
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return _Vector_FToZS(OpSize::i128Bit, ElementSize, Src);
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}
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};
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Result.Low = Convert(Src.Low);
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if (!Is128BitSrc) {
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Result.High = Convert(Src.High);
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}
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}
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if (SrcElementSize == OpSize::i64Bit || Is128BitSrc) {
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Result.Low = Vector_CVT_Float_To_Int32Impl(Op, OpSize::i128Bit, Src.Low, OpSize::i128Bit, SrcElementSize, HostRoundingMode, Is128BitSrc);
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if (Is128BitSrc) {
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// Zero the upper 128-bit lane of the result.
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Result = AVX128_Zext(Result.Low);
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} else {
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Result.High = Vector_CVT_Float_To_Int32Impl(Op, OpSize::i128Bit, Src.High, OpSize::i128Bit, SrcElementSize, HostRoundingMode, false);
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// Also convert the upper 128-bit lane
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if (SrcElementSize == OpSize::i64Bit) {
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// Zip the two halves together in to the lower 128-bits
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Result.Low = _VZip(OpSize::i128Bit, OpSize::i64Bit, Result.Low, Result.High);
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// Zero the upper 128-bit lane of the result.
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Result = AVX128_Zext(Result.Low);
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}
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}
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AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
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@@ -2067,6 +2067,24 @@ void OpDispatchBuilder::AVXCVTGPR_To_FPR(OpcodeArgs) {
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template void OpDispatchBuilder::AVXCVTGPR_To_FPR<OpSize::i32Bit>(OpcodeArgs);
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template void OpDispatchBuilder::AVXCVTGPR_To_FPR<OpSize::i64Bit>(OpcodeArgs);
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Ref OpDispatchBuilder::CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSize SrcElementSize, bool HostRoundingMode) {
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// GPR size is determined by REX.W
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// Source Element size is determined by instruction
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const auto GPRSize = OpSizeFromDst(Op);
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if (HostRoundingMode) {
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Src = _Vector_FToI(SrcElementSize, SrcElementSize, Src, Round_Host);
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}
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Ref Converted = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src);
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bool Dst32 = GPRSize == OpSize::i32Bit;
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Ref MaxI = Dst32 ? _Constant(0x80000000) : _Constant(0x8000000000000000);
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Ref MaxF = LoadAndCacheNamedVectorConstant(SrcElementSize, (SrcElementSize == OpSize::i32Bit) ?
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(Dst32 ? NAMED_VECTOR_CVTMAX_F32_I32 : NAMED_VECTOR_CVTMAX_F32_I64) :
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(Dst32 ? NAMED_VECTOR_CVTMAX_F64_I32 : NAMED_VECTOR_CVTMAX_F64_I64));
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return _Select(GPRSize, SrcElementSize, CondClassType {FEXCore::IR::COND_FGT}, MaxF, Src, Converted, MaxI);
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}
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template<IR::OpSize SrcElementSize, bool HostRoundingMode>
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void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) {
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// If loading a vector, use the full size, so we don't
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@@ -2074,18 +2092,8 @@ void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) {
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// memory, then we want to load the element size exactly.
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const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : OpSizeFromSrc(Op);
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Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags);
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// GPR size is determined by REX.W
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// Source Element size is determined by instruction
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const auto GPRSize = OpSizeFromDst(Op);
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if constexpr (HostRoundingMode) {
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Src = _Float_ToGPR_S(GPRSize, SrcElementSize, Src);
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} else {
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Src = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src);
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}
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StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Src, GPRSize, OpSize::iInvalid);
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Ref Result = CVTFPR_To_GPRImpl(Op, Src, SrcElementSize, HostRoundingMode);
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StoreResult(GPRClass, Op, Result, OpSize::iInvalid);
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}
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template void OpDispatchBuilder::CVTFPR_To_GPR<OpSize::i32Bit, true>(OpcodeArgs);
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@@ -2127,43 +2135,40 @@ void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs) {
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template void OpDispatchBuilder::Vector_CVT_Int_To_Float<OpSize::i32Bit, true>(OpcodeArgs);
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template void OpDispatchBuilder::Vector_CVT_Int_To_Float<OpSize::i32Bit, false>(OpcodeArgs);
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Ref OpDispatchBuilder::Vector_CVT_Float_To_IntImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode) {
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const auto DstSize = OpSizeFromDst(Op);
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auto ElementSize = SrcElementSize;
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Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
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if (SrcElementSize == OpSize::i64Bit) {
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Src = _Vector_FToF(DstSize, SrcElementSize >> 1, Src, SrcElementSize);
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ElementSize = ElementSize >> 1;
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}
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Ref OpDispatchBuilder::Vector_CVT_Float_To_Int32Impl(OpcodeArgs, IR::OpSize DstSize, Ref Src, IR::OpSize SrcSize, IR::OpSize SrcElementSize,
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bool HostRoundingMode, bool ZeroUpperHalf) {
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if (HostRoundingMode) {
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return _Vector_FToS(DstSize, ElementSize, Src);
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} else {
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return _Vector_FToZS(DstSize, ElementSize, Src);
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Src = _Vector_FToI(SrcSize, SrcElementSize, Src, Round_Host);
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}
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OpSize OverflowConstSize = ZeroUpperHalf && SrcElementSize == OpSize::i64Bit ? DstSize / 2 : DstSize;
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Ref MaxI = LoadAndCacheNamedVectorConstant(OverflowConstSize, NAMED_VECTOR_CVTMAX_I32);
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Ref Converted {}, Cmp {};
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if (SrcElementSize == OpSize::i64Bit) {
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Ref MaxF = LoadAndCacheNamedVectorConstant(SrcSize, NAMED_VECTOR_CVTMAX_F64_I32);
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Converted = _Vector_F64ToI32(DstSize, Src, Round_Towards_Zero, ZeroUpperHalf);
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Cmp = _VFCMPGT(SrcSize, OpSize::i64Bit, MaxF, Src);
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Cmp = _VUShrNI(DstSize, OpSize::i64Bit, Cmp, 32);
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} else {
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Ref MaxF = LoadAndCacheNamedVectorConstant(DstSize, NAMED_VECTOR_CVTMAX_F32_I32);
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Converted = _Vector_FToZS(DstSize, OpSize::i32Bit, Src);
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Cmp = _VFCMPGT(DstSize, OpSize::i32Bit, MaxF, Src);
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}
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return _VBSL(DstSize, Cmp, Converted, MaxI);
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}
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template<IR::OpSize SrcElementSize, bool HostRoundingMode>
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void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs) {
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const auto DstSize = OpSizeFromDst(Op);
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Ref Result {};
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if (SrcElementSize == OpSize::i64Bit) {
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///< Special case for CVTTPD2DQ because it has weird rounding requirements.
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Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
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Result = _Vector_F64ToI32(DstSize, Src, HostRoundingMode ? Round_Host : Round_Towards_Zero, true);
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} else {
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Result = Vector_CVT_Float_To_IntImpl(Op, SrcElementSize, HostRoundingMode);
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}
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Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
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Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, OpSizeFromSrc(Op), SrcElementSize, HostRoundingMode, true);
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StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
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}
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template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i32Bit, false>(OpcodeArgs);
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template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i32Bit, true>(OpcodeArgs);
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template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i32Bit, false>(OpcodeArgs);
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template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i64Bit, true>(OpcodeArgs);
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template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i64Bit, false>(OpcodeArgs);
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@@ -2257,23 +2262,10 @@ void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs) {
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// unnecessarily zero extend the vector. Otherwise, if
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// memory, then we want to load the element size exactly.
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const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : OpSizeFromSrc(Op);
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const auto DstSize = OpSizeFromDst(Op);
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Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags);
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auto ElementSize = SrcElementSize;
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const auto Size = OpSizeFromDst(Op);
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if (SrcElementSize == OpSize::i64Bit) {
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Src = _Vector_FToF(Size, SrcElementSize >> 1, Src, SrcElementSize);
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ElementSize = ElementSize >> 1;
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}
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if constexpr (HostRoundingMode) {
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Src = _Vector_FToS(Size, ElementSize, Src);
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} else {
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Src = _Vector_FToZS(Size, ElementSize, Src);
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}
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StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, OpSize::iInvalid);
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Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, SrcSize, SrcElementSize, HostRoundingMode, false /* TODO? */);
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StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
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}
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template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int<OpSize::i32Bit, false>(OpcodeArgs);
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@@ -209,6 +209,22 @@ static void PrintArg(fextl::stringstream* out, [[maybe_unused]] const IRListView
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return "x87_log10_2";
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case NamedVectorConstant::NAMED_VECTOR_X87_LOG_2:
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return "x87_log2";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32:
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return "cvtmax_f32_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32_UPPER:
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return "cvtmax_f32_i32_upper";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I64:
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return "cvtmax_f32_i64";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32:
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return "cvtmax_f64_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32_UPPER:
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return "cvtmax_f64_i32_upper";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I64:
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return "cvtmax_f64_i64";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I32:
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return "cvtmax_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I64:
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return "cvtmax_i64";
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default:
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return "<Unknown Named Vector Constant>";
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}
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@@ -71,6 +71,15 @@ enum NamedVectorConstant : uint8_t {
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NAMED_VECTOR_X87_LOG10_2,
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NAMED_VECTOR_X87_LOG_2,
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NAMED_VECTOR_CVTMAX_F32_I32,
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NAMED_VECTOR_CVTMAX_F32_I32_UPPER,
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NAMED_VECTOR_CVTMAX_F32_I64,
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NAMED_VECTOR_CVTMAX_F64_I32,
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NAMED_VECTOR_CVTMAX_F64_I32_UPPER,
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NAMED_VECTOR_CVTMAX_F64_I64,
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NAMED_VECTOR_CVTMAX_I32,
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NAMED_VECTOR_CVTMAX_I64,
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NAMED_VECTOR_CONST_POOL_MAX,
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// Beginning of named constants that don't have a constant pool backing.
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NAMED_VECTOR_ZERO = NAMED_VECTOR_CONST_POOL_MAX,
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