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instcountci: Implement address size modifier handling in CMPSOp and SCASOp for 64bits

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Paulo Matos committed 2025-11-20 13:42:19 +01:00
1 parent ba71e79e54
commit de10154f29
3 files changed
+43 -52
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unittests/InstructionCountCI/FEXOpt/MultiInst.json
+16 -16
View File
@@ -215,8 +215,8 @@
"mov w20, #0x1",
"ldrb w21, [x10]",
"strb w21, [x11]",
"add x10, x10, #0x1 (1)",
"add x11, x11, #0x1 (1)",
"add x10, x10, x20",
"add x11, x11, x20",
"strb w20, [x28, #1018]"
]
},
@@ -235,8 +235,8 @@
"mov w20, #0x1",
"ldrh w21, [x10]",
"strh w21, [x11]",
"add x10, x10, #0x2 (2)",
"add x11, x11, #0x2 (2)",
"add x10, x10, x20, lsl #1",
"add x11, x11, x20, lsl #1",
"strb w20, [x28, #1018]"
]
},
@@ -255,8 +255,8 @@
"mov w20, #0x1",
"ldr w21, [x10]",
"str w21, [x11]",
"add x10, x10, #0x4 (4)",
"add x11, x11, #0x4 (4)",
"add x10, x10, x20, lsl #2",
"add x11, x11, x20, lsl #2",
"strb w20, [x28, #1018]"
]
},
@@ -275,8 +275,8 @@
"mov w20, #0x1",
"ldr x21, [x10]",
"str x21, [x11]",
"add x10, x10, #0x8 (8)",
"add x11, x11, #0x8 (8)",
"add x10, x10, x20, lsl #3",
"add x11, x11, x20, lsl #3",
"strb w20, [x28, #1018]"
]
},
@@ -295,8 +295,8 @@
"mov x20, #0xffffffffffffffff",
"ldrb w21, [x10]",
"strb w21, [x11]",
"sub x10, x10, #0x1 (1)",
"sub x11, x11, #0x1 (1)",
"add x10, x10, x20",
"add x11, x11, x20",
"strb w20, [x28, #1018]"
]
},
@@ -315,8 +315,8 @@
"mov x20, #0xffffffffffffffff",
"ldrh w21, [x10]",
"strh w21, [x11]",
"sub x10, x10, #0x2 (2)",
"sub x11, x11, #0x2 (2)",
"add x10, x10, x20, lsl #1",
"add x11, x11, x20, lsl #1",
"strb w20, [x28, #1018]"
]
},
@@ -335,8 +335,8 @@
"mov x20, #0xffffffffffffffff",
"ldr w21, [x10]",
"str w21, [x11]",
"sub x10, x10, #0x4 (4)",
"sub x11, x11, #0x4 (4)",
"add x10, x10, x20, lsl #2",
"add x11, x11, x20, lsl #2",
"strb w20, [x28, #1018]"
]
},
@@ -355,8 +355,8 @@
"mov x20, #0xffffffffffffffff",
"ldr x21, [x10]",
"str x21, [x11]",
"sub x10, x10, #0x8 (8)",
"sub x11, x11, #0x8 (8)",
"add x10, x10, x20, lsl #3",
"add x11, x11, x20, lsl #3",
"strb w20, [x28, #1018]"
]
},
unittests/InstructionCountCI/FlagM/Primary.json
+9 -12
View File
@@ -1850,7 +1850,7 @@
]
},
"cmpsw": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": [
"0xa7"
],
@@ -1862,13 +1862,12 @@
"cmp w0, w20, lsl #16",
"sub w26, w21, w20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #1",
"add x10, x10, x20, lsl #1"
]
},
"cmpsd": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": [
"0xa7"
],
@@ -1878,13 +1877,12 @@
"eor x27, x21, x20",
"subs w26, w21, w20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #2",
"add x10, x10, x20, lsl #2"
]
},
"cmpsq": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": [
"0xa7"
],
@@ -1894,9 +1892,8 @@
"eor x27, x21, x20",
"subs x26, x21, x20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #3",
"add x10, x10, x20, lsl #3"
]
},
"repz cmpsb": {
unittests/InstructionCountCI/Primary.json
+18 -24
View File
@@ -2878,7 +2878,7 @@
]
},
"movsw": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": [
"0xa5"
],
@@ -2886,13 +2886,12 @@
"ldrh w20, [x10]",
"strh w20, [x11]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x10, x10, x20",
"add x11, x11, x20"
"add x10, x10, x20, lsl #1",
"add x11, x11, x20, lsl #1"
]
},
"movsd": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": [
"0xa5"
],
@@ -2900,13 +2899,12 @@
"ldr w20, [x10]",
"str w20, [x11]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x10, x10, x20",
"add x11, x11, x20"
"add x10, x10, x20, lsl #2",
"add x11, x11, x20, lsl #2"
]
},
"movsq": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": [
"0xa5"
],
@@ -2914,9 +2912,8 @@
"ldr x20, [x10]",
"str x20, [x11]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x10, x10, x20",
"add x11, x11, x20"
"add x10, x10, x20, lsl #3",
"add x11, x11, x20, lsl #3"
]
},
"rep movsb": {
@@ -3293,7 +3290,7 @@
]
},
"cmpsw": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": [
"0xa7"
],
@@ -3305,13 +3302,12 @@
"cmp w0, w20, lsl #16",
"sub w26, w21, w20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #1",
"add x10, x10, x20, lsl #1"
]
},
"cmpsd": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": [
"0xa7"
],
@@ -3321,13 +3317,12 @@
"eor x27, x21, x20",
"subs w26, w21, w20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #2",
"add x10, x10, x20, lsl #2"
]
},
"cmpsq": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": [
"0xa7"
],
@@ -3337,9 +3332,8 @@
"eor x27, x21, x20",
"subs x26, x21, x20",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x11, x11, x20",
"add x10, x10, x20"
"add x11, x11, x20, lsl #3",
"add x10, x10, x20, lsl #3"
]
},
"repz cmpsb": {