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https://github.com/FEX-Emu/FEX.git
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instcount: Ensure predicate cache is reset when control flow leaves block
This commit is contained in:
Paulo Matos committed
1 parent
3dc7b8d90a
commit
ddd241fe39
1 file changed
+6
-28
@@ -14,13 +14,12 @@
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},
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"Instructions": {
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"fstp tword [rax]": {
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"ExpectedInstructionCount": 13,
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"ExpectedInstructionCount": 12,
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"Comment": "Single 80-bit store.",
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"ExpectedArm64ASM": [
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"st1h {z2.h}, p2, [x4]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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@@ -34,7 +33,7 @@
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},
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"2-store 80bit": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 25,
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"ExpectedInstructionCount": 23,
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"x86Insts": [
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"fstp tword [rax]",
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"fstp tword [rax+10]"
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@@ -43,7 +42,6 @@
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"st1h {z2.h}, p2, [x4]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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@@ -55,7 +53,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0xa (10)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -69,7 +66,7 @@
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},
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"8-store 80bit": {
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"x86InstructionCount": 8,
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"ExpectedInstructionCount": 97,
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"ExpectedInstructionCount": 89,
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"x86Insts": [
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"fstp tword [rax]",
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"fstp tword [rax+10]",
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@@ -84,7 +81,6 @@
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"st1h {z2.h}, p2, [x4]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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@@ -96,7 +92,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0xa (10)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -108,7 +103,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x14 (20)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -120,7 +114,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x1e (30)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -132,7 +125,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x28 (40)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -144,7 +136,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x32 (50)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -156,7 +147,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x3c (60)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -168,7 +158,6 @@
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"strb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"ptrue p2.h, vl5",
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"add x21, x4, #0x46 (70)",
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"st1h {z2.h}, p2, [x21]",
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"ldrb w21, [x28, #1298]",
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@@ -181,10 +170,9 @@
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]
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},
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"fld tword [rax]": {
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"ExpectedInstructionCount": 13,
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"ExpectedInstructionCount": 12,
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"Comment": "Single 80-bit store.",
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"ExpectedArm64ASM": [
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"ptrue p2.h, vl5",
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"ld1h {z2.h}, p2/z, [x4]",
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"ldrb w20, [x28, #1019]",
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"mov w21, #0x1",
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@@ -201,16 +189,14 @@
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},
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"2-load 80bit": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 22,
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"ExpectedInstructionCount": 20,
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"x86Insts": [
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"fld tword [rax]",
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"fld tword [rax+10]"
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],
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"ExpectedArm64ASM": [
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"ptrue p2.h, vl5",
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"ld1h {z2.h}, p2/z, [x4]",
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"add x20, x4, #0xa (10)",
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"ptrue p2.h, vl5",
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"ld1h {z3.h}, p2/z, [x20]",
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"ldrb w20, [x28, #1019]",
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"sub w20, w20, #0x2 (2)",
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@@ -233,7 +219,7 @@
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},
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"8-load 80bit": {
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"x86InstructionCount": 8,
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"ExpectedInstructionCount": 59,
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"ExpectedInstructionCount": 51,
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"x86Insts": [
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"fld tword [rax]",
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"fld tword [rax+10]",
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@@ -245,28 +231,20 @@
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"fld tword [rax+70]"
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],
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"ExpectedArm64ASM": [
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"ptrue p2.h, vl5",
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"ld1h {z2.h}, p2/z, [x4]",
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"add x20, x4, #0xa (10)",
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"ptrue p2.h, vl5",
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"ld1h {z3.h}, p2/z, [x20]",
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"add x20, x4, #0x14 (20)",
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"ptrue p2.h, vl5",
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"ld1h {z4.h}, p2/z, [x20]",
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"add x20, x4, #0x1e (30)",
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"ptrue p2.h, vl5",
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"ld1h {z5.h}, p2/z, [x20]",
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"add x20, x4, #0x28 (40)",
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"ptrue p2.h, vl5",
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"ld1h {z6.h}, p2/z, [x20]",
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"add x20, x4, #0x32 (50)",
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"ptrue p2.h, vl5",
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"ld1h {z7.h}, p2/z, [x20]",
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"add x20, x4, #0x3c (60)",
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"ptrue p2.h, vl5",
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"ld1h {z8.h}, p2/z, [x20]",
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"add x20, x4, #0x46 (70)",
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"ptrue p2.h, vl5",
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"ld1h {z9.h}, p2/z, [x20]",
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"ldrb w20, [x28, #1019]",
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"sub w20, w20, #0x8 (8)",
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