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IR: Add missing flag clobbers

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2023-11-01 15:44:36 -04:00
1 parent a586d3823d
commit d75c0f2c50
1 file changed
+6 -3
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FEXCore/Source/Interface/IR/IR.json
+6 -3
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@@ -1348,7 +1348,8 @@
"If either source operand is NaN then return the second operand."
],
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"
"NumElements": "RegisterSize / ElementSize",
"ImplicitFlagClobber": true
},
"FPR = VFMaxScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
"Desc": ["Does a scalar 'max' between Vector1 and Vector2.",
@@ -1361,7 +1362,8 @@
"If either source operand is NaN then return the second operand."
],
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"
"NumElements": "RegisterSize / ElementSize",
"ImplicitFlagClobber": true
},
"FPR = VFSqrtScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
"Desc": ["Does a scalar 'sqrt' on Vector2, inserting in to Vector1 and storing in to the destination.",
@@ -1923,7 +1925,8 @@
"FPR = VCMPEQ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"
"NumElements": "RegisterSize / ElementSize",
"ImplicitFlagClobber": true
},
"FPR = VCMPGT u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {