Merge pull request #5419 from pmatos/f64-scale-f2xm1

JIT-inline F64SCALE and F64F2XM1 for reduced precision x87 path

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -549,6 +549,8 @@ void Dispatcher::EmitDispatcher() {
   EmitF64Sin();
   EmitF64Cos();
   EmitF64Tan();
+  EmitF64F2XM1();
+  EmitF64Scale();
 
   // Interpreter fallbacks
   {
@@ -1246,6 +1248,179 @@ void Dispatcher::EmitF64Tan() {
   dc64(0x4160'0000'0000'0000ULL); // 2^23
 }
 
+void Dispatcher::EmitF64Scale() {
+  // Computes result = src1 * 2^trunc(src2).
+  // Input: VTMP1 = base (src1), VTMP2 = exponent (src2). Output: VTMP1.
+  F64ScaleHandlerAddress = GetCursorAddress<uint64_t>();
+
+  ARMEmitter::ForwardLabel Fallback;
+
+  // save nzcv
+  mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
+  str(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
+
+  // n = trunc(src2).
+  frintz(VTMP2.D(), VTMP2.D());
+
+  // NaN check: NaN != NaN sets V flag.
+  fcmp(VTMP2.D(), VTMP2.D());
+  (void)b(ARMEmitter::Condition::CC_VS, &Fallback);
+
+  fcvtzs(ARMEmitter::Size::i64Bit, TMP1, VTMP2.D());
+
+  // Range check: int_n in [-1022, 1023].
+  cmn(ARMEmitter::Size::i64Bit, TMP1, 1022);
+  (void)b(ARMEmitter::Condition::CC_LT, &Fallback);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, 1023);
+  (void)b(ARMEmitter::Condition::CC_GT, &Fallback);
+
+  // 2^n, then result = src1 * 2^n.
+  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1023);
+  lsl(ARMEmitter::Size::i64Bit, TMP1, TMP1, 52);
+  fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP1);
+  fmul(VTMP1.D(), VTMP1.D(), VTMP2.D());
+
+  // restore nzcv
+  ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
+  msr(ARMEmitter::SystemRegister::NZCV, TMP1);
+
+  ret();
+
+  // Fallback path.
+  (void)Bind(&Fallback);
+  str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64SCALE].ABIHandler));
+  ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64SCALE].Func));
+  blr(TMP1);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+  ret();
+}
+
+void Dispatcher::EmitF64F2XM1() {
+  // JIT-inlined double-precision 2^x - 1 for x in [-1, 1].
+  // Uses argument reduction: split x into n = round(x) and r = x - n,
+  // then compute 2^x - 1 = 2^n * (2^r - 1) + (2^n - 1).
+  // 2^r - 1 is approximated via a 13-term Horner polynomial in r.
+  // Input in VTMP1.D(), output in VTMP1.D().
+  F64F2XM1HandlerAddress = GetCursorAddress<uint64_t>();
+
+  constexpr auto Accum = ARMEmitter::VReg::v2;
+
+  ARMEmitter::ForwardLabel Fallback;
+  ARMEmitter::ForwardLabel OneLabel;
+  ARMEmitter::ForwardLabel C1Label, C2Label, C3Label, C4Label, C5Label, C6Label;
+  ARMEmitter::ForwardLabel C7Label, C8Label, C9Label, C10Label, C11Label, C12Label, C13Label;
+
+  // Save q2.
+  str<ARMEmitter::IndexType::PRE>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, -16);
+
+  // save nzcv
+  mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
+  str(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
+
+  // Range check: |x| > 1.0 -> fallback.
+  fabs(VTMP2.D(), VTMP1.D());
+  ldr(Accum.D(), &OneLabel);
+  fcmp(VTMP2.D(), Accum.D());
+  (void)b(ARMEmitter::Condition::CC_HI, &Fallback);
+
+  // Argument reduction: n = round(x), r = x - n.
+  frinta(VTMP2.D(), VTMP1.D());
+  fcvtzs(ARMEmitter::Size::i64Bit, TMP1, VTMP2.D());
+  fsub(Accum.D(), VTMP1.D(), VTMP2.D());
+
+  // scale = 2^n, scale_m1 = 2^n - 1.
+  // TMP1 = scale bits, TMP3 = scale_m1 bits, Accum = r.
+  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1023);
+  lsl(ARMEmitter::Size::i64Bit, TMP1, TMP1, 52);
+  fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP1);
+  ldr(VTMP1.D(), &OneLabel);
+  fsub(VTMP1.D(), VTMP2.D(), VTMP1.D());
+  fmov(ARMEmitter::Size::i64Bit, TMP3, VTMP1.D());
+
+  // Horner polynomial: p = c1 + r * (c2 + r * (... + r * c13)).
+  ldr(VTMP1.D(), &C13Label);
+  ldr(VTMP2.D(), &C12Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C11Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C10Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C9Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C8Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C7Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C6Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C5Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C4Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C3Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C2Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+  ldr(VTMP2.D(), &C1Label);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+
+  // q = r * p, then result = scale * q + scale_m1.
+  fmul(VTMP1.D(), Accum.D(), VTMP1.D());
+  fmov(ARMEmitter::Size::i64Bit, Accum.D(), TMP1);
+  fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP3);
+  fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
+
+  // restore nzcv
+  ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
+  msr(ARMEmitter::SystemRegister::NZCV, TMP1);
+
+  // Restore q2 and return.
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 16);
+  ret();
+
+  // Fallback path.
+  (void)Bind(&Fallback);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 16);
+  str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64F2XM1].ABIHandler));
+  ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64F2XM1].Func));
+  blr(TMP1);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+  ret();
+
+  // Constant pool
+  Align(16);
+  (void)Bind(&OneLabel);
+  dc64(0x3FF0'0000'0000'0000ULL); // 1.0
+  (void)Bind(&C1Label);
+  dc64(0x3FE6'2E42'FEFA'39EFULL); // ln(2)
+  (void)Bind(&C2Label);
+  dc64(0x3FCE'BFBD'FF82'C58EULL);
+  (void)Bind(&C3Label);
+  dc64(0x3FAC'6B08'D704'A0BEULL);
+  (void)Bind(&C4Label);
+  dc64(0x3F83'B2AB'6FBA'4E76ULL);
+  (void)Bind(&C5Label);
+  dc64(0x3F55'D87F'E78A'672FULL);
+  (void)Bind(&C6Label);
+  dc64(0x3F24'3091'2F86'C785ULL);
+  (void)Bind(&C7Label);
+  dc64(0x3EEF'FCBF'C588'B0C2ULL);
+  (void)Bind(&C8Label);
+  dc64(0x3EB6'2C02'23A5'C821ULL);
+  (void)Bind(&C9Label);
+  dc64(0x3E7B'5253'D395'E7C0ULL);
+  (void)Bind(&C10Label);
+  dc64(0x3E3E'4CF5'158B'8EC5ULL);
+  (void)Bind(&C11Label);
+  dc64(0x3DFE'8CAC'7351'BB20ULL);
+  (void)Bind(&C12Label);
+  dc64(0x3DBC'3BD6'50FC'2981ULL);
+  (void)Bind(&C13Label);
+  dc64(0x3D78'1619'3166'D0F5ULL);
+}
+
 uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
   auto Address = GetCursorAddress<uint64_t>();
   constexpr static auto FallbackPointerReg = TMP4;
@@ -1693,6 +1868,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
     Ptrs.F64SinHandler = F64SinHandlerAddress;
     Ptrs.F64CosHandler = F64CosHandlerAddress;
     Ptrs.F64TanHandler = F64TanHandlerAddress;
+    Ptrs.F64F2XM1Handler = F64F2XM1HandlerAddress;
+    Ptrs.F64ScaleHandler = F64ScaleHandlerAddress;
 
     // Fill in the fallback handlers
     InterpreterOps::FillFallbackIndexPointers(Ptrs.FallbackHandlerPointers, &ABIPointers[0]);

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -99,10 +99,12 @@ private:
   uint64_t LUDIVHandlerAddress {};
   uint64_t LDIVHandlerAddress {};
 
-  // F64 trig shared handlers
+  // F64 reduced-precision shared handlers
   uint64_t F64SinHandlerAddress {};
   uint64_t F64CosHandlerAddress {};
   uint64_t F64TanHandlerAddress {};
+  uint64_t F64F2XM1HandlerAddress {};
+  uint64_t F64ScaleHandlerAddress {};
 
   void EmitDispatcher();
   uint64_t GenerateABICall(FallbackABI ABI);
@@ -117,6 +119,8 @@ private:
   void EmitF64Sin();
   void EmitF64Cos();
   void EmitF64Tan();
+  void EmitF64F2XM1();
+  void EmitF64Scale();
 
   FEX_CONFIG_OPT(DisableL2Cache, DISABLEL2CACHE);
 };

FEXCore/Source/Interface/Core/JIT/VectorOps.cpp

@@ -4651,4 +4651,33 @@ DEF_OP(F64TAN) {
 }
 
 
+DEF_OP(F64SCALE) {
+  const auto Op = IROp->C<IR::IROp_F64SCALE>();
+  const auto Src1 = GetVReg(Op->Src1);
+  const auto Src2 = GetVReg(Op->Src2);
+  const auto Dst = GetVReg(Node);
+
+  fmov(VTMP1.D(), Src1.D());
+  fmov(VTMP2.D(), Src2.D());
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.F64ScaleHandler));
+  str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
+  blr(TMP1);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+  fmov(Dst.D(), VTMP1.D());
+}
+
+DEF_OP(F64F2XM1) {
+  const auto Op = IROp->C<IR::IROp_F64F2XM1>();
+  const auto Src = GetVReg(Op->Src);
+  const auto Dst = GetVReg(Node);
+
+  fmov(VTMP1.D(), Src.D());
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.F64F2XM1Handler));
+  str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
+  blr(TMP1);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+  fmov(Dst.D(), VTMP1.D());
+}
+
+
 } // namespace FEXCore::CPU

FEXCore/Source/Interface/IR/IR.json

@@ -2770,11 +2770,11 @@
       },
       "FPR = F64SCALE FPR:$Src1, FPR:$Src2": {
         "DestSize": "OpSize::i64Bit",
-        "JITDispatch": false
+        "JITDispatch": true
       },
       "FPR = F64F2XM1 FPR:$Src": {
         "DestSize": "OpSize::i64Bit",
-        "JITDispatch": false
+        "JITDispatch": true
       },
       "FPR = F64FYL2X FPR:$Src, FPR:$Src2": {
         "DestSize": "OpSize::i64Bit",

FEXCore/include/FEXCore/Core/CoreState.h

@@ -379,6 +379,8 @@ struct JITPointers {
   uint64_t F64SinHandler {};
   uint64_t F64CosHandler {};
   uint64_t F64TanHandler {};
+  uint64_t F64F2XM1Handler {};
+  uint64_t F64ScaleHandler {};
   /**  @} */
 
   // Copy of process-wide named vector constants data.

unittests/ASM/X87_F64/D9_F0_02_F64.asm

@@ -0,0 +1,53 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x3FDA827999FCEF32",
+    "RBX": "0xBFE0000000000000",
+    "RCX": "0x3FF0000000000000"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1" }
+}
+%endif
+
+; Test F2XM1 with non-trivial inputs
+; Test 1: 2^0.5 - 1 = sqrt(2) - 1 ~= 0.41421356237309515
+; Test 2: 2^(-1) - 1 = -0.5
+; Test 3: 2^1 - 1 = 1.0
+
+mov rdx, 0xe0000000
+
+; Test 1: f2xm1(0.5)
+lea rsi, [rel data_half]
+fld tword [rsi]
+f2xm1
+fstp qword [rdx]
+mov rax, [rdx]
+
+; Test 2: f2xm1(-1.0)
+lea rsi, [rel data_neg1]
+fld tword [rsi]
+f2xm1
+fstp qword [rdx]
+mov rbx, [rdx]
+
+; Test 3: f2xm1(1.0)
+lea rsi, [rel data_pos1]
+fld tword [rsi]
+f2xm1
+fstp qword [rdx]
+mov rcx, [rdx]
+
+hlt
+
+align 8
+data_half:
+  dt 0.5
+  dq 0
+
+data_neg1:
+  dt -1.0
+  dq 0
+
+data_pos1:
+  dt 1.0
+  dq 0

unittests/ASM/X87_F64/D9_FD_3_F64.asm

@@ -0,0 +1,54 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4098000000000000",
+    "RBX": "0x3FF8000000000000"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1" }
+}
+%endif
+
+; Test FSCALE with double-precision verification
+; Test 1: 1.5 * 2^10 = 1536.0 (0x4098000000000000)
+; Test 2: 3.0 * 2^(-1) = 1.5  (0x3FF8000000000000)
+
+mov rcx, 0xe0000000
+
+; Test 1: 1.5 * 2^10
+lea rdx, [rel data_exp1]
+fld tword [rdx]
+lea rdx, [rel data_base1]
+fld tword [rdx]
+fscale
+fstp qword [rcx]
+mov rax, [rcx]
+fstp st0
+
+; Test 2: 3.0 * 2^(-1)
+lea rdx, [rel data_exp2]
+fld tword [rdx]
+lea rdx, [rel data_base2]
+fld tword [rdx]
+fscale
+fstp qword [rcx]
+mov rbx, [rcx]
+fstp st0
+
+hlt
+
+align 8
+data_base1:
+  dt 1.5
+  dq 0
+
+data_exp1:
+  dt 10.0
+  dq 0
+
+data_base2:
+  dt 3.0
+  dq 0
+
+data_exp2:
+  dt -1.0
+  dq 0

unittests/InstructionCountCI/AVX128/VEX_map1.json

@@ -485,7 +485,7 @@
       ],
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3168]",
+        "ldr q3, [x28, #3184]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -499,7 +499,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #192]",
         "ushr v3.4s, v16.4s, #31",
-        "ldr q4, [x28, #3168]",
+        "ldr q4, [x28, #3184]",
         "ushl v3.4s, v3.4s, v4.4s",
         "addv s3, v3.4s",
         "mov w20, v3.s[0]",
@@ -3884,7 +3884,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d",
         "stp xzr, xzr, [x28, #192]"
@@ -3898,7 +3898,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3072]",
+        "ldr q4, [x28, #3088]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.2d, v17.2d, v5.2d",
         "eor v3.16b, v3.16b, v4.16b",
@@ -3912,7 +3912,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s",
         "stp xzr, xzr, [x28, #192]"
@@ -3926,7 +3926,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3040]",
+        "ldr q4, [x28, #3056]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.4s, v17.4s, v5.4s",
         "eor v3.16b, v3.16b, v4.16b",
@@ -4097,7 +4097,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4113,7 +4113,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #192]",
-        "ldr q3, [x28, #3296]",
+        "ldr q3, [x28, #3312]",
         "cmlt v4.16b, v16.16b, #0",
         "and v4.16b, v4.16b, v3.16b",
         "addp v4.16b, v4.16b, v4.16b",

unittests/InstructionCountCI/AVX128/VEX_map2.json

@@ -1917,7 +1917,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3008]",
+        "ldr q2, [x28, #3024]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -4485,7 +4485,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4502,7 +4502,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4518,7 +4518,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4535,7 +4535,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4551,7 +4551,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4568,7 +4568,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4584,7 +4584,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4601,7 +4601,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -5541,7 +5541,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5558,7 +5558,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5574,7 +5574,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5591,7 +5591,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5607,7 +5607,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5624,7 +5624,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5640,7 +5640,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5657,7 +5657,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5673,7 +5673,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5689,7 +5689,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5704,7 +5704,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5720,7 +5720,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5735,7 +5735,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5751,7 +5751,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5766,7 +5766,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5782,7 +5782,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",

unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json

@@ -2843,7 +2843,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2860,7 +2860,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2876,7 +2876,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2893,7 +2893,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2909,7 +2909,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2926,7 +2926,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2942,7 +2942,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2959,7 +2959,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -3879,7 +3879,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3896,7 +3896,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3912,7 +3912,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3929,7 +3929,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3945,7 +3945,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3962,7 +3962,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3978,7 +3978,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3995,7 +3995,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4011,7 +4011,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4027,7 +4027,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3040]",
+        "ldr q5, [x28, #3056]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4042,7 +4042,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4058,7 +4058,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4073,7 +4073,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4089,7 +4089,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4104,7 +4104,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4120,7 +4120,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",

unittests/InstructionCountCI/AVX128/VEX_map3.json

@@ -337,7 +337,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3200]",
+        "ldr q2, [x28, #3216]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -348,7 +348,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -369,7 +369,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3232]",
+        "ldr q2, [x28, #3248]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -391,7 +391,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -412,7 +412,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3264]",
+        "ldr q2, [x28, #3280]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -423,7 +423,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
+        "ldr q2, [x28, #3296]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -3488,7 +3488,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3184]",
+        "ldr q3, [x28, #3200]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
@@ -3502,7 +3502,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3184]",
+        "ldr q3, [x28, #3200]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",

unittests/InstructionCountCI/Crypto/H0F3A.json

@@ -55,7 +55,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -84,7 +84,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3568]",
+        "ldr q2, [x28, #3584]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -101,7 +101,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -118,7 +118,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3600]",
+        "ldr q2, [x28, #3616]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -135,7 +135,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3616]",
+        "ldr q2, [x28, #3632]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",

unittests/InstructionCountCI/FlagM/Secondary.json

@@ -1608,7 +1608,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3296]",
+        "ldr d3, [x28, #3312]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/FlagM/Secondary_OpSize.json

@@ -37,7 +37,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/FlagM/VEX_map1.json

@@ -68,7 +68,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/FlagM/x87-HalfLife.json

@@ -557,7 +557,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4]",
         "str x30, [sp, #-16]!",
@@ -567,7 +567,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q4, [x28, #3552]",
+        "ldr q4, [x28, #3568]",
         "bic v3.16b, v3.16b, v4.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
@@ -598,7 +598,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #4]",
         "str x30, [sp, #-16]!",
@@ -608,7 +608,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "bic v3.16b, v3.16b, v5.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
@@ -639,7 +639,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #8]",
         "str x30, [sp, #-16]!",
@@ -649,7 +649,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "bic v3.16b, v3.16b, v6.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",

unittests/InstructionCountCI/FlagM/x87-Oblivion.json

@@ -3789,7 +3789,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -3839,7 +3839,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #28]",
         "str x30, [sp, #-16]!",
@@ -4002,7 +4002,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4052,7 +4052,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #60]",
         "str x30, [sp, #-16]!",
@@ -4238,7 +4238,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4259,7 +4259,7 @@
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
         "str s2, [x8, #176]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v9.16b, v2.16b",
         "ldr s9, [x8, #8]",
         "str x30, [sp, #-16]!",
@@ -7530,7 +7530,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q10, [x28, #3552]",
+        "ldr q10, [x28, #3568]",
         "eor v8.16b, v8.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7621,7 +7621,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3552]",
+        "ldr q11, [x28, #3568]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7679,7 +7679,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3552]",
+        "ldr q11, [x28, #3568]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7952,7 +7952,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v7.16b, v7.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -8112,7 +8112,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1024]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8130,7 +8130,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8141,7 +8141,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1152]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v6.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8159,7 +8159,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8177,7 +8177,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8188,7 +8188,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1344]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v11.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8206,7 +8206,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8217,7 +8217,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1472]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v10.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8228,7 +8228,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1536]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v9.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8239,7 +8239,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1600]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v8.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8249,7 +8249,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1664]",
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "eor v2.16b, v7.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -12538,7 +12538,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v3.16b, v2.16b, v3.16b",
         "ldr s4, [x4]",
         "str x30, [sp, #-16]!",
@@ -12580,7 +12580,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "eor v5.16b, v4.16b, v5.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12615,7 +12615,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v6.16b, v5.16b, v6.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12650,7 +12650,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3552]",
+        "ldr q7, [x28, #3568]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12685,7 +12685,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q8, [x28, #3552]",
+        "ldr q8, [x28, #3568]",
         "eor v8.16b, v7.16b, v8.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12720,7 +12720,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q9, [x28, #3552]",
+        "ldr q9, [x28, #3568]",
         "eor v9.16b, v8.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12755,7 +12755,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3552]",
+        "ldr q10, [x28, #3568]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12789,7 +12789,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3552]",
+        "ldr q10, [x28, #3568]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12823,7 +12823,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3552]",
+        "ldr q10, [x28, #3568]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -20012,7 +20012,7 @@
         "mov x8, x26",
         "str s2, [x8, #16]",
         "uxtb w7, w4",
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "str w7, [x8, #56]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -21708,7 +21708,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "add x14, x28, x20, lsl #4",
         "ldr q3, [x14, #1056]",
@@ -21763,7 +21763,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "eor v2.16b, v2.16b, v5.16b",
         "mov w14, #0x7b90",
         "movk w14, #0xa7, lsl #16",
@@ -21827,7 +21827,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v2.16b, v2.16b, v6.16b",
         "mov w15, #0x7b80",
         "movk w15, #0xa7, lsl #16",
@@ -21955,7 +21955,7 @@
         "fmov s7, s0",
         "str s7, [x8, #64]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3552]",
+        "ldr q7, [x28, #3568]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -21979,7 +21979,7 @@
         "fmov s7, s0",
         "str s7, [x8, #68]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3552]",
+        "ldr q7, [x28, #3568]",
         "eor v2.16b, v2.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -22005,7 +22005,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "eor v5.16b, v2.16b, v5.16b",
         "ldr d7, [x15]",
         "str x30, [sp, #-16]!",

unittests/InstructionCountCI/FlagM/x87-Psychonauts.json

@@ -10858,7 +10858,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3552]",
+        "ldr q4, [x28, #3568]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -10903,7 +10903,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x12, x28, x22, lsl #4",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldur s5, [x5, #-4]",
         "str x30, [sp, #-16]!",
@@ -11028,7 +11028,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x5, #4]",
         "str x30, [sp, #-16]!",
@@ -12174,7 +12174,7 @@
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q5, [x28, #3552]",
+        "ldr q5, [x28, #3568]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldr s5, [x9, #12]",
         "str x30, [sp, #-16]!",
@@ -12302,7 +12302,7 @@
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x9, #4]",
         "str x30, [sp, #-16]!",
@@ -14021,7 +14021,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3552]",
+        "ldr q4, [x28, #3568]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -22326,7 +22326,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x13, x28, x22, lsl #4",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w14, w4, w10, lsl #2",
         "ldur s6, [x14, #-4]",
@@ -22927,7 +22927,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #4]",
@@ -23397,7 +23397,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3552]",
+        "ldr q7, [x28, #3568]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -23485,7 +23485,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3552]",
+        "ldr q6, [x28, #3568]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #12]",
@@ -25586,7 +25586,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3552]",
+        "ldr q7, [x28, #3568]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",

unittests/InstructionCountCI/FlagM/x87.json

@@ -2468,7 +2468,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2482,7 +2482,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2548,7 +2548,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2568,7 +2568,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3344]",
+        "ldr q2, [x28, #3360]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2588,7 +2588,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2608,7 +2608,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2628,7 +2628,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2648,7 +2648,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2742,7 +2742,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3328]",
+        "ldr q3, [x28, #3344]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
@@ -2900,7 +2900,7 @@
         "0xd9 11b 0xf9 /7"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q3, [x21, #1056]",

unittests/InstructionCountCI/FlagM/x87_f64.json

@@ -2142,7 +2142,7 @@
       ]
     },
     "f2xm1": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 10,
       "Comment": [
         "0xd9 11b 0xf0 /6"
       ],
@@ -2150,10 +2150,9 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #2248]",
-        "ldr x3, [x28, #2256]",
+        "ldr x0, [x28, #3008]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -2444,7 +2443,7 @@
       ]
     },
     "fscale": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xd9 11b 0xfd /7"
       ],
@@ -2456,11 +2455,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2312]",
-        "ldr x3, [x28, #2320]",
+        "ldr x0, [x28, #3016]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",

unittests/InstructionCountCI/H0F38.json

@@ -685,7 +685,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3008]",
+        "ldr q2, [x28, #3024]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",

unittests/InstructionCountCI/H0F3A.json

@@ -327,7 +327,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3200]",
+        "ldr q2, [x28, #3216]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -337,7 +337,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -356,7 +356,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3232]",
+        "ldr q2, [x28, #3248]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -376,7 +376,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -395,7 +395,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3264]",
+        "ldr q2, [x28, #3280]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -405,7 +405,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
+        "ldr q2, [x28, #3296]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },

unittests/InstructionCountCI/Secondary.json

@@ -651,7 +651,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3168]",
+        "ldr q3, [x28, #3184]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -662,7 +662,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3168]",
+        "ldr q3, [x28, #3184]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3697,7 +3697,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3296]",
+        "ldr d3, [x28, #3312]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/Secondary_OpSize.json

@@ -1259,7 +1259,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1315,7 +1315,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/Secondary_REP.json

@@ -118,7 +118,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3424]",
+        "ldr s2, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -132,7 +132,7 @@
         "ldr s2, [x6]",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3424]",
+        "ldr s3, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -145,7 +145,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3456]",
+        "ldr s2, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -159,7 +159,7 @@
         "ldr s2, [x6]",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -173,7 +173,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3424]",
+        "ldr s3, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -188,7 +188,7 @@
         "frinti s2, s2",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3424]",
+        "ldr s3, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -202,7 +202,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -217,7 +217,7 @@
         "frinti s2, s2",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -296,8 +296,8 @@
       "ExpectedInstructionCount": 6,
       "Comment": "0xf3 0x0f 0x5b",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
-        "ldr q3, [x28, #3424]",
+        "ldr q2, [x28, #3536]",
+        "ldr q3, [x28, #3440]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",

unittests/InstructionCountCI/Secondary_REPNE.json

@@ -503,7 +503,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]

unittests/InstructionCountCI/VEX_map1.json

@@ -3271,7 +3271,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3424]",
+        "ldr s2, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -3286,7 +3286,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3456]",
+        "ldr s2, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -3301,7 +3301,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, d16",
         "mov w21, #0x80000000",
-        "ldr d2, [x28, #3472]",
+        "ldr d2, [x28, #3488]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel w4, w20, w21, gt",
@@ -3316,7 +3316,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, d16",
         "mov x21, #0x8000000000000000",
-        "ldr d2, [x28, #3504]",
+        "ldr d2, [x28, #3520]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel x4, x20, x21, gt",
@@ -3332,7 +3332,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3424]",
+        "ldr s3, [x28, #3440]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -3348,7 +3348,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -3364,7 +3364,7 @@
         "frinti d2, d16",
         "fcvtzs w20, d2",
         "mov w21, #0x80000000",
-        "ldr d3, [x28, #3472]",
+        "ldr d3, [x28, #3488]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel w4, w20, w21, gt",
@@ -3380,7 +3380,7 @@
         "frinti d2, d16",
         "fcvtzs x20, d2",
         "mov x21, #0x8000000000000000",
-        "ldr d3, [x28, #3504]",
+        "ldr d3, [x28, #3520]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel x4, x20, x21, gt",
@@ -3643,8 +3643,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.4s, v17.4s",
-        "ldr q3, [x28, #3520]",
-        "ldr q4, [x28, #3424]",
+        "ldr q3, [x28, #3536]",
+        "ldr q4, [x28, #3440]",
         "fcvtzs v5.4s, v2.4s",
         "fcmgt v2.4s, v4.4s, v2.4s",
         "mov v16.16b, v2.16b",
@@ -3678,8 +3678,8 @@
         "Map 1 0b10 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
-        "ldr q3, [x28, #3424]",
+        "ldr q2, [x28, #3536]",
+        "ldr q3, [x28, #3440]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
@@ -4427,7 +4427,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4450,7 +4450,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4587,7 +4587,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4979,8 +4979,8 @@
         "Map 1 0b01 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d2, [x28, #3520]",
-        "ldr q3, [x28, #3472]",
+        "ldr d2, [x28, #3536]",
+        "ldr q3, [x28, #3488]",
         "fcvtzs z4.s, p6/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
         "mov v4.8b, v4.8b",
@@ -4996,7 +4996,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
+        "ldr q2, [x28, #3536]",
         "ldr x0, [x28, #2592]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -5040,8 +5040,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.2d, v17.2d",
-        "ldr d3, [x28, #3520]",
-        "ldr q4, [x28, #3472]",
+        "ldr d3, [x28, #3536]",
+        "ldr q4, [x28, #3488]",
         "fcvtzs z5.s, p6/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",
         "mov v5.8b, v5.8b",
@@ -5058,7 +5058,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3520]",
+        "ldr q3, [x28, #3536]",
         "ldr x0, [x28, #2592]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",

unittests/InstructionCountCI/VEX_map1_FRINTTS.json

@@ -173,7 +173,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
+        "ldr q2, [x28, #3536]",
         "ldr x0, [x28, #2592]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -208,7 +208,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3520]",
+        "ldr q3, [x28, #3536]",
         "ldr x0, [x28, #2592]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",

unittests/InstructionCountCI/VEX_map2.json

@@ -1603,7 +1603,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3008]",
+        "ldr q2, [x28, #3024]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3683,7 +3683,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3709,7 +3709,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3735,7 +3735,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4609,7 +4609,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4635,7 +4635,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4661,7 +4661,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4687,7 +4687,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4713,7 +4713,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4738,7 +4738,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4763,7 +4763,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4788,7 +4788,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"

unittests/InstructionCountCI/VEX_map3.json

@@ -5372,7 +5372,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -5385,7 +5385,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",

unittests/InstructionCountCI/x87.json

@@ -2467,7 +2467,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2481,7 +2481,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2547,7 +2547,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2567,7 +2567,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3344]",
+        "ldr q2, [x28, #3360]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2587,7 +2587,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2607,7 +2607,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2627,7 +2627,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2647,7 +2647,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2741,7 +2741,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3328]",
+        "ldr q3, [x28, #3344]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
@@ -2899,7 +2899,7 @@
         "0xd9 11b 0xf9 /7"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q3, [x21, #1056]",

unittests/InstructionCountCI/x87_f64.json

@@ -2160,7 +2160,7 @@
       ]
     },
     "f2xm1": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 10,
       "Comment": [
         "0xd9 11b 0xf0 /6"
       ],
@@ -2168,10 +2168,9 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #2248]",
-        "ldr x3, [x28, #2256]",
+        "ldr x0, [x28, #3008]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -2462,7 +2461,7 @@
       ]
     },
     "fscale": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xd9 11b 0xfd /7"
       ],
@@ -2474,11 +2473,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2312]",
-        "ldr x3, [x28, #2320]",
+        "ldr x0, [x28, #3016]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",