Merge pull request #3192 from Sonicadvance1/optimize_small_push

OpcodeDispatcher: Optimizes < 32-bit register push

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -512,7 +512,7 @@ void OpDispatchBuilder::PUSHOp(OpcodeArgs) {
 void OpDispatchBuilder::PUSHREGOp(OpcodeArgs) {
   const uint8_t Size = GetSrcSize(Op);
 
-  OrderedNode *Src = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(GPRClass, Op, Op->Dest , Op->Flags, -1, true, false, MemoryAccessType::ACCESS_DEFAULT, true);
 
   auto OldSP = LoadGPRRegister(X86State::REG_RSP);
   const uint8_t GPRSize = CTX->GetGPRSize();

unittests/InstructionCountCI/Primary.json

@@ -2553,12 +2553,11 @@
       ]
     },
     "push ax": {
-      "ExpectedInstructionCount": 2,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 1,
+      "Optimal": "Yes",
       "Comment": "0x50",
       "ExpectedArm64ASM": [
-        "uxth w20, w4",
-        "strh w20, [x8, #-2]!"
+        "strh w4, [x8, #-2]!"
       ]
     },
     "push rax": {

unittests/InstructionCountCI/PrimaryGroup.json

@@ -4050,12 +4050,11 @@
       ]
     },
     "push ax": {
-      "ExpectedInstructionCount": 2,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 1,
+      "Optimal": "Yes",
       "Comment": "GROUP4 0xff /6",
       "ExpectedArm64ASM": [
-        "uxth w20, w4",
-        "strh w20, [x8, #-2]!"
+        "strh w4, [x8, #-2]!"
       ]
     },
     "push rax": {

unittests/InstructionCountCI/Primary_32Bit.json

@@ -342,6 +342,22 @@
         "str w20, [x28, #728]"
       ]
     },
+    "push ax": {
+      "ExpectedInstructionCount": 1,
+      "Optimal": "Yes",
+      "Comment": "0x50",
+      "ExpectedArm64ASM": [
+        "strh w4, [x8, #-2]!"
+      ]
+    },
+    "push eax": {
+      "ExpectedInstructionCount": 1,
+      "Optimal": "Yes",
+      "Comment": "0x50",
+      "ExpectedArm64ASM": [
+        "str w4, [x8, #-4]!"
+      ]
+    },
     "dec eax": {
       "ExpectedInstructionCount": 10,
       "Optimal": "No",

unittests/InstructionCountCI/Test.json

@@ -1,27 +0,0 @@
-{
-  "Features": {
-    "Bitness": 64,
-    "EnabledHostFeatures": [],
-    "DisabledHostFeatures": [
-      "SVE128",
-      "SVE256"
-    ]
-  },
-  "Instructions": {
-    "push ax, bx": {
-      "ExpectedInstructionCount": 4,
-      "Optimal": "No",
-      "Comment": "0x50",
-      "x86Insts": [
-        "push ax",
-        "push bx"
-      ],
-      "ExpectedArm64ASM": [
-        "uxth w20, w4",
-        "strh w20, [x8, #-2]!",
-        "uxth w20, w7",
-        "strh w20, [x8, #-2]!"
-      ]
-    }
-  }
-}