Merge pull request #2305 from lioncash/mask

OpcodeDispatcher: Handle VMASKMOVDQU

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -5995,6 +5995,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b01, 0xF2), 1, &OpDispatchBuilder::VPSLLOp<4>},
     {OPD(1, 0b01, 0xF3), 1, &OpDispatchBuilder::VPSLLOp<8>},
     {OPD(1, 0b01, 0xF4), 1, &OpDispatchBuilder::VPMULLOp<4, false>},
+    {OPD(1, 0b01, 0xF7), 1, &OpDispatchBuilder::MASKMOVOp},
+
     {OPD(1, 0b01, 0xF8), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 1>},
     {OPD(1, 0b01, 0xF9), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 2>},
     {OPD(1, 0b01, 0xFA), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 4>},

External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp

@@ -248,7 +248,7 @@ void InitializeVEXTables() {
     {OPD(1, 0b01, 0xF4), 1, X86InstInfo{"VPMULUDQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0xF5), 1, X86InstInfo{"VPMADDWD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0xF6), 1, X86InstInfo{"VPSADBW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF7), 1, X86InstInfo{"VMASKMOVDQU", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b01, 0xF7), 1, X86InstInfo{"VMASKMOVDQU", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(1, 0b01, 0xF8), 1, X86InstInfo{"VPSUBB", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0xF9), 1, X86InstInfo{"VPSUBW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},

unittests/ASM/VEX/vmaskmovdqu.asm

@@ -0,0 +1,63 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "RAX": "0x4142434445464748",
+    "RBX": "0x5152535455565758",
+    "RCX": "0x41424344FFFFFFFF",
+    "RSP": "0x51525354FFFFFFFF",
+    "RSI": "0xFFFFFFFFFFFFFFFF",
+    "RDI": "0xFFFFFFFFFFFFFFFF"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovaps xmm0, [rdx + 16 * 0]
+vmovaps xmm1, [rdx + 16 * 1]
+vmovaps xmm2, [rdx + 16 * 2]
+vmovaps xmm3, [rdx + 16 * 3]
+
+lea rdi, [rdx + 16 * 4]
+vmaskmovdqu xmm0, xmm1
+
+lea rdi, [rdx + 16 * 5]
+vmaskmovdqu xmm0, xmm2
+
+lea rdi, [rdx + 16 * 6]
+vmaskmovdqu xmm0, xmm3
+
+mov rax, qword [rdx + 8 * 8]
+mov rbx, qword [rdx + 8 * 9]
+
+mov rcx, qword [rdx + 8 * 10]
+mov rsp, qword [rdx + 8 * 11]
+
+mov rsi, qword [rdx + 8 * 12]
+mov rdi, qword [rdx + 8 * 13]
+
+hlt
+
+align 32
+.data:
+dq 0x4142434445464748
+dq 0x5152535455565758
+
+dq 0x8080808080808080
+dq 0x8080808080808080
+
+dq 0x8080808000000000
+dq 0x8080808000000000
+
+dq 0x0000000000000000
+dq 0x0000000000000000
+
+dq -1
+dq -1
+
+dq -1
+dq -1
+
+dq -1
+dq -1