asm_tests: Fix quiet and signalling nan propagation

unittests/32Bit_ASM/CMakeLists.txt

@@ -38,7 +38,7 @@ foreach(ASM_SRC ${ASM_SOURCES})
 
   add_custom_command(OUTPUT ${OUTPUT_NAME}
     DEPENDS "${TMP_FILE}"
-    COMMAND "nasm" ARGS "${TMP_FILE}" "-o" "${OUTPUT_NAME}")
+    COMMAND "nasm" ARGS "-i" "${CMAKE_SOURCE_DIR}/unittests/32Bit_ASM/Includes/" "${TMP_FILE}" "-o" "${OUTPUT_NAME}")
 
   add_custom_command(OUTPUT ${OUTPUT_CONFIG_NAME}
     DEPENDS "${ASM_SRC}"

unittests/32Bit_ASM/Includes/nan_test_macros.inc

@@ -0,0 +1,130 @@
+; NaN Testing Macros for 32-bit Assembly Tests
+; Implements NaN triple testing system:
+; - Bit 2: 1 if value is NaN
+; - Bit 1: 1 if quiet NaN
+; - Bit 0: 1 if signaling NaN
+;
+; Triple values:
+; 0b000 (0): Not a NaN
+; 0b101 (5): Signaling NaN
+; 0b110 (6): Quiet NaN
+;
+; ASSUMPTION: All input pointers (edx) are valid and non-null
+
+; Macro: CHECK_NAN_TRIPLE_32
+; Checks 32-bit float NaN classification and returns triple in EAX
+; Input: 32-bit float value in xmm0
+; Output: NaN triple in EAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_32 0
+  push ecx
+  push esi
+  push edx
+  
+  xor eax, eax
+  ucomiss xmm0, xmm0
+  setp al
+  mov ecx, eax
+  shl ecx, 2
+  
+  ; Extract and check quiet bit (bit 22)
+  movd edx, xmm0
+  and edx, 0x00400000
+  mov esi, edx
+  shr esi, 22
+  and esi, eax
+  and esi, 1
+  shl esi, 1
+  add ecx, esi
+  
+  ; Check for signaling NaN (NaN but not quiet)
+  test edx, edx
+  sete dl
+  and dl, al
+  movzx eax, dl
+  or eax, ecx
+  
+  pop edx
+  pop esi
+  pop ecx
+%endmacro
+
+; Macro: CHECK_NAN_TRIPLE_64
+; Checks 64-bit double NaN classification and returns triple in EAX
+; Input: 64-bit double value should be pre-stored at [edx] by caller
+; Output: NaN triple in EAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_64 0
+  push ebx
+  push esi
+  sub esp, 12
+  
+  ; Load 64-bit double and use SSE for NaN comparison
+  movsd xmm0, qword [edx]
+  xor eax, eax
+  ucomisd xmm0, xmm0
+  setp al
+  
+  mov ecx, eax
+  movsd qword [esp], xmm0
+  mov edx, 524288
+  and edx, [esp + 4]
+  shl ecx, 2
+  
+  ; Extract quiet bit (bit 51)
+  mov ebx, edx
+  shr ebx, 19
+  and bl, al
+  movzx esi, bl
+  lea ecx, [ecx + 2*esi]
+  
+  ; Check for signaling NaN (NaN but not quiet)
+  test edx, edx
+  sete dl
+  and dl, al
+  movzx eax, dl
+  or eax, ecx
+  
+  add esp, 12
+  pop esi
+  pop ebx
+%endmacro
+
+; Macro: CHECK_NAN_TRIPLE_80
+; Checks 80-bit extended precision NaN classification and returns triple in EAX
+; Input: 80-bit extended precision value in memory at [eax] (10 bytes)
+; Output: NaN triple in EAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_80 0
+  push ebx
+  push esi
+  sub esp, 20
+  
+  ; Load the 80-bit value and store copy for bit manipulation
+  fld tword [eax]
+  fld st0
+  fstp tword [esp]
+  
+  ; Get bits 63:32 from stored significand
+  mov ecx, [esp + 4]
+  xor eax, eax
+  fucomip st0
+  setp al
+  mov edx, eax
+  shl edx, 2
+  
+  ; Extract quiet bit (bit 30 in high dword)
+  mov ebx, ecx
+  shr ebx, 30
+  and bl, al
+  movzx esi, bl
+  lea edx, [edx + 2*esi]
+  
+  ; Check for signaling NaN using bt instruction
+  bt ecx, 30
+  setae cl
+  and cl, al
+  movzx eax, cl
+  or eax, edx
+  
+  add esp, 20
+  pop esi
+  pop ebx
+%endmacro

unittests/32Bit_ASM/X87/x87_32bit_qnan_preservation.asm

@@ -0,0 +1,36 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 quiet NaN preservation in non-reduced precision mode (32-bit)
+; This test verifies that FLDT loads a quiet NaN and preserves its nature
+; We test that loading a quiet nan preserves it
+; that then storing it as 32bit, keeps it as a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea edx, [.data]
+fld tword [edx] ; load qnan 80bit
+fstp dword [edx + 16] ; store qnan as 32bit
+
+; Check the stored 32-bit value using NaN triple macro
+lea edx, [.data + 16]
+movss xmm0, [edx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+.data:
+  dq 0xc000000000000000  ; quiet NaN significand
+  dw 0x7fff              ; NaN exponent
+  dd 0                   ; space for 32-bit result

unittests/32Bit_ASM/X87/x87_32bit_snan_preservation.asm

@@ -0,0 +1,36 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in non-reduced precision mode (32-bit)
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 32bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN (converted from signaling)
+
+finit
+lea edx, [.data]
+fld tword [edx] ; load snan
+fstp dword [edx + 16] ; store snan as 32bit qnan
+
+; Check the stored 32-bit value using NaN triple macro
+lea edx, [.data + 16]
+movss xmm0, [edx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+.data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dd 0                   ; space for 32-bit result

unittests/32Bit_ASM/X87/x87_neg_snan_roundtrip.asm

@@ -0,0 +1,34 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling negative NaN round-trip preservation in non-reduced precision mode (32-bit)
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+lea edx, [.data]
+fld tword [edx] ; load snan 80bit
+fstp tword [edx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+lea eax, [.data + 16]
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+.data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0xffff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)

unittests/32Bit_ASM/X87/x87_qnan_preservation.asm

@@ -1,4 +1,3 @@
-BITS 32
 %ifdef CONFIG
 {
   "RegData": {
@@ -8,7 +7,7 @@ BITS 32
 }
 %endif
 
-%include "Includes/nan_test_macros.inc"
+%include "nan_test_macros.inc"
 
 mov esp, 0xe0000040
 

unittests/32Bit_ASM/X87/x87_snan_preservation.asm

@@ -0,0 +1,36 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in non-reduced precision mode (32-bit)
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 64bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+mov edx, .data
+fld tword [edx] ; load snan
+fstp qword [edx + 16] ; store snan as 64bit qnan
+
+; Check the stored 64-bit value using NaN triple macro
+mov edx, .data
+add edx, 16
+CHECK_NAN_TRIPLE_64
+
+hlt
+
+align 8
+.data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dq 0                   ; space for 64-bit result

unittests/32Bit_ASM/X87/x87_snan_roundtrip.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN round-trip preservation in non-reduced precision mode (32-bit)
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+mov edx, .data
+fld tword [edx] ; load nan 80bit
+fstp tword [edx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+mov eax, edx
+add eax, 16
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+.data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0x7fff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)

unittests/ASM/Includes/nan_test_macros.inc

@@ -0,0 +1,128 @@
+; NaN Testing Macros for Assembly Tests
+; Implements NaN triple testing system:
+; - Bit 2: 1 if value is NaN
+; - Bit 1: 1 if quiet NaN
+; - Bit 0: 1 if signaling NaN
+;
+; Triple values:
+; 0b000 (0): Not a NaN
+; 0b101 (5): Signaling NaN
+; 0b110 (6): Quiet NaN
+;
+; ASSUMPTION: All input pointers (rdx) are valid and non-null
+
+; Macro: CHECK_NAN_TRIPLE_32
+; Checks 32-bit float NaN classification and returns triple in EAX
+; Input: 32-bit float value in xmm0
+; Output: NaN triple in EAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_32 0
+  push rcx
+  push rsi
+  push rdx
+  
+  xor eax, eax
+  ucomiss xmm0, xmm0
+  setp al
+  lea rcx, [4*rax]
+  
+  ; Extract and check quiet bit (bit 22)
+  movd edx, xmm0
+  and edx, 0x00400000
+  mov esi, edx
+  shr esi, 22
+  and sil, al
+  movzx esi, sil
+  lea rcx, [rcx + 2*rsi]
+  
+  ; Check for signaling NaN (NaN but not quiet)
+  test edx, edx
+  sete dl
+  and dl, al
+  movzx eax, dl
+  or eax, ecx
+  
+  pop rdx
+  pop rsi
+  pop rcx
+%endmacro
+
+; Macro: CHECK_NAN_TRIPLE_64
+; Checks 64-bit double NaN classification and returns triple in RAX
+; Input: 64-bit double value in xmm0
+; Output: NaN triple in RAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_64 0
+  push rcx
+  push rsi
+  push rdx
+  
+  xor eax, eax
+  ucomisd xmm0, xmm0
+  setp al
+  lea rcx, [4*rax]
+  
+  ; Extract and check quiet bit (bit 51)
+  movq rdx, xmm0
+  mov rsi, 0x0008000000000000
+  and rsi, rdx
+  mov rdx, rsi
+  shr rdx, 51
+  and dl, al
+  movzx rdx, dl
+  lea rcx, [rcx + 2*rdx]
+  
+  ; Check for signaling NaN (NaN but not quiet)
+  test rsi, rsi
+  sete dl
+  and dl, al
+  movzx eax, dl
+  or eax, ecx
+  
+  pop rdx
+  pop rsi
+  pop rcx
+%endmacro
+
+; Macro: CHECK_NAN_TRIPLE_80
+; Checks 80-bit extended precision NaN classification and returns triple in RAX
+; Input: 80-bit extended precision value in memory at [rax] (10 bytes)
+; Output: NaN triple in RAX (bits 2:0)
+%macro CHECK_NAN_TRIPLE_80 0
+  push rcx
+  push rdx
+  push rsi
+  
+  ; Load the 80-bit value twice for comparison
+  fld tword [rax]
+  fld tword [rax]
+  
+  ; Store one copy to memory for bit manipulation
+  sub rsp, 16
+  fstp tword [rsp]
+  
+  ; Use fucomip for NaN detection
+  xor eax, eax
+  fucomip st0, st1
+  setp al
+  lea rdx, [4*rax]
+  
+  ; Extract and check quiet bit (bit 62)
+  mov rcx, 0x4000000000000000
+  and rcx, [rsp]
+  mov rsi, rcx
+  shr rsi, 62
+  and sil, al
+  movzx rsi, sil
+  lea rdx, [rdx + 2*rsi]
+  
+  ; Check for signaling NaN (NaN but not quiet)
+  test rcx, rcx
+  sete cl
+  and cl, al
+  movzx eax, cl
+  or eax, edx
+  
+  add rsp, 16
+  pop rsi
+  pop rdx
+  pop rcx
+%endmacro

unittests/ASM/X87/x87_32bit_qnan_preservation.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 quiet NaN preservation in non-reduced precision mode
+; This test verifies that FLDT loads a quiet NaN and preserves its nature
+; We test that loading a quiet nan preserves it
+; that then storing it as 32bit, keeps it as a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load qnan 80bit
+fstp dword [rdx + 16] ; store qnan as 32bit
+
+; Check the stored 32-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movss xmm0, [rdx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+data:
+  dq 0xc000000000000000  ; quiet NaN significand
+  dw 0x7fff              ; NaN exponent
+  dd 0                   ; space for 32-bit result

unittests/ASM/X87/x87_32bit_snan_preservation.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in non-reduced precision mode
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 32bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN (converted from signaling)
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan
+fstp dword [rdx + 16] ; store snan as 32bit qnan
+
+; Check the stored 32-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movss xmm0, [rdx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dd 0                   ; space for 32-bit result

unittests/ASM/X87/x87_neg_snan_roundtrip.asm

@@ -0,0 +1,33 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 signaling negative NaN round-trip preservation in non-reduced precision mode
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan 80bit
+fstp tword [rdx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+lea rax, [rel data + 16]
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0xffff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)

unittests/ASM/X87/x87_qnan_preservation.asm

@@ -0,0 +1,33 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 quiet NaN preservation in non-reduced precision mode
+; This test verifies that quiet NaNs remain quiet during conversion
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load qnan 80bit
+fstp qword [rdx + 16] ; store qnan as 64bit
+
+; Check the stored 64-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movsd xmm0, [rdx]    ; Load 64-bit double into xmm0
+CHECK_NAN_TRIPLE_64
+
+hlt
+
+align 8
+data:
+  dq 0xc000000000000000  ; quiet NaN significand
+  dw 0x7fff              ; NaN exponent
+  dq 0                   ; space for 64-bit result

unittests/ASM/X87/x87_snan_preservation.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in non-reduced precision mode
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 64bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan
+fstp qword [rdx + 16] ; store snan as 64bit qnan
+
+; Check the stored 64-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movsd xmm0, [rdx]    ; Load 64-bit double into xmm0
+CHECK_NAN_TRIPLE_64
+
+hlt
+
+align 8
+data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dq 0                   ; space for 64-bit result

unittests/ASM/X87/x87_snan_roundtrip.asm

@@ -0,0 +1,33 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov rsp, 0xe0000040
+
+; Test x87 signaling NaN round-trip preservation in non-reduced precision mode
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load nan 80bit
+fstp tword [rdx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+lea rax, [rel data + 16]
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0x7fff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)

unittests/ASM/X87_F64/x87_32bit_qnan_preservation_F64.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Env": { "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 quiet NaN preservation in reduced precision mode
+; This test verifies that quiet NaNs remain quiet during conversion
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load qnan 80bit
+fstp dword [rdx + 16] ; store qnan as 32bit
+
+; Check the stored 32-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movss xmm0, [rdx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+data:
+  dq 0xc000000000000000  ; quiet NaN significand
+  dw 0x7fff              ; NaN exponent
+  dd 0                   ; space for 32-bit result
+

unittests/ASM/X87_F64/x87_32bit_snan_preservation_F64.asm

@@ -0,0 +1,37 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1", "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in reduced precision mode
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 32bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN (converted from signaling)
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan
+fstp dword [rdx + 16] ; store snan as 32bit qnan
+
+; Check the stored 32-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movss xmm0, [rdx]    ; Load 32-bit float into xmm0
+CHECK_NAN_TRIPLE_32
+
+hlt
+
+align 8
+data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dd 0                   ; space for 32-bit result
+

unittests/ASM/X87_F64/x87_neg_snan_roundtrip_F64.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1", "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling negative NaN round-trip preservation in reduced precision mode
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan 80bit
+fstp tword [rdx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+lea rax, [rel data + 16]
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0xffff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)
+

unittests/ASM/X87_F64/x87_qnan_preservation_F64.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Env": { "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 quiet NaN preservation in reduced precision mode
+; This test verifies that quiet NaNs remain quiet during conversion
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load qnan 80bit
+fstp qword [rdx + 16] ; store qnan as 64bit
+
+; Check the stored 64-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movsd xmm0, [rdx]    ; Load 64-bit double into xmm0
+CHECK_NAN_TRIPLE_64
+
+hlt
+
+align 8
+data:
+  dq 0xc000000000000000  ; quiet NaN significand
+  dw 0x7fff              ; NaN exponent
+  dq 0                   ; space for 64-bit result
+

unittests/ASM/X87_F64/x87_snan_preservation_F64.asm

@@ -0,0 +1,37 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "6"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1", "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN non-preservation in reduced precision mode
+; This test verifies that FLDT loads a signaling NaN and DOES NOT preserve its signaling nature
+; We test that loading a signaling nan preserves it but
+; that then storing it as 64bit, transforms it to a quiet nan.
+; Returns NaN triple: 6 (0b110) for quiet NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load snan
+fstp qword [rdx + 16] ; store snan as 64bit qnan
+
+; Check the stored 64-bit value using NaN triple macro
+lea rdx, [rel data + 16]
+movsd xmm0, [rdx]    ; Load 64-bit double into xmm0
+CHECK_NAN_TRIPLE_64
+
+hlt
+
+align 8
+data:
+  dq 0xa000000000000000  ; signaling NaN significand
+  dw 0x7fff              ; signaling NaN exponent  
+  dq 0                   ; space for 64-bit result
+

unittests/ASM/X87_F64/x87_snan_roundtrip_F64.asm

@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "5"
+  },
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1", "FEX_X87STRICTREDUCEDPRECISION" : "1" }
+}
+%endif
+
+%include "nan_test_macros.inc"
+
+mov esp, 0xe0000040
+
+; Test x87 signaling NaN round-trip preservation in reduced precision mode
+; This test verifies that FLDT -> FSTPT preserves signaling nan across round-trip
+; Returns NaN triple: 5 (0b101) for signaling NaN
+
+finit
+lea rdx, [rel data]
+fld tword [rdx] ; load nan 80bit
+fstp tword [rdx + 16] ; store nan as 80bit
+
+; Check the stored 80-bit value using NaN triple macro
+lea rax, [rel data + 16]
+CHECK_NAN_TRIPLE_80
+
+hlt
+
+align 16
+data:
+  dq 0xa000000000000000  ; signaling nan significand  
+  dw 0x7fff              ; signaling nan exponent
+  dw 0, 0, 0             ; padding to 16 bytes
+  dq 0, 0                ; space for 80-bit result (16 bytes)
+