steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 14:00:16 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity

InstCountCI: Update

Browse Source 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2023-11-14 08:40:41 -04:00
1 parent 56841f0e50
commit bec8e27b4f
10 files changed
+1394 -2166
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

unittests/InstructionCountCI/Atomics.json
+54 -54
View File
@@ -22,12 +22,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -44,12 +44,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -121,7 +121,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -151,7 +151,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -197,7 +197,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -228,7 +228,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -301,12 +301,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -324,12 +324,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -442,12 +442,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -465,12 +465,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -512,10 +512,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -532,10 +532,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -551,10 +551,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -571,10 +571,10 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w20, #16, #1",
"ubfx x23, x20, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -639,10 +639,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -814,7 +814,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -842,7 +842,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -869,7 +869,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -897,7 +897,7 @@
"csel x20, x20, x25, eq",
"orr w20, w24, w20, lsl #29",
"bic w21, w23, w22",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
@@ -981,7 +981,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1037,7 +1037,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1066,7 +1066,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1094,7 +1094,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1123,7 +1123,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1236,7 +1236,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1427,10 +1427,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1448,10 +1448,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1468,10 +1468,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1489,10 +1489,10 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w20, #16, #1",
"ubfx x23, x20, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1574,10 +1574,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1749,7 +1749,7 @@
"cmn wzr, w21, lsl #24",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
@@ -1801,10 +1801,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1823,10 +1823,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1881,7 +1881,7 @@
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
@@ -1934,7 +1934,7 @@
"cmn wzr, w21, lsl #24",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
@@ -1953,7 +1953,7 @@
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
unittests/InstructionCountCI/FlagM/Primary.json
+20 -42
View File
@@ -2000,105 +2000,83 @@
]
},
"imul ax, bx, 257": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x20, w20",
"sxth x20, w7",
"mov w21, #0x101",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx, 257": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"mov w20, w7",
"sxtw x20, w20",
"sxtw x20, w7",
"mov w21, #0x101",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx, 257": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x69",
"ExpectedArm64ASM": [
"mov w20, #0x101",
"mul x4, x7, x20",
"smulh x20, x7, x20",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul ax, bx, 3": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x20, w20",
"sxth x20, w7",
"mov w21, #0x3",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx, 3": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"mov w20, w7",
"sxtw x20, w20",
"sxtw x20, w7",
"mov w21, #0x3",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx, 3": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"mov w20, #0x3",
"mul x4, x7, x20",
"smulh x20, x7, x20",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"test al, bl": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+417 -843
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/Secondary.json
+104 -186
View File
@@ -680,7 +680,7 @@
]
},
"shld ax, bx, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -690,16 +690,14 @@
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"ubfx w22, w21, #15, #1",
"rmif x22, #63, #nzCv",
"rmif x21, #14, #nzCv",
"strb w20, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #15, #1",
"rmif x20, #0, #nzcV"
"rmif x20, #15, #nzcV"
]
},
"shld ax, bx, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -709,13 +707,12 @@
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"ubfx w21, w21, #1, #1",
"rmif x21, #63, #nzCv",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -724,13 +721,12 @@
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"ubfx w21, w21, #0, #1",
"rmif x21, #63, #nzCv",
"strb w20, [x28, #706]"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -740,119 +736,108 @@
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"ubfx w21, w21, #1, #1",
"rmif x21, #63, #nzCv",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
]
},
"shld eax, ebx, 1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #31",
"tst w4, w4",
"lsr w20, w21, #31",
"rmif x20, #63, #nzCv",
"rmif x21, #30, #nzCv",
"strb w4, [x28, #706]",
"eor w20, w4, w21",
"lsr w20, w20, #31",
"rmif x20, #0, #nzcV"
"rmif x20, #31, #nzcV"
]
},
"shld eax, ebx, 15": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #17",
"tst w4, w4",
"ubfx w20, w21, #17, #1",
"rmif x20, #63, #nzCv",
"rmif x21, #16, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld eax, ebx, 16": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #16",
"tst w4, w4",
"ubfx w20, w21, #16, #1",
"rmif x20, #63, #nzCv",
"rmif x21, #15, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld eax, ebx, 31": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #1",
"tst w4, w4",
"ubfx w20, w21, #1, #1",
"rmif x20, #63, #nzCv",
"rmif x21, #0, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld rax, rbx, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #63",
"tst x4, x4",
"lsr x21, x20, #63",
"rmif x21, #63, #nzCv",
"rmif x20, #62, #nzCv",
"strb w4, [x28, #706]",
"eor x20, x4, x20",
"lsr x20, x20, #63",
"rmif x20, #0, #nzcV"
"rmif x20, #63, #nzcV"
]
},
"shld rax, rbx, 15": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #49",
"tst x4, x4",
"ubfx x20, x20, #49, #1",
"rmif x20, #63, #nzCv",
"rmif x20, #48, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld rax, rbx, 32": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #32",
"tst x4, x4",
"ubfx x20, x20, #32, #1",
"rmif x20, #63, #nzCv",
"rmif x20, #31, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld rax, rbx, 63": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #1",
"tst x4, x4",
"ubfx x20, x20, #1, #1",
"rmif x20, #63, #nzCv",
"rmif x20, #0, #nzCv",
"strb w4, [x28, #706]"
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 34,
"ExpectedInstructionCount": 24,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -860,39 +845,29 @@
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x10",
"sub x24, x23, x22",
"lsl x25, x21, x22",
"lsr w20, w20, w24",
"orr x20, x25, x20",
"mrs x24, nzcv",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"uxth x20, w20",
"msr nzcv, x24",
"mrs x24, nzcv",
"msr nzcv, x23",
"cbz x22, #+0x24",
"cmn wzr, w20, lsl #16",
"sub w23, w23, w22",
"lsr w23, w21, w23",
"ubfx w23, w23, #0, #1",
"rmif x23, #63, #nzCv",
"ldrb w23, [x28, #706]",
"mrs x25, nzcv",
"cmp x22, #0x0 (0)",
"csel x23, x23, x20, eq",
"strb w23, [x28, #706]",
"mov w23, #0x10",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"eor w20, w21, w20",
"ubfx w20, w20, #15, #1",
"msr nzcv, x25",
"rmif x20, #0, #nzcV",
"mrs x20, nzcv",
"cmp x22, #0x0 (0)",
"csel w20, w24, w20, eq",
"msr nzcv, x20"
"rmif x20, #15, #nzcV"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 34,
"ExpectedInstructionCount": 24,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -900,72 +875,53 @@
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x24, x23, x22",
"lsl x25, x21, x22",
"lsr w20, w20, w24",
"orr x20, x25, x20",
"mrs x24, nzcv",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"mov w4, w20",
"mov w20, w20",
"msr nzcv, x24",
"mrs x24, nzcv",
"msr nzcv, x23",
"cbz x22, #+0x24",
"tst w20, w20",
"sub w23, w23, w22",
"lsr w23, w21, w23",
"ubfx w23, w23, #0, #1",
"rmif x23, #63, #nzCv",
"ldrb w23, [x28, #706]",
"mrs x25, nzcv",
"cmp x22, #0x0 (0)",
"csel x23, x23, x20, eq",
"strb w23, [x28, #706]",
"mov w23, #0x20",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"eor w20, w21, w20",
"lsr w20, w20, #31",
"msr nzcv, x25",
"rmif x20, #0, #nzcV",
"mrs x20, nzcv",
"cmp x22, #0x0 (0)",
"csel w20, w24, w20, eq",
"msr nzcv, x20"
"rmif x20, #31, #nzcV"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 22,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x23, x22, x21",
"lsl x24, x20, x21",
"lsr x23, x7, x23",
"orr x23, x24, x23",
"mrs x24, nzcv",
"cmp x21, #0x0 (0)",
"csel x4, x20, x23, eq",
"msr nzcv, x24",
"mrs x23, nzcv",
"tst x4, x4",
"sub x22, x22, x21",
"lsr x22, x20, x22",
"ubfx x22, x22, #0, #1",
"rmif x22, #63, #nzCv",
"ldrb w22, [x28, #706]",
"mrs x24, nzcv",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x22, x22, x4, eq",
"csel x22, x20, x22, eq",
"mov x4, x22",
"msr nzcv, x23",
"cbz x21, #+0x24",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"strb w22, [x28, #706]",
"eor x20, x20, x4",
"lsr x20, x20, #63",
"msr nzcv, x24",
"rmif x20, #0, #nzcV",
"mrs x20, nzcv",
"cmp x21, #0x0 (0)",
"csel w20, w23, w20, eq",
"msr nzcv, x20"
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
]
},
"bts ax, bx": {
@@ -1109,56 +1065,42 @@
]
},
"imul ax, bx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"sxth x20, w20",
"sxth x21, w21",
"sxth x20, w4",
"sxth x21, w7",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w7",
"sxtw x20, w20",
"sxtw x21, w21",
"sxtw x20, w4",
"sxtw x21, w7",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"mov x20, x4",
"mul x4, x20, x7",
"smulh x20, x20, x7",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"smulh x20, x4, x7",
"mul x4, x4, x7",
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"cmpxchg al, bl": {
@@ -1621,7 +1563,7 @@
]
},
"bsf ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth w20, w4",
@@ -1631,17 +1573,13 @@
"rbit w0, w0",
"clz w22, w0",
"csinv w22, w22, wzr, ne",
"cmp x21, #0x0 (0)",
"csel w20, w20, w22, eq",
"bfxil x4, x20, #0, #16",
"cmp x21, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsf eax, ebx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1650,32 +1588,24 @@
"rbit w0, w0",
"clz w21, w0",
"csinv w21, w21, wzr, ne",
"cmp x20, #0x0 (0)",
"csel x4, x4, x21, eq",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsf rax, rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x0, x7",
"cmp x7, #0x0 (0)",
"clz x20, x0",
"csinv x20, x20, xzr, ne",
"cmp x7, #0x0 (0)",
"csel x4, x4, x20, eq",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"bsr ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth w20, w4",
@@ -1685,44 +1615,32 @@
"orr w22, w22, #0x8000",
"clz w22, w22",
"sub x22, x0, x22",
"cmp x21, #0x0 (0)",
"csel w20, w20, w22, eq",
"bfxil x4, x20, #0, #16",
"cmp x21, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsr eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x0, #0x1f",
"clz w21, w20",
"sub x21, x0, x21",
"cmp x20, #0x0 (0)",
"csel x4, x4, x21, eq",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsr rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov x0, #0x3f",
"clz x20, x7",
"sub x20, x0, x20",
"cmp x7, #0x0 (0)",
"csel x4, x4, x20, eq",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"xadd al, bl": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+9 -12
View File
@@ -114,7 +114,7 @@
]
},
"lzcnt ax, bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -125,13 +125,12 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx w20, w20, #15, #1",
"orr w20, w21, w20, lsl #30",
"msr nzcv, x20"
"msr nzcv, x21",
"rmif x20, #13, #nZcv"
]
},
"lzcnt eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -139,22 +138,20 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"lsr w20, w20, #31",
"orr w20, w21, w20, lsl #30",
"msr nzcv, x20"
"msr nzcv, x21",
"rmif x20, #29, #nZcv"
]
},
"lzcnt rax, rbx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"lsr x21, x7, #63",
"orr w20, w20, w21, lsl #30",
"msr nzcv, x20"
"msr nzcv, x20",
"rmif x7, #61, #nZcv"
]
}
}
unittests/InstructionCountCI/Primary.json
+115 -137
View File
@@ -23,12 +23,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -46,12 +46,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -96,12 +96,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -122,12 +122,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -173,10 +173,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -192,10 +192,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -234,10 +234,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -255,10 +255,10 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w20, #16, #1",
"ubfx x23, x20, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -492,7 +492,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -523,7 +523,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -586,7 +586,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -620,7 +620,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -683,7 +683,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -711,7 +711,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -768,7 +768,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -797,7 +797,7 @@
"csel x20, x20, x25, eq",
"orr w20, w24, w20, lsl #29",
"bic w21, w23, w22",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
@@ -858,7 +858,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -889,7 +889,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -964,7 +964,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -998,7 +998,7 @@
"eor w20, w23, w20",
"eor w22, w22, w23",
"and w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1073,7 +1073,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1101,7 +1101,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w22, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1170,7 +1170,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1199,7 +1199,7 @@
"csel x21, x25, x24, eq",
"orr w21, w23, w21, lsl #29",
"bic w20, w20, w22",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1425,12 +1425,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1448,12 +1448,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1504,12 +1504,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1530,12 +1530,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1587,10 +1587,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1606,10 +1606,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1654,10 +1654,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1675,10 +1675,10 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w20, #16, #1",
"ubfx x23, x20, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1853,12 +1853,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1915,12 +1915,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1970,12 +1970,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1995,12 +1995,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2051,10 +2051,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2069,10 +2069,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #16, #1",
"ubfx x23, x21, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2115,10 +2115,10 @@
"strb w21, [x28, #706]",
"cmn wzr, w21, lsl #24",
"mrs x22, nzcv",
"ubfx w23, w21, #8, #1",
"ubfx x23, x21, #8, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2135,10 +2135,10 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w20, #16, #1",
"ubfx x23, x20, #16, #1",
"orr w22, w22, w23, lsl #29",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2230,54 +2230,43 @@
]
},
"imul ax, bx, 257": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x20, w20",
"sxth x20, w7",
"mov w21, #0x101",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx, 257": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"mov w20, w7",
"sxtw x20, w20",
"sxtw x20, w7",
"mov w21, #0x101",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx, 257": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x69",
"ExpectedArm64ASM": [
"mov w20, #0x101",
"mul x4, x7, x20",
"smulh x20, x7, x20",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"push word -1": {
@@ -2305,54 +2294,43 @@
]
},
"imul ax, bx, 3": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x20, w20",
"sxth x20, w7",
"mov w21, #0x3",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx, 3": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"mov w20, w7",
"sxtw x20, w20",
"sxtw x20, w7",
"mov w21, #0x3",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx, 3": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"mov w20, #0x3",
"mul x4, x7, x20",
"smulh x20, x7, x20",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"test al, bl": {
@@ -3021,15 +2999,15 @@
"add x8, x8, #0x8 (8)",
"mov w21, #0x202",
"orr x20, x20, x21",
"ubfx w21, w20, #0, #1",
"ubfx x21, x20, #0, #1",
"lsl x21, x21, #29",
"ubfx w22, w20, #2, #1",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"strb w20, [x28, #708]",
"ubfx w22, w20, #6, #1",
"ubfx x22, x20, #6, #1",
"orr w21, w21, w22, lsl #30",
"ubfx w22, w20, #7, #1",
"ubfx x22, x20, #7, #1",
"orr w21, w21, w22, lsl #31",
"ubfx w22, w20, #8, #1",
"strb w22, [x28, #712]",
@@ -3037,7 +3015,7 @@
"strb w22, [x28, #713]",
"ubfx w22, w20, #10, #1",
"strb w22, [x28, #714]",
"ubfx w22, w20, #11, #1",
"ubfx x22, x20, #11, #1",
"orr w21, w21, w22, lsl #28",
"ubfx w22, w20, #12, #1",
"strb w22, [x28, #716]",
@@ -3066,7 +3044,7 @@
"mov w21, #0x28",
"bic x20, x20, x21",
"orr x20, x20, #0x2",
"ubfx w21, w20, #0, #1",
"ubfx x21, x20, #0, #1",
"mrs x22, nzcv",
"mov w0, w22",
"bfi w0, w21, #29, #1",
@@ -3075,9 +3053,9 @@
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"strb w20, [x28, #708]",
"ubfx w22, w20, #6, #1",
"ubfx x22, x20, #6, #1",
"bfi w21, w22, #30, #1",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"mov w0, w21",
"bfi w0, w20, #31, #1",
"mov w20, w0",
@@ -3379,12 +3357,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -3408,12 +3386,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -3480,12 +3458,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #24",
"mrs x24, nzcv",
"ubfx w25, w23, #8, #1",
"ubfx x25, x23, #8, #1",
"orr w24, w24, w25, lsl #29",
"eor w21, w22, w21",
"eor w22, w23, w22",
"and w21, w22, w21",
"ubfx w21, w21, #7, #1",
"ubfx x21, x21, #7, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -3511,12 +3489,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #16",
"mrs x24, nzcv",
"ubfx w25, w23, #16, #1",
"ubfx x25, x23, #16, #1",
"orr w24, w24, w25, lsl #29",
"eor w21, w22, w21",
"eor w22, w23, w22",
"and w21, w22, w21",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -3592,12 +3570,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #24",
"mrs x24, nzcv",
"ubfx w25, w23, #8, #1",
"ubfx x25, x23, #8, #1",
"orr w24, w24, w25, lsl #29",
"eor w21, w22, w21",
"eor w22, w23, w22",
"and w21, w22, w21",
"ubfx w21, w21, #7, #1",
"ubfx x21, x21, #7, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -3623,12 +3601,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #16",
"mrs x24, nzcv",
"ubfx w25, w23, #16, #1",
"ubfx x25, x23, #16, #1",
"orr w24, w24, w25, lsl #29",
"eor w21, w22, w21",
"eor w22, w23, w22",
"and w21, w22, w21",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -4024,12 +4002,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w21, w20, w21",
"eor w20, w22, w20",
"and w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -4050,12 +4028,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w21, w20, w21",
"eor w20, w22, w20",
"and w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -4115,12 +4093,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #24",
"mrs x24, nzcv",
"ubfx w25, w23, #8, #1",
"ubfx x25, x23, #8, #1",
"orr w24, w24, w25, lsl #29",
"eor w22, w21, w22",
"eor w21, w23, w21",
"and w21, w21, w22",
"ubfx w21, w21, #7, #1",
"ubfx x21, x21, #7, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -4145,12 +4123,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #16",
"mrs x24, nzcv",
"ubfx w25, w23, #16, #1",
"ubfx x25, x23, #16, #1",
"orr w24, w24, w25, lsl #29",
"eor w22, w21, w22",
"eor w21, w23, w21",
"and w21, w21, w22",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -4222,12 +4200,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #24",
"mrs x24, nzcv",
"ubfx w25, w23, #8, #1",
"ubfx x25, x23, #8, #1",
"orr w24, w24, w25, lsl #29",
"eor w22, w21, w22",
"eor w21, w23, w21",
"and w21, w21, w22",
"ubfx w21, w21, #7, #1",
"ubfx x21, x21, #7, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
@@ -4252,12 +4230,12 @@
"strb w23, [x28, #706]",
"cmn wzr, w23, lsl #16",
"mrs x24, nzcv",
"ubfx w25, w23, #16, #1",
"ubfx x25, x23, #16, #1",
"orr w24, w24, w25, lsl #29",
"eor w22, w21, w22",
"eor w21, w23, w21",
"and w21, w21, w22",
"ubfx w21, w21, #15, #1",
"ubfx x21, x21, #15, #1",
"orr w21, w24, w21, lsl #28",
"msr nzcv, x21",
"sub x5, x5, #0x1 (1)",
unittests/InstructionCountCI/PrimaryGroup.json
+555 -723
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+2 -2
View File
@@ -301,7 +301,7 @@
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
@@ -335,7 +335,7 @@
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"msr nzcv, x20"
unittests/InstructionCountCI/Secondary.json
+113 -162
View File
@@ -1428,11 +1428,11 @@
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w23, w21, #15, #1",
"ubfx x23, x21, #15, #1",
"orr w22, w22, w23, lsl #29",
"strb w20, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
@@ -1449,7 +1449,7 @@
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w21, w21, #1, #1",
"ubfx x21, x21, #1, #1",
"orr w21, w22, w21, lsl #29",
"strb w20, [x28, #706]",
"msr nzcv, x21"
@@ -1466,7 +1466,7 @@
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w21, w21, #0, #1",
"ubfx x21, x21, #0, #1",
"orr w21, w22, w21, lsl #29",
"strb w20, [x28, #706]",
"msr nzcv, x21"
@@ -1484,7 +1484,7 @@
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"mrs x22, nzcv",
"ubfx w21, w21, #1, #1",
"ubfx x21, x21, #1, #1",
"orr w21, w22, w21, lsl #29",
"strb w20, [x28, #706]",
"msr nzcv, x21"
@@ -1506,11 +1506,11 @@
"extr w4, w21, w20, #31",
"tst w4, w4",
"mrs x20, nzcv",
"lsr w22, w21, #31",
"ubfx x22, x21, #31, #1",
"orr w20, w20, w22, lsl #29",
"strb w4, [x28, #706]",
"eor w21, w4, w21",
"lsr w21, w21, #31",
"ubfx x21, x21, #31, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
@@ -1524,7 +1524,7 @@
"extr w4, w21, w20, #17",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx w21, w21, #17, #1",
"ubfx x21, x21, #17, #1",
"orr w20, w20, w21, lsl #29",
"strb w4, [x28, #706]",
"msr nzcv, x20"
@@ -1539,7 +1539,7 @@
"extr w4, w21, w20, #16",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx w21, w21, #16, #1",
"ubfx x21, x21, #16, #1",
"orr w20, w20, w21, lsl #29",
"strb w4, [x28, #706]",
"msr nzcv, x20"
@@ -1554,7 +1554,7 @@
"extr w4, w21, w20, #1",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx w21, w21, #1, #1",
"ubfx x21, x21, #1, #1",
"orr w20, w20, w21, lsl #29",
"strb w4, [x28, #706]",
"msr nzcv, x20"
@@ -1625,7 +1625,7 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 32,
"ExpectedInstructionCount": 28,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1633,37 +1633,33 @@
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x10",
"sub x24, x23, x22",
"lsl x25, x21, x22",
"lsr w20, w20, w24",
"orr x20, x25, x20",
"mrs x24, nzcv",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"uxth x20, w20",
"msr nzcv, x24",
"mrs x24, nzcv",
"msr nzcv, x23",
"cbz x22, #+0x34",
"cmn wzr, w20, lsl #16",
"mrs x25, nzcv",
"sub w23, w23, w22",
"lsr w23, w21, w23",
"ubfx w23, w23, #0, #1",
"orr w23, w25, w23, lsl #29",
"ldrb w25, [x28, #706]",
"cmp x22, #0x0 (0)",
"csel x25, x25, x20, eq",
"strb w25, [x28, #706]",
"mrs x23, nzcv",
"mov w24, #0x10",
"sub w22, w24, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"orr w22, w23, w22, lsl #29",
"strb w20, [x28, #706]",
"eor w20, w21, w20",
"ubfx w20, w20, #15, #1",
"orr w20, w23, w20, lsl #28",
"cmp x22, #0x0 (0)",
"csel w20, w24, w20, eq",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 32,
"ExpectedInstructionCount": 28,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1671,67 +1667,60 @@
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x24, x23, x22",
"lsl x25, x21, x22",
"lsr w20, w20, w24",
"orr x20, x25, x20",
"mrs x24, nzcv",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"mov w4, w20",
"mov w20, w20",
"msr nzcv, x24",
"mrs x24, nzcv",
"msr nzcv, x23",
"cbz x22, #+0x34",
"tst w20, w20",
"mrs x25, nzcv",
"sub w23, w23, w22",
"lsr w23, w21, w23",
"ubfx w23, w23, #0, #1",
"orr w23, w25, w23, lsl #29",
"ldrb w25, [x28, #706]",
"cmp x22, #0x0 (0)",
"csel x25, x25, x20, eq",
"strb w25, [x28, #706]",
"mrs x23, nzcv",
"mov w24, #0x20",
"sub w22, w24, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"orr w22, w23, w22, lsl #29",
"strb w20, [x28, #706]",
"eor w20, w21, w20",
"lsr w20, w20, #31",
"orr w20, w23, w20, lsl #28",
"cmp x22, #0x0 (0)",
"csel w20, w24, w20, eq",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 26,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x23, x22, x21",
"lsl x24, x20, x21",
"lsr x23, x7, x23",
"orr x23, x24, x23",
"mrs x24, nzcv",
"cmp x21, #0x0 (0)",
"csel x4, x20, x23, eq",
"msr nzcv, x24",
"mrs x23, nzcv",
"tst x4, x4",
"mrs x24, nzcv",
"sub x22, x22, x21",
"lsr x22, x20, x22",
"ubfx x22, x22, #0, #1",
"orr w22, w24, w22, lsl #29",
"ldrb w24, [x28, #706]",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x24, x24, x4, eq",
"strb w24, [x28, #706]",
"eor x20, x20, x4",
"csel x22, x20, x22, eq",
"mov x4, x22",
"msr nzcv, x23",
"cbz x21, #+0x34",
"tst x22, x22",
"mrs x23, nzcv",
"mov w24, #0x40",
"sub x21, x24, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"orr w21, w23, w21, lsl #29",
"strb w22, [x28, #706]",
"eor x20, x20, x22",
"lsr x20, x20, #63",
"orr w20, w22, w20, lsl #28",
"cmp x21, #0x0 (0)",
"csel w20, w23, w20, eq",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
@@ -1906,56 +1895,42 @@
]
},
"imul ax, bx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"sxth x20, w20",
"sxth x21, w21",
"sxth x20, w4",
"sxth x21, w7",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"mov w22, #0x0",
"sbfx x20, x20, #15, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w7",
"sxtw x20, w20",
"sxtw x21, w21",
"sxtw x20, w4",
"sxtw x21, w7",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"mov w22, #0x0",
"sbfx x20, x20, #31, #1",
"mov w23, #0x30000000",
"cmp x21, x20",
"csel x20, x22, x23, eq",
"msr nzcv, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"mov x20, x4",
"mul x4, x20, x7",
"smulh x20, x20, x7",
"mov w21, #0x0",
"asr x22, x4, #63",
"mov w23, #0x30000000",
"cmp x20, x22",
"csel x20, x21, x23, eq",
"msr nzcv, x20"
"smulh x20, x4, x7",
"mul x4, x4, x7",
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"cmpxchg al, bl": {
@@ -1977,12 +1952,12 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #24",
"mrs x21, nzcv",
"ubfx w24, w20, #8, #1",
"ubfx x24, x20, #8, #1",
"orr w21, w21, w24, lsl #29",
"eor w23, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w23",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2003,12 +1978,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2032,12 +2007,12 @@
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"mrs x21, nzcv",
"ubfx w24, w20, #16, #1",
"ubfx x24, x20, #16, #1",
"orr w21, w21, w24, lsl #29",
"eor w23, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w23",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2058,12 +2033,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"and w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2524,7 +2499,7 @@
]
},
"bsf ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth w20, w4",
@@ -2534,17 +2509,13 @@
"rbit w0, w0",
"clz w22, w0",
"csinv w22, w22, wzr, ne",
"cmp x21, #0x0 (0)",
"csel w20, w20, w22, eq",
"bfxil x4, x20, #0, #16",
"cmp x21, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsf eax, ebx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -2553,32 +2524,24 @@
"rbit w0, w0",
"clz w21, w0",
"csinv w21, w21, wzr, ne",
"cmp x20, #0x0 (0)",
"csel x4, x4, x21, eq",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsf rax, rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x0, x7",
"cmp x7, #0x0 (0)",
"clz x20, x0",
"csinv x20, x20, xzr, ne",
"cmp x7, #0x0 (0)",
"csel x4, x4, x20, eq",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"bsr ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth w20, w4",
@@ -2588,44 +2551,32 @@
"orr w22, w22, #0x8000",
"clz w22, w22",
"sub x22, x0, x22",
"cmp x21, #0x0 (0)",
"csel w20, w20, w22, eq",
"bfxil x4, x20, #0, #16",
"cmp x21, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsr eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x0, #0x1f",
"clz w21, w20",
"sub x21, x0, x21",
"cmp x20, #0x0 (0)",
"csel x4, x4, x21, eq",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsr rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov x0, #0x3f",
"clz x20, x7",
"sub x20, x0, x20",
"cmp x7, #0x0 (0)",
"csel x4, x4, x20, eq",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"movsx ax, bl": {
@@ -2728,12 +2679,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w21, w20, w21",
"eor w20, w22, w20",
"bic w20, w20, w21",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2751,12 +2702,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
"ubfx w24, w22, #8, #1",
"ubfx x24, x22, #8, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #7, #1",
"ubfx x20, x20, #7, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2775,12 +2726,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w21, w20, w21",
"eor w20, w22, w20",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
@@ -2798,12 +2749,12 @@
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",
"ubfx w24, w22, #16, #1",
"ubfx x24, x22, #16, #1",
"orr w23, w23, w24, lsl #29",
"eor w20, w21, w20",
"eor w21, w22, w21",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"msr nzcv, x20"
]
unittests/InstructionCountCI/Secondary_REP.json
+5 -5
View File
@@ -467,7 +467,7 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx w20, w20, #0, #1",
"ubfx x20, x20, #0, #1",
"orr w20, w21, w20, lsl #30",
"msr nzcv, x20"
]
@@ -482,7 +482,7 @@
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"ubfx w21, w4, #0, #1",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #30",
"msr nzcv, x20"
]
@@ -496,7 +496,7 @@
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"ubfx w21, w4, #0, #1",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #30",
"msr nzcv, x20"
]
@@ -513,7 +513,7 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx w20, w20, #15, #1",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #30",
"msr nzcv, x20"
]
@@ -527,7 +527,7 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"lsr w20, w20, #31",
"ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #30",
"msr nzcv, x20"
]