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ArchHelpers: Add cfinv()

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FlagM goodness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2023-11-01 15:44:35 -04:00
1 parent 39c5ab1c81
commit bbad06f81a
2 files changed
+8
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FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl
+5
View File
@@ -766,6 +766,11 @@ public:
EvaluateIntoFlags(Op, 1, rn);
}
void cfinv() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0001'1111;
dc32(Op);
}
// Conditional compare - register
void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0011'1010'010 << 21;
FEXCore/unittests/Emitter/ALU_Tests.cpp
+3
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@@ -1709,6 +1709,9 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Evaluate into flags") {
TEST_SINGLE(setf8(WReg::w30), "setf8 w30");
TEST_SINGLE(setf16(WReg::w30), "setf16 w30");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Carry flag invert") {
TEST_SINGLE(cfinv(), "cfinv");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Conditional compare - register") {
TEST_SINGLE(ccmn(Size::i32Bit, Reg::r29, Reg::r28, StatusFlags::None, Condition::CC_AL), "ccmn w29, w28, #nzcv, al");
TEST_SINGLE(ccmn(Size::i32Bit, Reg::r29, Reg::r28, StatusFlags::Flag_N, Condition::CC_AL), "ccmn w29, w28, #Nzcv, al");