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WOW64: Support inline SMC
Matches the ARM64EC handling
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573d0858ac
commit
b15e49910a
1 file changed
+13
-1
@@ -756,7 +756,19 @@ bool BTCpuResetToConsistentStateImpl(EXCEPTION_POINTERS* Ptrs) {
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std::scoped_lock Lock(ThreadCreationMutex);
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FEXCORE_PROFILE_INSTANT_INCREMENT(Thread, AccumulatedSMCCount, 1);
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if (InvalidationTracker->HandleRWXAccessViolation(FaultAddress)) {
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LogMan::Msg::DFmt("Handled self-modifying code: pc: {:X} fault: {:X}", Context->Pc, FaultAddress);
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if (CTX->IsAddressInCodeBuffer(Thread, Context->Pc) && !CTX->IsCurrentBlockSingleInst(Thread) &&
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CTX->IsAddressInCurrentBlock(Thread, FaultAddress & FEXCore::Utils::FEX_PAGE_MASK, FEXCore::Utils::FEX_PAGE_SIZE)) {
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Context::ReconstructThreadState(Context);
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LogMan::Msg::DFmt("Handled inline self-modifying code: pc: {:X} rip: {:X} fault: {:X}", Context->Pc,
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Thread->CurrentFrame->State.rip, FaultAddress);
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// Adjust context to return to the dispatcher, reloading SRA from thread state
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const auto& Config = SignalDelegator->GetConfig();
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Context->Pc = Config.AbsoluteLoopTopAddressFillSRA;
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Context->X1 = 1; // Set ENTRY_FILL_SRA_SINGLE_INST_REG to force a single step
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} else {
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LogMan::Msg::DFmt("Handled self-modifying code: pc: {:X} fault: {:X}", Context->Pc, FaultAddress);
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}
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return true;
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}
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}
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