WOW64: Support inline SMC

Matches the ARM64EC handling
This commit is contained in:
Billy Laws committed 2025-07-23 18:46:28 +01:00
1 parent 573d0858ac
commit b15e49910a
1 file changed
+13 -1
+13 -1
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@@ -756,7 +756,19 @@ bool BTCpuResetToConsistentStateImpl(EXCEPTION_POINTERS* Ptrs) {
std::scoped_lock Lock(ThreadCreationMutex);
FEXCORE_PROFILE_INSTANT_INCREMENT(Thread, AccumulatedSMCCount, 1);
if (InvalidationTracker->HandleRWXAccessViolation(FaultAddress)) {
LogMan::Msg::DFmt("Handled self-modifying code: pc: {:X} fault: {:X}", Context->Pc, FaultAddress);
if (CTX->IsAddressInCodeBuffer(Thread, Context->Pc) && !CTX->IsCurrentBlockSingleInst(Thread) &&
CTX->IsAddressInCurrentBlock(Thread, FaultAddress & FEXCore::Utils::FEX_PAGE_MASK, FEXCore::Utils::FEX_PAGE_SIZE)) {
Context::ReconstructThreadState(Context);
LogMan::Msg::DFmt("Handled inline self-modifying code: pc: {:X} rip: {:X} fault: {:X}", Context->Pc,
Thread->CurrentFrame->State.rip, FaultAddress);
// Adjust context to return to the dispatcher, reloading SRA from thread state
const auto& Config = SignalDelegator->GetConfig();
Context->Pc = Config.AbsoluteLoopTopAddressFillSRA;
Context->X1 = 1; // Set ENTRY_FILL_SRA_SINGLE_INST_REG to force a single step
} else {
LogMan::Msg::DFmt("Handled self-modifying code: pc: {:X} fault: {:X}", Context->Pc, FaultAddress);
}
return true;
}
}