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Merge pull request #4929 from Sonicadvance1/sse4a_imm

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OpcodeDispatcher: Implement support for imm variants of SSE4a extrq/insertq
This commit is contained in:
LC authored and GitHub committed 2025-10-03 17:40:19 -04:00
2 parents 86898035da 69f3ab14b9
commit a9fffe771b
15 files changed
+263 -23
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FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
+4 -1
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@@ -41,6 +41,7 @@ namespace FEXCore::CPU {
const auto Op = IROp->C<IR::IROp_##FEXOp>(); \
const auto OpSize = IROp->Size; \
const auto Is256Bit = OpSize == IR::OpSize::i256Bit; \
const auto Is128Bit = OpSize == IR::OpSize::i128Bit; \
LOGMAN_THROW_A_FMT(!Is256Bit || HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__); \
\
const auto Dst = GetVReg(Node); \
@@ -49,8 +50,10 @@ namespace FEXCore::CPU {
\
if (HostSupportsSVE256 && Is256Bit) { \
ARMOp(Dst.Z(), Vector1.Z(), Vector2.Z()); \
} else { \
} else if (Is128Bit) { \
ARMOp(Dst.Q(), Vector1.Q(), Vector2.Q()); \
} else { \
ARMOp(Dst.D(), Vector1.D(), Vector2.D()); \
} \
}
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+2
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@@ -908,6 +908,8 @@ public:
void VPCLMULQDQOp(OpcodeArgs);
void CRC32(OpcodeArgs);
void Extrq_imm(OpcodeArgs);
void Insertq_imm(OpcodeArgs);
void BreakOp(OpcodeArgs, FEXCore::IR::BreakDefinition BreakDefinition);
void UnimplementedOp(OpcodeArgs);
FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryGroupTables.h
+3
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@@ -151,6 +151,9 @@ constexpr DispatchTableEntry OpDispatch_SecondaryGroupTables[] = {
{OPD(FEXCore::X86Tables::TYPE_GROUP_16, PF_F2, 3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::Prefetch, false, false, 3>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_16, PF_F2, 4), 4, &OpDispatchBuilder::NOPOp},
// GROUP 17
{OPD(FEXCore::X86Tables::TYPE_GROUP_17, PF_66, 0), 1, &OpDispatchBuilder::Extrq_imm},
// GROUP P
{OPD(FEXCore::X86Tables::TYPE_GROUP_P, PF_NONE, 0), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::Prefetch, false, false, 1>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_P, PF_NONE, 1), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::Prefetch, true, false, 1>},
FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h
+1
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@@ -198,6 +198,7 @@ constexpr DispatchTableEntry OpDispatch_SecondaryRepNEModTables[] = {
{0x5E, 1, &OpDispatchBuilder::VectorScalarInsertALUOp<IR::OP_VFDIVSCALARINSERT, OpSize::i64Bit>},
{0x5F, 1, &OpDispatchBuilder::VectorScalarInsertALUOp<IR::OP_VFMAXSCALARINSERT, OpSize::i64Bit>},
{0x70, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PSHUFWOp, true>},
{0x78, 1, &OpDispatchBuilder::Insertq_imm},
{0x7C, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADDP, OpSize::i32Bit>},
{0x7D, 1, &OpDispatchBuilder::HSUBP<OpSize::i32Bit>},
{0xD0, 1, &OpDispatchBuilder::ADDSUBPOp<OpSize::i32Bit>},
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+47
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@@ -5132,4 +5132,51 @@ void OpDispatchBuilder::VPGATHER(OpcodeArgs) {
template void OpDispatchBuilder::VPGATHER<OpSize::i32Bit>(OpcodeArgs);
template void OpDispatchBuilder::VPGATHER<OpSize::i64Bit>(OpcodeArgs);
void OpDispatchBuilder::Extrq_imm(OpcodeArgs) {
const uint8_t MaskWidth = Op->Src[1].Literal() & 0x3F;
const uint8_t Shift = (Op->Src[1].Literal() >> 8) & 0x3F;
Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
Ref Result = Dest;
if (Shift > 0) {
Result = _VUShrI(OpSize::i64Bit, OpSize::i64Bit, Dest, Shift);
}
const uint64_t Mask = ~0ULL >> (MaskWidth == 0 ? 0 : (64 - MaskWidth));
const Ref ZeroRegister = LoadZeroVector(OpSize::i128Bit);
const Ref MaskVector = _VInsGPR(OpSize::i128Bit, OpSize::i64Bit, 0, ZeroRegister, _Constant(Mask));
Result = _VAnd(OpSize::i128Bit, OpSize::i64Bit, Result, MaskVector);
StoreResultFPR(Op, Result, OpSize::iInvalid);
}
void OpDispatchBuilder::Insertq_imm(OpcodeArgs) {
const uint8_t MaskWidth = Op->Src[1].Literal() & 0x3F;
const uint8_t Shift = (Op->Src[1].Literal() >> 8) & 0x3F;
Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
const uint64_t Mask = ~0ULL >> (MaskWidth == 0 ? 0 : (64 - MaskWidth));
const Ref ZeroRegister = LoadZeroVector(OpSize::i128Bit);
Ref MaskVector = _VInsGPR(OpSize::i128Bit, OpSize::i64Bit, 0, ZeroRegister, _Constant(Mask));
// Mask incoming source.
Src = _VAnd(OpSize::i64Bit, OpSize::i64Bit, Src, MaskVector);
// If shifting then shift source and mask in to the correct location.
if (Shift) {
Src = _VShlI(OpSize::i64Bit, OpSize::i64Bit, Src, Shift);
MaskVector = _VShlI(OpSize::i128Bit, OpSize::i64Bit, MaskVector, Shift);
}
// Negate the mask.
MaskVector = _VNot(OpSize::i64Bit, OpSize::i64Bit, MaskVector);
Dest = _VAnd(OpSize::i64Bit, OpSize::i64Bit, Dest, MaskVector);
const Ref Result = _VOr(OpSize::i64Bit, OpSize::i64Bit, Dest, Src);
StoreResultFPR(Op, Result, OpSize::iInvalid);
}
} // namespace FEXCore::IR
FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp
+1 -1
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@@ -442,7 +442,7 @@ constexpr std::array<X86InstInfo, MAX_REPNE_MOD_TABLE_SIZE> RepNEModOps = []() c
{0x70, 1, X86InstInfo{"PSHUFLW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
{0x71, 3, X86InstInfo{"", TYPE_COPY_OTHER, FLAGS_NONE, 0}},
{0x74, 4, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0}},
{0x78, 1, X86InstInfo{"INSERTQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_XMM_FLAGS,2}},
{0x78, 1, X86InstInfo{"INSERTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_XMM_FLAGS,2}},
{0x79, 1, X86InstInfo{"INSERTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_XMM_FLAGS, 0}},
{0x7A, 2, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0}},
{0x7C, 1, X86InstInfo{"HADDPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
FEXCore/Source/Interface/IR/IR.json
+16 -4
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@@ -2150,22 +2150,34 @@
"FPR = VAnd OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"ElementSize": "ElementSize"
"ElementSize": "ElementSize",
"EmitValidation": [
"RegisterSize == FEXCore::IR::OpSize::i256Bit || RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i64Bit"
]
},
"FPR = VAndn OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"ElementSize": "ElementSize"
"ElementSize": "ElementSize",
"EmitValidation": [
"RegisterSize == FEXCore::IR::OpSize::i256Bit || RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i64Bit"
]
},
"FPR = VOr OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"ElementSize": "ElementSize"
"ElementSize": "ElementSize",
"EmitValidation": [
"RegisterSize == FEXCore::IR::OpSize::i256Bit || RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i64Bit"
]
},
"FPR = VXor OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"ElementSize": "ElementSize"
"ElementSize": "ElementSize",
"EmitValidation": [
"RegisterSize == FEXCore::IR::OpSize::i256Bit || RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i64Bit"
]
},
"FPR = VUQAdd OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
unittests/ASM/Disabled_Tests_Simulator
+4
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@@ -110,3 +110,7 @@ Test_Secondary/09_F3_07.asm
# Vixl sim at 256-bit vector width access too much memory with some AVX instructions
Test_modrm_oob/VEX.asm
# Vixl simulator with 256-bit vector width doesn't always do correct data retention for 128-bit non-AVX operations.
Test_SSE4a/extrq_imm.asm
Test_SSE4a/insertq_imm.asm
unittests/ASM/SSE4a/extrq_imm.asm
+59
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@@ -0,0 +1,59 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x48510f254d2fa47f", "0", "0x30b556de1f6de86b", "0x67d29af330ae762c"],
"XMM1": ["0", "0", "0xb615b9533de8ad09", "0xb76472a37404b890"],
"XMM2": ["0x3615b9533de8ad09", "0", "0x24426b4c72f110ad", "0x8a6789f2d415a567"],
"XMM3": ["0", "0", "0x8996f88178236612", "0x19a26b823d3ca2a9"],
"XMM4": ["0x00000001132df102", "0", "0x00f658ab689712b0", "0xc97d9d031ed21972"],
"XMM5": ["0x0000000001ecb156", "0", "0x1c86432298df55c8", "0xb29bfeda891be9cc"],
"XMM6": ["0x00000000432298df", "0", "0x88b0bd28710f2147", "0xc4e95e887fb5ac38"],
"XMM7": ["0x0000b0bd28710f21", "0", "0xa7df8c2ad03e5be4", "0x6c70d1eec2d395ea"]
}
}
%endif
; Random data
vmovups ymm0, [rel .random_data + (0 * 16)]
vmovups ymm1, [rel .random_data + (1 * 16)]
vmovups ymm2, [rel .random_data + (2 * 16)]
vmovups ymm3, [rel .random_data + (3 * 16)]
vmovups ymm4, [rel .random_data + (4 * 16)]
vmovups ymm5, [rel .random_data + (5 * 16)]
vmovups ymm6, [rel .random_data + (6 * 16)]
vmovups ymm7, [rel .random_data + (7 * 16)]
; imm extrq
; The upper 64-bits of the xmm are "undefined." Zen will zero.
; Additionally if width and length is > 64 then the results are undefined.
; - Behaviour is actually shift then mask so FEX matches "undefined" behaviour here.
extrq xmm0, 0, 0
extrq xmm1, 0, 63
extrq xmm2, 63, 0
extrq xmm3, 63, 63
extrq xmm4, 0, 31
extrq xmm5, 31, 31
extrq xmm6, 31, 16
extrq xmm7, 48, 8
hlt
align 16
; 256bytes of random data
.random_data:
db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
unittests/ASM/SSE4a/insertq_imm.asm
+67
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@@ -0,0 +1,67 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0xa7df8c2ad03e5be4", "0", "0x30b556de1f6de86b", "0x67d29af330ae762c"],
"XMM1": ["0x30b556de1f6de86b", "0", "0xb615b9533de8ad09", "0xb76472a37404b890"],
"XMM2": ["0xc1029b7f255b4cf4", "0", "0x24426b4c72f110ad", "0x8a6789f2d415a567"],
"XMM3": ["0x24426b4c72f110ad", "0", "0x8996f88178236612", "0x19a26b823d3ca2a9"],
"XMM4": ["0xd47dbb9e78236612", "0", "0x00f658ab689712b0", "0xc97d9d031ed21972"],
"XMM5": ["0x017003bfe89712b0", "0", "0x1c86432298df55c8", "0xb29bfeda891be9cc"],
"XMM6": ["0x1c8678f6900455c8", "0", "0x88b0bd28710f2147", "0xc4e95e887fb5ac38"],
"XMM7": ["0x881fa17837c17f47", "0", "0xa7df8c2ad03e5be4", "0x6c70d1eec2d395ea"]
}
}
%endif
; Random data
vmovups ymm0, [rel .random_data + (0 * 16)]
vmovups ymm1, [rel .random_data + (1 * 16)]
vmovups ymm2, [rel .random_data + (2 * 16)]
vmovups ymm3, [rel .random_data + (3 * 16)]
vmovups ymm4, [rel .random_data + (4 * 16)]
vmovups ymm5, [rel .random_data + (5 * 16)]
vmovups ymm6, [rel .random_data + (6 * 16)]
vmovups ymm7, [rel .random_data + (7 * 16)]
vmovups ymm8, [rel .random_data + (8 * 16)]
vmovups ymm9, [rel .random_data + (9 * 16)]
vmovups ymm10, [rel .random_data + (10 * 16)]
vmovups ymm11, [rel .random_data + (11 * 16)]
vmovups ymm12, [rel .random_data + (12 * 16)]
vmovups ymm13, [rel .random_data + (13 * 16)]
vmovups ymm14, [rel .random_data + (14 * 16)]
vmovups ymm15, [rel .random_data + (15 * 16)]
; imm insertq
; The upper 64-bits of the xmm are "undefined." Zen will zero.
; Additionally if width and length is > 64 then the results are undefined.
; - Behaviour is actually shift then mask so FEX matches "undefined" behaviour here.
insertq xmm0, xmm8, 0, 0
insertq xmm1, xmm9, 0, 63
insertq xmm2, xmm10, 63, 0
insertq xmm3, xmm11, 63, 63
insertq xmm4, xmm12, 0, 31
insertq xmm5, xmm13, 31, 31
insertq xmm6, xmm14, 31, 16
insertq xmm7, xmm15, 48, 8
hlt
align 16
; 256bytes of random data
.random_data:
db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -1610,7 +1610,7 @@
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #3216]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"and v2.8b, v2.8b, v3.8b",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"addp v2.8b, v2.8b, v2.8b",
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -24,7 +24,7 @@
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"movi v4.16b, #0x87",
"and v3.16b, v3.16b, v4.16b",
"and v3.8b, v3.8b, v4.8b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
unittests/InstructionCountCI/Secondary.json
+5 -5
View File
@@ -3692,7 +3692,7 @@
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #3216]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"and v2.8b, v2.8b, v3.8b",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"addp v2.8b, v2.8b, v2.8b",
@@ -3750,7 +3750,7 @@
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"and v2.16b, v3.16b, v2.16b",
"and v2.8b, v3.8b, v2.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
]
@@ -3806,7 +3806,7 @@
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"bic v2.16b, v2.16b, v3.16b",
"bic v2.8b, v2.8b, v3.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
]
@@ -3967,7 +3967,7 @@
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"orr v2.16b, v3.16b, v2.16b",
"orr v2.8b, v3.8b, v2.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
]
@@ -4023,7 +4023,7 @@
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"eor v2.16b, v3.16b, v2.16b",
"eor v2.8b, v3.8b, v2.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
]
unittests/InstructionCountCI/Secondary_OpSize.json
+22 -6
View File
@@ -799,27 +799,43 @@
]
},
"extrq xmm0, 64, 0": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 4,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"and v16.16b, v16.16b, v2.16b"
]
},
"extrq xmm0, 32, 32": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 5,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"ushr v2.2d, v16.2d, #32",
"movi v3.2d, #0x0",
"mov w20, #0xffffffff",
"mov v3.d[0], x20",
"and v16.16b, v2.16b, v3.16b"
]
},
"extrq xmm0, 0, 0": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 4,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"and v16.16b, v16.16b, v2.16b"
]
},
"extrq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+30 -4
View File
@@ -321,26 +321,52 @@
},
"insertq xmm0, xmm1, 0, 0": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"and v3.8b, v17.8b, v2.8b",
"mvn v2.16b, v2.16b",
"and v2.8b, v16.8b, v2.8b",
"orr v16.8b, v2.8b, v3.8b"
]
},
"insertq xmm0, xmm1, 64, 0": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"and v3.8b, v17.8b, v2.8b",
"mvn v2.16b, v2.16b",
"and v2.8b, v16.8b, v2.8b",
"orr v16.8b, v2.8b, v3.8b"
]
},
"insertq xmm0, xmm1, 32, 32": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 9,
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov w20, #0xffffffff",
"mov v2.d[0], x20",
"and v3.8b, v17.8b, v2.8b",
"shl v3.2d, v3.2d, #32",
"shl v2.2d, v2.2d, #32",
"mvn v2.16b, v2.16b",
"and v2.8b, v16.8b, v2.8b",
"orr v16.8b, v2.8b, v3.8b"
]
},
"insertq xmm0, xmm1": {