mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 18:00:17 +02:00
Merge pull request #2302 from lioncash/dpp
OpcodeDispatcher: Handle VDPPD/VDPPS
This commit is contained in:
7 files changed
+258
-22
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@@ -6082,6 +6082,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
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{OPD(3, 0b01, 0x38), 1, &OpDispatchBuilder::VINSERTOp},
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{OPD(3, 0b01, 0x40), 1, &OpDispatchBuilder::VDPPOp<4>},
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{OPD(3, 0b01, 0x41), 1, &OpDispatchBuilder::VDPPOp<8>},
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{OPD(3, 0b01, 0x46), 1, &OpDispatchBuilder::VPERM2Op},
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{OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::VAESKeyGenAssistOp},
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@@ -440,6 +440,9 @@ public:
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template <size_t ElementSize>
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void VBROADCASTOp(OpcodeArgs);
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template <size_t ElementSize>
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void VDPPOp(OpcodeArgs);
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template <IROps IROp, size_t ElementSize>
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void VHADDPOp(OpcodeArgs);
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@@ -751,6 +754,10 @@ private:
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OrderedNode* AESKeyGenAssistImpl(OpcodeArgs);
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OrderedNode* AESIMCImpl(OpcodeArgs);
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OrderedNode* DPPOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2,
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const X86Tables::DecodedOperand& Imm, size_t ElementSize);
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OrderedNode* ExtendVectorElementsImpl(OpcodeArgs, size_t ElementSize,
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size_t DstElementSize, bool Signed);
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@@ -3488,47 +3488,60 @@ void OpDispatchBuilder::VPHMINPOSUWOp(OpcodeArgs) {
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StoreResult(FPRClass, Op, Result, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::DPPOp(OpcodeArgs) {
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LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
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uint8_t Mask = Op->Src[1].Data.Literal.Value;
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uint8_t SrcMask = Mask >> 4;
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uint8_t DstMask = Mask & 0xF;
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OrderedNode* OpDispatchBuilder::DPPOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2,
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const X86Tables::DecodedOperand& Imm, size_t ElementSize) {
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LOGMAN_THROW_A_FMT(Imm.IsLiteral(), "Imm needs to be literal here");
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const uint8_t Mask = Imm.Data.Literal.Value;
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const uint8_t SrcMask = Mask >> 4;
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const uint8_t DstMask = Mask & 0xF;
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OrderedNode *ZeroVec = _VectorZero(16);
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const auto DstSize = GetDstSize(Op);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Src1V = LoadSource(FPRClass, Op, Src1, Op->Flags, -1);
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OrderedNode *Src2V = LoadSource(FPRClass, Op, Src2, Op->Flags, -1);
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OrderedNode *ZeroVec = _VectorZero(DstSize);
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// First step is to do an FMUL
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OrderedNode *Temp = _VFMul(16, ElementSize, Dest, Src);
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OrderedNode *Temp = _VFMul(DstSize, ElementSize, Src1V, Src2V);
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// Now we zero out elements based on src mask
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for (size_t i = 0; i < (16 / ElementSize); ++i) {
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if ((SrcMask & (1 << i)) == 0) {
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Temp = _VInsElement(16, ElementSize, i, 0, Temp, ZeroVec);
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for (size_t i = 0; i < (DstSize / ElementSize); ++i) {
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const auto Bit = 1U << (i % 4);
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if ((SrcMask & Bit) == 0) {
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Temp = _VInsElement(DstSize, ElementSize, i, 0, Temp, ZeroVec);
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}
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}
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// Now we need to do a horizontal add of the elements
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// We only have pairwise float add so this needs to be done in steps
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Temp = _VFAddP(16, ElementSize, Temp, ZeroVec);
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Temp = _VFAddP(DstSize, ElementSize, Temp, ZeroVec);
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if constexpr (ElementSize == 4) {
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if (ElementSize == 4) {
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// For 32-bit float we need one more step to add all four results together
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Temp = _VFAddP(16, ElementSize, Temp, ZeroVec);
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Temp = _VFAddP(DstSize, ElementSize, Temp, ZeroVec);
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}
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// Now using the destination mask we choose where the result ends up
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// It can duplicate and zero results
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auto Result = ZeroVec;
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OrderedNode *Result = ZeroVec;
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for (size_t i = 0; i < (16 / ElementSize); ++i) {
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if (DstMask & (1 << i)) {
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Result = _VInsElement(16, ElementSize, i, 0, Result, Temp);
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for (size_t i = 0; i < (DstSize / ElementSize); ++i) {
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const auto Bit = 1U << (i % 4);
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if ((DstMask & Bit) != 0) {
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Result = _VInsElement(DstSize, ElementSize, i, 0, Result, Temp);
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}
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}
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return Result;
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::DPPOp(OpcodeArgs) {
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OrderedNode *Result = DPPOpImpl(Op, Op->Dest, Op->Src[0], Op->Src[1], ElementSize);
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StoreResult(FPRClass, Op, Result, -1);
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}
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@@ -3537,6 +3550,20 @@ void OpDispatchBuilder::DPPOp<4>(OpcodeArgs);
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template
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void OpDispatchBuilder::DPPOp<8>(OpcodeArgs);
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template <size_t ElementSize>
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void OpDispatchBuilder::VDPPOp(OpcodeArgs) {
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OrderedNode *Result = DPPOpImpl(Op, Op->Src[0], Op->Src[1], Op->Src[2], ElementSize);
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// We don't need to emit a _VMov to clear the upper lane, since DPPOpImpl uses a zero vector
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// to construct the results, so the upper lane will always be cleared for the 128-bit version.
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StoreResult(FPRClass, Op, Result, -1);
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}
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template
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void OpDispatchBuilder::VDPPOp<4>(OpcodeArgs);
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template
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void OpDispatchBuilder::VDPPOp<8>(OpcodeArgs);
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void OpDispatchBuilder::MPSADBWOp(OpcodeArgs) {
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LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
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uint8_t Select = Op->Src[1].Data.Literal.Value;
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@@ -437,8 +437,8 @@ void InitializeVEXTables() {
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{OPD(3, 0b01, 0x38), 1, X86InstInfo{"VINSERTI128", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x39), 1, X86InstInfo{"VEXTRACTI128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x40), 1, X86InstInfo{"VDPPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x41), 1, X86InstInfo{"VDPPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x40), 1, X86InstInfo{"VDPPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x41), 1, X86InstInfo{"VDPPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x42), 1, X86InstInfo{"VMPSADBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x44), 1, X86InstInfo{"VPCLMULQDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x46), 1, X86InstInfo{"VPERM2I128", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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@@ -0,0 +1,56 @@
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%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM8": ["0x41278C496C911A6E", "0x41278C496C911A6E", "0x0000000000000000", "0x0000000000000000"],
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"XMM9": ["0x41235CCC64AFB361", "0x41235CCC64AFB361", "0x0000000000000000", "0x0000000000000000"],
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"XMM10": ["0x412BACE273945DC5", "0x412BACE273945DC5", "0x0000000000000000", "0x0000000000000000"],
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"XMM11": ["0x412CF22EF582FD76", "0x412CF22EF582FD76", "0x0000000000000000", "0x0000000000000000"],
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"XMM12": ["0x4121C80E40F3BC7B", "0x4121C80E40F3BC7B", "0x0000000000000000", "0x0000000000000000"],
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"XMM13": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM14": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM15": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"]
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}
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}
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%endif
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lea rdx, [rel .data]
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vmovaps xmm0, [rdx + 16 * 0]
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vmovaps xmm1, [rdx + 16 * 1]
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vmovaps xmm2, [rdx + 16 * 2]
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vmovaps xmm3, [rdx + 16 * 3]
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vmovaps xmm4, [rdx + 16 * 4]
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vmovaps xmm5, [rdx + 16 * 5]
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vmovaps xmm6, [rdx + 16 * 6]
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vmovaps xmm7, [rdx + 16 * 7]
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vdppd xmm8, xmm0, [rdx + 16 * 8], 11111111b
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vdppd xmm9, xmm1, [rdx + 16 * 9], 11111111b
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vdppd xmm10, xmm2, [rdx + 16 * 10], 11111111b
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vdppd xmm11, xmm3, [rdx + 16 * 11], 11111111b
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vdppd xmm12, xmm4, [rdx + 16 * 12], 11111111b
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vdppd xmm13, xmm5, [rdx + 16 * 13], 00000000b
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vdppd xmm14, xmm6, [rdx + 16 * 14], 11110000b
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vdppd xmm15, xmm7, [rdx + 16 * 15], 00001111b
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hlt
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align 32
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.data:
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dq 470.4127, 683.87
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dq 711.3545, 511.5631
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dq 996.8793, 548.682
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dq 588.9345, 832.5925
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dq 210.6613, 792.6059
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dq 298.4494, 154.4895
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dq 818.4 , 881.6027
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dq 705.3087, 687.478
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dq 737.0665, 621.31
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dq 755.3097, 189.9614
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dq 552.4284, 649.1206
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dq 798.252 , 574.5732
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dq 593.7565, 577.3129
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dq 383.3844, 443.3476
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dq 414.3571, 615.1567
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dq 94.898 , 438.3107
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@@ -0,0 +1,56 @@
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%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM8": ["0x492FEB2E492FEB2E", "0x492FEB2E492FEB2E", "0x0000000000000000", "0x0000000000000000"],
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"XMM9": ["0x499A5226499A5226", "0x499A5226499A5226", "0x0000000000000000", "0x0000000000000000"],
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"XMM10": ["0x494ECFA4494ECFA4", "0x494ECFA4494ECFA4", "0x0000000000000000", "0x0000000000000000"],
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"XMM11": ["0x495F7816495F7816", "0x495F7816495F7816", "0x0000000000000000", "0x0000000000000000"],
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"XMM12": ["0x496E3962496E3962", "0x496E3962496E3962", "0x0000000000000000", "0x0000000000000000"],
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"XMM13": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM14": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM15": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"]
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}
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}
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%endif
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lea rdx, [rel .data]
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vmovaps xmm0, [rdx + 16 * 0]
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vmovaps xmm1, [rdx + 16 * 1]
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vmovaps xmm2, [rdx + 16 * 2]
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vmovaps xmm3, [rdx + 16 * 3]
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vmovaps xmm4, [rdx + 16 * 4]
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vmovaps xmm5, [rdx + 16 * 5]
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vmovaps xmm6, [rdx + 16 * 6]
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vmovaps xmm7, [rdx + 16 * 7]
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vdpps xmm8, xmm0, [rdx + 16 * 8], 11111111b
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vdpps xmm9, xmm1, [rdx + 16 * 9], 11111111b
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vdpps xmm10, xmm2, [rdx + 16 * 10], 11111111b
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vdpps xmm11, xmm3, [rdx + 16 * 11], 11111111b
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vdpps xmm12, xmm4, [rdx + 16 * 12], 11111111b
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vdpps xmm13, xmm5, [rdx + 16 * 13], 00000000b
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vdpps xmm14, xmm6, [rdx + 16 * 14], 11110000b
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vdpps xmm15, xmm7, [rdx + 16 * 15], 00001111b
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hlt
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align 32
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.data:
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dd 655.9708, 532.2244, 108.0451, 512.4019
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dd 754.227 , 586.0859, 127.7574, 114.8167
|
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dd 764.4266, 226.6145, 337.864 , 320.3296
|
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dd 296.5247, 480.0057, 28.4267 , 565.9418
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dd 265.8255, 536.4473, 754.3489, 460.681
|
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dd 818.7269, 43.7204 , 464.592 , 847.9381
|
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dd 306.0592, 702.7584, 887.6473, 551.5908
|
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dd 620.9001, 520.9829, 232.9532, 510.3388
|
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dd 204.8474, 225.626 , 564.973 , 790.5175
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dd 836.1953, 844.5266, 633.5626, 501.7409
|
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dd 393.2616, 674.4415, 244.3265, 971.1598
|
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dd 770.8029, 746.1836, 255.9902, 567.7578
|
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dd 187.7175, 924.181 , 466.4362, 169.8267
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dd 651.7481, 462.4206, 396.6924, 355.8538
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dd 6.148 , 523.1443, 989.7004, 713.6646
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dd 497.5427, 657.6965, 651.0534, 778.5236
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@@ -0,0 +1,87 @@
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%ifdef CONFIG
|
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{
|
||||
"HostFeatures": ["AVX"],
|
||||
"RegData": {
|
||||
"XMM8": ["0x492FEB2E492FEB2E", "0x492FEB2E492FEB2E", "0x492FEB2E492FEB2E", "0x492FEB2E492FEB2E"],
|
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"XMM9": ["0x499A5226499A5226", "0x499A5226499A5226", "0x499A5226499A5226", "0x499A5226499A5226"],
|
||||
"XMM10": ["0x494ECFA4494ECFA4", "0x494ECFA4494ECFA4", "0x494ECFA4494ECFA4", "0x494ECFA4494ECFA4"],
|
||||
"XMM11": ["0x495F7816495F7816", "0x495F7816495F7816", "0x495F7816495F7816", "0x495F7816495F7816"],
|
||||
"XMM12": ["0x496E3962496E3962", "0x496E3962496E3962", "0x496E3962496E3962", "0x496E3962496E3962"],
|
||||
"XMM13": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM14": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM15": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"]
|
||||
}
|
||||
}
|
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%endif
|
||||
|
||||
lea rdx, [rel .data]
|
||||
|
||||
vmovaps ymm0, [rdx + 32 * 0]
|
||||
vmovaps ymm1, [rdx + 32 * 1]
|
||||
vmovaps ymm2, [rdx + 32 * 2]
|
||||
vmovaps ymm3, [rdx + 32 * 3]
|
||||
vmovaps ymm4, [rdx + 32 * 4]
|
||||
vmovaps ymm5, [rdx + 32 * 5]
|
||||
vmovaps ymm6, [rdx + 32 * 6]
|
||||
vmovaps ymm7, [rdx + 32 * 7]
|
||||
|
||||
vdpps ymm8, ymm0, [rdx + 32 * 8], 11111111b
|
||||
vdpps ymm9, ymm1, [rdx + 32 * 9], 11111111b
|
||||
vdpps ymm10, ymm2, [rdx + 32 * 10], 11111111b
|
||||
vdpps ymm11, ymm3, [rdx + 32 * 11], 11111111b
|
||||
vdpps ymm12, ymm4, [rdx + 32 * 12], 11111111b
|
||||
vdpps ymm13, ymm5, [rdx + 32 * 13], 00000000b
|
||||
vdpps ymm14, ymm6, [rdx + 32 * 14], 11110000b
|
||||
vdpps ymm15, ymm7, [rdx + 32 * 15], 00001111b
|
||||
|
||||
hlt
|
||||
|
||||
align 32
|
||||
.data:
|
||||
dd 655.9708, 532.2244, 108.0451, 512.4019
|
||||
dd 655.9708, 532.2244, 108.0451, 512.4019
|
||||
|
||||
dd 754.227 , 586.0859, 127.7574, 114.8167
|
||||
dd 754.227 , 586.0859, 127.7574, 114.8167
|
||||
|
||||
dd 764.4266, 226.6145, 337.864 , 320.3296
|
||||
dd 764.4266, 226.6145, 337.864 , 320.3296
|
||||
|
||||
dd 296.5247, 480.0057, 28.4267 , 565.9418
|
||||
dd 296.5247, 480.0057, 28.4267 , 565.9418
|
||||
|
||||
dd 265.8255, 536.4473, 754.3489, 460.681
|
||||
dd 265.8255, 536.4473, 754.3489, 460.681
|
||||
|
||||
dd 818.7269, 43.7204 , 464.592 , 847.9381
|
||||
dd 818.7269, 43.7204 , 464.592 , 847.9381
|
||||
|
||||
dd 306.0592, 702.7584, 887.6473, 551.5908
|
||||
dd 306.0592, 702.7584, 887.6473, 551.5908
|
||||
|
||||
dd 620.9001, 520.9829, 232.9532, 510.3388
|
||||
dd 620.9001, 520.9829, 232.9532, 510.3388
|
||||
|
||||
dd 204.8474, 225.626 , 564.973 , 790.5175
|
||||
dd 204.8474, 225.626 , 564.973 , 790.5175
|
||||
|
||||
dd 836.1953, 844.5266, 633.5626, 501.7409
|
||||
dd 836.1953, 844.5266, 633.5626, 501.7409
|
||||
|
||||
dd 393.2616, 674.4415, 244.3265, 971.1598
|
||||
dd 393.2616, 674.4415, 244.3265, 971.1598
|
||||
|
||||
dd 770.8029, 746.1836, 255.9902, 567.7578
|
||||
dd 770.8029, 746.1836, 255.9902, 567.7578
|
||||
|
||||
dd 187.7175, 924.181 , 466.4362, 169.8267
|
||||
dd 187.7175, 924.181 , 466.4362, 169.8267
|
||||
|
||||
dd 651.7481, 462.4206, 396.6924, 355.8538
|
||||
dd 651.7481, 462.4206, 396.6924, 355.8538
|
||||
|
||||
dd 6.148 , 523.1443, 989.7004, 713.6646
|
||||
dd 6.148 , 523.1443, 989.7004, 713.6646
|
||||
|
||||
dd 497.5427, 657.6965, 651.0534, 778.5236
|
||||
dd 497.5427, 657.6965, 651.0534, 778.5236
|
||||
Reference in new issue
Block a user