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Merge pull request #3274 from alyssarosenzweig/opt/pf

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Arm64Emitter: Dedicate registers for PF/AF
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Ryan Houdek authored and GitHub committed 2023-11-17 16:45:38 -08:00
2 parents 1c115096c4 11993daec4
commit 9b646746b2
61 files changed
+21820 -21805
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FEXCore/Source/Interface/Context/Context.h
+1 -1
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@@ -107,7 +107,7 @@ namespace FEXCore::Context {
void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) override;
uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) override;
uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread) override;
uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, bool WasInJIT, uint64_t *HostGPRs, uint64_t PSTATE) override;
void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, uint32_t EFLAGS) override;
/**
FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+39 -12
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@@ -1,5 +1,6 @@
// SPDX-License-Identifier: MIT
#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
#include "FEXCore/Core/X86Enums.h"
#include "FEXCore/Utils/AllocatorHooks.h"
#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
@@ -28,7 +29,7 @@ namespace FEXCore::CPU {
namespace x64 {
// All but x19 and x29 are caller saved
constexpr std::array<FEXCore::ARMEmitter::Register, 16> SRA = {
constexpr std::array<FEXCore::ARMEmitter::Register, 18> SRA = {
FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9,
@@ -36,23 +37,23 @@ namespace x64 {
FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13,
FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r29
FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r29,
// PF/AF must be last.
REG_PF, REG_AF,
};
constexpr std::array<FEXCore::ARMEmitter::Register, 9> RA = {
constexpr std::array<FEXCore::ARMEmitter::Register, 7> RA = {
// All these callee saved
FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21,
FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25,
FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
FEXCore::ARMEmitter::Reg::r30,
};
constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 4> RAPair = {{
constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 3> RAPair = {{
{FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
{FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
{FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
{FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
}};
// All are caller saved
@@ -175,19 +176,20 @@ namespace x64 {
namespace x32 {
// All but x19 and x29 are caller saved
constexpr std::array<FEXCore::ARMEmitter::Register, 8> SRA = {
constexpr std::array<FEXCore::ARMEmitter::Register, 10> SRA = {
FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9,
FEXCore::ARMEmitter::Reg::r10, FEXCore::ARMEmitter::Reg::r11,
// PF/AF must be last.
REG_PF, REG_AF,
};
constexpr std::array<FEXCore::ARMEmitter::Register, 17> RA = {
constexpr std::array<FEXCore::ARMEmitter::Register, 15> RA = {
// All these callee saved
FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21,
FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25,
FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
// Registers only available on 32-bit
// All these are caller saved (except for r19).
@@ -199,11 +201,10 @@ namespace x32 {
FEXCore::ARMEmitter::Reg::r19,
};
constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 8> RAPair = {{
constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 7> RAPair = {{
{FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
{FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
{FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
{FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
{FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13},
{FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
@@ -368,7 +369,7 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr
GeneralFPRegisters = x64::RAFPR;
}
else {
ConfiguredDynamicRegisterBase = std::span(x32::RA.begin() + 8, 8);
ConfiguredDynamicRegisterBase = std::span(x32::RA.begin() + 6, 8);
StaticRegisters = x32::SRA;
GeneralRegisters = x32::RA;
@@ -613,6 +614,11 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
return;
}
// PF/AF are special, remove them from the mask
uint32_t PFAFMask = ((1u << REG_PF.Idx()) | ((1u << REG_AF.Idx())));
unsigned PFAFSpillMask = GPRSpillMask & PFAFMask;
GPRSpillMask &= ~PFAFSpillMask;
for (size_t i = 0; i < StaticRegisters.size(); i+=2) {
auto Reg1 = StaticRegisters[i];
auto Reg2 = StaticRegisters[i+1];
@@ -628,6 +634,14 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
}
}
// Now handle PF/AF
if (PFAFSpillMask) {
LOGMAN_THROW_A_FMT(PFAFSpillMask == PFAFMask, "PF/AF not spilled together");
str(REG_PF.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.pf_raw));
str(REG_AF.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.af_raw));
}
if (FPRs) {
if (EmitterCTX->HostFeatures.SupportsAVX) {
for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
@@ -770,6 +784,11 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
}
}
// PF/AF are special, remove them from the mask
uint32_t PFAFMask = ((1u << REG_PF.Idx()) | ((1u << REG_AF.Idx())));
uint32_t PFAFFillMask = GPRFillMask & PFAFMask;
GPRFillMask &= ~PFAFMask;
for (size_t i = 0; i < StaticRegisters.size(); i+=2) {
auto Reg1 = StaticRegisters[i];
auto Reg2 = StaticRegisters[i+1];
@@ -784,6 +803,14 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
ldr(Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1]));
}
}
// Now handle PF/AF
if (PFAFFillMask) {
LOGMAN_THROW_A_FMT(PFAFFillMask == PFAFMask, "PF/AF not filled together");
ldr(REG_PF.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.pf_raw));
ldr(REG_AF.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.af_raw));
}
}
void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs) {
FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
+4
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@@ -53,6 +53,10 @@ constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6;
constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7;
// We pin r26/r27 as PF/AF respectively, this is internal FEX ABI.
constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26;
constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27;
// This class contains common emitter utility functions that can
// be used by both Arm64 JIT and ARM64 Dispatcher
class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl
+10
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@@ -771,6 +771,16 @@ public:
dc32(Op);
}
void axflag() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0101'1111;
dc32(Op);
}
void xaflag() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0011'1111;
dc32(Op);
}
// Conditional compare - register
void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0011'1010'010 << 21;
FEXCore/Source/Interface/Core/Core.cpp
+22 -7
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@@ -11,6 +11,7 @@ $end_info$
#include <cstdint>
#include "FEXCore/Utils/DeferredSignalMutex.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/ArchHelpers//Arm64Emitter.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/CPUID.h"
#include "Interface/Core/Frontend.h"
@@ -220,7 +221,7 @@ namespace FEXCore::Context {
return Frame->State.rip;
}
uint32_t ContextImpl::ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread) {
uint32_t ContextImpl::ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, bool WasInJIT, uint64_t *HostGPRs, uint64_t PSTATE) {
const auto Frame = Thread->CurrentFrame;
uint32_t EFLAGS{};
@@ -242,9 +243,23 @@ namespace FEXCore::Context {
}
}
// SF/ZF/CF/OF are packed in a 32-bit value in RFLAG_NZCV_LOC.
uint32_t Packed_NZCV{};
memcpy(&Packed_NZCV, &Frame->State.flags[X86State::RFLAG_NZCV_LOC], sizeof(Packed_NZCV));
if (WasInJIT) {
// If we were in the JIT then NZCV is in the CPU's PSTATE object.
// Packed in to the same bit locations as RFLAG_NZCV_LOC.
Packed_NZCV = PSTATE;
// If we were in the JIT then PF and AF are in registers.
// Move them to the CPUState frame now.
Frame->State.pf_raw = HostGPRs[CPU::REG_PF.Idx()];
Frame->State.af_raw = HostGPRs[CPU::REG_AF.Idx()];
}
else {
// If we were not in the JIT then the NZCV state is stored in the CPUState RFLAG_NZCV_LOC.
// SF/ZF/CF/OF are packed in a 32-bit value in RFLAG_NZCV_LOC.
memcpy(&Packed_NZCV, &Frame->State.flags[X86State::RFLAG_NZCV_LOC], sizeof(Packed_NZCV));
}
uint32_t OF = (Packed_NZCV >> IR::OpDispatchBuilder::IndexNZCV(X86State::RFLAG_OF_RAW_LOC)) & 1;
uint32_t CF = (Packed_NZCV >> IR::OpDispatchBuilder::IndexNZCV(X86State::RFLAG_CF_RAW_LOC)) & 1;
uint32_t ZF = (Packed_NZCV >> IR::OpDispatchBuilder::IndexNZCV(X86State::RFLAG_ZF_RAW_LOC)) & 1;
@@ -258,13 +273,13 @@ namespace FEXCore::Context {
// PF calculation is deferred, calculate it now.
// Popcount the 8-bit flag and then extract the lower bit.
uint32_t PFByte = Frame->State.flags[X86State::RFLAG_PF_RAW_LOC];
uint32_t PFByte = Frame->State.pf_raw & 0xff;
uint32_t PF = std::popcount(PFByte ^ 1) & 1;
EFLAGS |= PF << X86State::RFLAG_PF_RAW_LOC;
// AF calculation is deferred, calculate it now.
// XOR with PF byte and extract bit 4.
uint32_t AF = ((Frame->State.flags[X86State::RFLAG_AF_RAW_LOC] ^ PFByte) & (1 << 4)) ? 1 : 0;
uint32_t AF = ((Frame->State.af_raw ^ PFByte) & (1 << 4)) ? 1 : 0;
EFLAGS |= AF << X86State::RFLAG_AF_RAW_LOC;
return EFLAGS;
@@ -284,11 +299,11 @@ namespace FEXCore::Context {
// AF stored in bit 4 in our internal representation. It is also
// XORed with byte 4 of the PF byte, but we write that as zero here so
// we don't need any special handling for that.
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? (1 << 4) : 0;
Frame->State.af_raw = (EFLAGS & (1U << i)) ? (1 << 4) : 0;
break;
case X86State::RFLAG_PF_RAW_LOC:
// PF is inverted in our internal representation.
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 0 : 1;
Frame->State.pf_raw = (EFLAGS & (1U << i)) ? 0 : 1;
break;
default:
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 1 : 0;
FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+5 -31
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@@ -212,6 +212,11 @@ DEF_OP(RmifNZCV) {
rmif(GetReg(Op->Src.ID()).X(), Op->Rotate, Op->Mask);
}
DEF_OP(AXFlag) {
LOGMAN_THROW_A_FMT(CTX->HostFeatures.SupportsFlagM2, "Unsupported flagm2 op");
axflag();
}
ARMEmitter::Condition MapSelectCC(IR::CondClassType Cond) {
switch (Cond.Val) {
case FEXCore::IR::COND_EQ: return ARMEmitter::Condition::CC_EQ;
@@ -1531,41 +1536,10 @@ DEF_OP(FCmp) {
auto Op = IROp->C<IR::IROp_FCmp>();
const auto EmitSubSize = Op->ElementSize == 8 ? ARMEmitter::ScalarRegSize::i64Bit : ARMEmitter::ScalarRegSize::i32Bit;
ARMEmitter::Register Dst = GetReg(Node);
ARMEmitter::VRegister Scalar1 = GetVReg(Op->Scalar1.ID());
ARMEmitter::VRegister Scalar2 = GetVReg(Op->Scalar2.ID());
fcmp(EmitSubSize, Scalar1, Scalar2);
bool set = false;
if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
LOGMAN_THROW_AA_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
// EQ or unordered
cset(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Condition::CC_EQ); // Z = 1
csinc(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::zr, ARMEmitter::Condition::CC_VC); // IF !V ? Z : 1
set = true;
}
if (Op->Flags & (1 << IR::FCMP_FLAG_LT)) {
// LT or unordered
cset(ARMEmitter::Size::i64Bit, TMP2, ARMEmitter::Condition::CC_LT);
if (!set) {
lsl(ARMEmitter::Size::i64Bit, Dst, TMP2, IR::FCMP_FLAG_LT);
set = true;
} else {
bfi(ARMEmitter::Size::i64Bit, Dst, TMP2, IR::FCMP_FLAG_LT, 1);
}
}
if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED)) {
cset(ARMEmitter::Size::i64Bit, TMP2, ARMEmitter::Condition::CC_VS);
if (!set) {
lsl(ARMEmitter::Size::i64Bit, Dst, TMP2, IR::FCMP_FLAG_UNORDERED);
set = true;
} else {
bfi(ARMEmitter::Size::i64Bit, Dst, TMP2, IR::FCMP_FLAG_UNORDERED, 1);
}
}
}
#undef DEF_OP
FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
+20 -3
View File
@@ -5,6 +5,7 @@ tags: backend|arm64
$end_info$
*/
#include "FEXCore/Core/X86Enums.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
@@ -295,7 +296,11 @@ DEF_OP(LoadRegisterSRA) {
const auto OpSize = IROp->Size;
if (Op->Class == IR::GPRClass) {
const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.gregs[0])) / Core::CPUState::GPR_REG_SIZE;
const auto regId =
Op->Offset == offsetof(Core::CpuStateFrame, State.pf_raw) ? (StaticRegisters.size() - 2) :
Op->Offset == offsetof(Core::CpuStateFrame, State.af_raw) ? (StaticRegisters.size() - 1) :
(Op->Offset - offsetof(Core::CpuStateFrame, State.gregs[0])) / Core::CPUState::GPR_REG_SIZE;
const auto regOffs = Op->Offset & 7;
LOGMAN_THROW_A_FMT(regId < StaticRegisters.size(), "out of range regId");
@@ -473,10 +478,14 @@ DEF_OP(StoreRegisterSRA) {
const auto OpSize = IROp->Size;
if (Op->Class == IR::GPRClass) {
const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
const auto regOffs = Op->Offset & 7;
LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
const auto regId =
Op->Offset == offsetof(Core::CpuStateFrame, State.pf_raw) ? (StaticRegisters.size() - 2) :
Op->Offset == offsetof(Core::CpuStateFrame, State.af_raw) ? (StaticRegisters.size() - 1) :
(Op->Offset - offsetof(Core::CpuStateFrame, State.gregs[0])) / Core::CPUState::GPR_REG_SIZE;
LOGMAN_THROW_A_FMT(regId < StaticRegisters.size(), "out of range regId");
const auto reg = StaticRegisters[regId];
const auto Src = GetReg(Op->Value.ID());
@@ -1047,12 +1056,20 @@ DEF_OP(LoadFlag) {
auto Op = IROp->C<IR::IROp_LoadFlag>();
auto Dst = GetReg(Node);
LOGMAN_THROW_A_FMT(Op->Flag != X86State::RFLAG_PF_RAW_LOC &&
Op->Flag != X86State::RFLAG_AF_RAW_LOC,
"PF/AF must be accessed as registers");
ldrb(Dst, STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
}
DEF_OP(StoreFlag) {
auto Op = IROp->C<IR::IROp_StoreFlag>();
LOGMAN_THROW_A_FMT(Op->Flag != X86State::RFLAG_PF_RAW_LOC &&
Op->Flag != X86State::RFLAG_AF_RAW_LOC,
"PF/AF must be accessed as registers");
strb(GetReg(Op->Value.ID()), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
}
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+4 -24
View File
@@ -1268,14 +1268,6 @@ void OpDispatchBuilder::TESTOp(OpcodeArgs) {
auto ALUOp = _And(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);
GenerateFlags_Logical(Op, ALUOp, Dest, Src);
flagsOp = SelectionFlag::AND;
flagsOpDest = ALUOp;
if (Size >= 4) {
flagsOpSize = Size;
} else {
flagsOpSize = 4; // assuming ZEXT semantics here
}
}
void OpDispatchBuilder::MOVSXDOp(OpcodeArgs) {
@@ -1325,26 +1317,14 @@ template<uint32_t SrcIndex>
void OpDispatchBuilder::CMPOp(OpcodeArgs) {
// CMP is an instruction that does a SUB between the sources
// Result isn't stored in result, only writes to flags
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags);
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
auto Size = GetDstSize(Op);
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, {.AllowUpperGarbage = Size >= 4});
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 4});
auto ALUOp = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);
OrderedNode *Result = ALUOp;
GenerateFlags_SUB(Op, Result, Dest, Src);
flagsOp = SelectionFlag::CMP;
if (Size >= 4) {
flagsOpSize = Size;
flagsOpDestSigned = flagsOpDest = Dest;
flagsOpSrcSigned = flagsOpSrc = Src;
} else {
flagsOpSize = 4;
flagsOpDestSigned = _Sbfe(OpSize::i64Bit, Size * 8, 0, flagsOpDest = Dest);
flagsOpSrcSigned = _Sbfe(OpSize::i64Bit, Size * 8, 0, flagsOpSrc = Src);
}
}
void OpDispatchBuilder::CQOOp(OpcodeArgs) {
@@ -3683,7 +3663,7 @@ void OpDispatchBuilder::INCOp(OpcodeArgs) {
Dest = _AtomicFetchAdd(OpSizeFromSrc(Op), OneConst, DestAddress);
} else {
Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 32});
}
Result = _Add(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, OneConst);
@@ -3714,7 +3694,7 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
DestAddress = AppendSegmentOffset(DestAddress, Op->Flags);
Dest = _AtomicFetchSub(OpSizeFromSrc(Op), OneConst, DestAddress);
} else {
Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 32});
}
Result = _Sub(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, OneConst);
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+83 -34
View File
@@ -89,7 +89,6 @@ public:
TYPE_RORI,
TYPE_ROL,
TYPE_ROLI,
TYPE_FCMP,
TYPE_BEXTR,
TYPE_BLSI,
TYPE_BLSMSK,
@@ -121,8 +120,6 @@ public:
}
void StartNewBlock() {
flagsOp = SelectionFlag::Nothing;
// If we loaded flags but didn't change them, invalidate the cached copy and move on.
// Changes get stored out by CalculateDeferredFlags.
CachedNZCV = nullptr;
@@ -954,13 +951,6 @@ protected:
}
private:
enum class SelectionFlag {
Nothing, // must rely on x86 flags
CMP, // flags were set by a CMP between flagsOpDest/flagsOpDestSigned and flagsOpSrc/flagsOpSrcSigned with flagsOpSize size
AND, // flags were set by an AND/TEST, flagsOpDest contains the resulting value of flagsOpSize size
FCMP, // flags were set by a ucomis* / comis*
};
struct JumpTargetInfo {
OrderedNode* BlockEntry;
bool HaveEmitted;
@@ -968,13 +958,6 @@ private:
FEXCore::Context::ContextImpl *CTX{};
SelectionFlag flagsOp{};
uint8_t flagsOpSize{};
OrderedNode* flagsOpDest{};
OrderedNode* flagsOpSrc{};
OrderedNode* flagsOpDestSigned{};
OrderedNode* flagsOpSrcSigned{};
constexpr static unsigned FullNZCVMask =
(1U << FEXCore::X86State::RFLAG_CF_RAW_LOC) |
(1U << FEXCore::X86State::RFLAG_ZF_RAW_LOC) |
@@ -1376,10 +1359,12 @@ private:
}
void SetRFLAG(OrderedNode *Value, unsigned BitOffset, unsigned ValueOffset = 0, bool MustMask = false) {
flagsOp = SelectionFlag::Nothing;
if (IsNZCV(BitOffset)) {
InsertNZCV(BitOffset, Value, ValueOffset, MustMask);
} else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) {
_StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
} else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) {
_StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
} else {
if (ValueOffset || MustMask)
Value = _Bfe(OpSize::i32Bit, 1, ValueOffset, Value);
@@ -1432,11 +1417,90 @@ private:
return _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(BitOffset, Invert),
_Constant(1), _Constant(0));
}
} else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) {
return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
} else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) {
return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
} else {
return _LoadFlag(BitOffset);
}
}
// Set SSE comparison flags based on the result set by Arm FCMP. This converts
// NZCV from the Arm representation to an eXternal representation that's
// totally not a euphemism for x86 or anything, nuh-uh.
void ConvertNZCVToSSE() {
if (CTX->HostFeatures.SupportsFlagM2) {
LOGMAN_THROW_A_FMT(!NZCVDirty, "only expected after fcmp");
// We need to set PF according to the unordered flag. We'd rather do this
// after axflag, since some impls fuse fcmp+axflag, so we want to do this
// after. We can recover "unordered" after axflag as (Z && !C), but
// there's no condition code for this so it would take 2 instructions
// instead of one, which seems worse than doing 1 op before and breaking
// the fusion.
//
// We set PF to unordered (V), but our PF representation is inverted so we
// actually set to !V. This is one instruction with the VC cond code.
OrderedNode *PFInvert =
_NZCVSelect(OpSize::i32Bit, CondClassType{COND_FNU}, _Constant(1), _Constant(0));
SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(PFInvert);
// For the rest, this one weird a64 instruction maps exactly to what x86
// needs. What a coincidence!
_AXFlag();
PossiblySetNZCVBits = ~0;
// It does assume we invert CF internally, which is still TODO for us. For
// now, add a cfinv to deal. Hopefully we delete this later.
CarryInvert();
} else {
OrderedNode *Z = GetRFLAG(FEXCore::X86State::RFLAG_ZF_RAW_LOC);
OrderedNode *C_inv = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC, true);
OrderedNode *V = GetRFLAG(FEXCore::X86State::RFLAG_OF_RAW_LOC);
// We want to zero SF/OF, and then set CF/ZF. Zeroing up front lets us do
// this all with shifted-or's on non-flagm platforms.
ZeroNZCV();
SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(_Or(OpSize::i32Bit, C_inv, V));
SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(_Or(OpSize::i32Bit, Z, V));
// Note that we store PF inverted.
// TODO: We could maybe optimize this xor out for non-flagm platforms with
// bfi/bfxil?
SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(_Xor(OpSize::i32Bit, V, _Constant(1)));
}
}
// Set x87 comparison flags based on the result set by Arm FCMP. Clobbers
// NZCV on flagm2 platforms.
void ConvertNZCVToX87() {
OrderedNode *V = GetRFLAG(FEXCore::X86State::RFLAG_OF_RAW_LOC);
if (CTX->HostFeatures.SupportsFlagM2) {
LOGMAN_THROW_A_FMT(!NZCVDirty, "only expected after fcmp");
// Convert to x86 flags, saves us from or'ing after.
_AXFlag();
PossiblySetNZCVBits = ~0;
// Copy the values. CF is inverted from the axflag result, ZF is as-is.
SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC, true));
SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(GetRFLAG(FEXCore::X86State::RFLAG_ZF_RAW_LOC));
} else {
OrderedNode *Z = GetRFLAG(FEXCore::X86State::RFLAG_ZF_RAW_LOC);
OrderedNode *N = GetRFLAG(FEXCore::X86State::RFLAG_SF_RAW_LOC);
SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(_Or(OpSize::i32Bit, N, V));
SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(_Or(OpSize::i32Bit, Z, V));
}
SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(V);
}
// Helper to derive Dest by a given builder-using Expression with the opcode
// replaced with NewOp. Useful for generic building code. Not safe in general.
// but does the right handling of ImplicitFlagClobber at least and must be
@@ -1668,7 +1732,6 @@ private:
void CalculateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
void CalculateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
void CalculateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
void CalculateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
void CalculateFlags_BEXTR(OrderedNode *Src);
void CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src);
void CalculateFlags_BLSMSK(OrderedNode *Src);
@@ -1979,20 +2042,6 @@ private:
};
}
void GenerateFlags_FCMP(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
CurrentDeferredFlags = DeferredFlagData {
.Type = FlagsGenerationType::TYPE_FCMP,
.SrcSize = GetSrcSize(Op),
.Res = Res,
.Sources = {
.TwoSource = {
.Src1 = Src1,
.Src2 = Src2,
},
}
};
}
void GenerateFlags_BEXTR(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
CurrentDeferredFlags = DeferredFlagData {
.Type = FlagsGenerationType::TYPE_BEXTR,
FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
+12 -43
View File
@@ -40,7 +40,6 @@ constexpr std::array<uint32_t, 17> FlagOffsets = {
};
void OpDispatchBuilder::ZeroMultipleFlags(uint32_t FlagsMask) {
flagsOp = SelectionFlag::Nothing;
auto ZeroConst = _Constant(0);
if (ContainsNZCV(FlagsMask)) {
@@ -240,12 +239,13 @@ void OpDispatchBuilder::CalculateOF(uint8_t SrcSize, OrderedNode *Res, OrderedNo
}
OrderedNode *OpDispatchBuilder::LoadPFRaw() {
// Read the stored byte. This is the original 8-bit result, it needs parity calculated.
auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
// Read the stored byte. This is the original result (up to 64-bits), it needs
// parity calculated.
auto Result = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
// Cast the input to a 32-bit FPR. Logically we only need 8-bit, but that would
// generate unwanted an ubfx instruction. VPopcount will ignore the upper bits anyway.
auto InputFPR = _VCastFromGPR(4, 4, PFByte);
auto InputFPR = _VCastFromGPR(4, 4, Result);
// Calculate the popcount.
auto Count = _VPopcount(1, 1, InputFPR);
@@ -253,14 +253,14 @@ OrderedNode *OpDispatchBuilder::LoadPFRaw() {
}
OrderedNode *OpDispatchBuilder::LoadAF() {
// Read the stored byte. This is the XOR of the arguments.
auto AFByte = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC);
// Read the stored value. This is the XOR of the arguments.
auto AFWord = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC);
// Read the result, stored as the PF byte for deferred PF calculation.
auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
// Read the result, stored for PF.
auto Result = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
// What's left is to XOR and extract. This is the deferred part.
return _Bfe(OpSize::i32Bit, 1, 4, _Xor(OpSize::i32Bit, AFByte, PFByte));
return _Bfe(OpSize::i32Bit, 1, 4, _Xor(OpSize::i32Bit, AFWord, Result));
}
void OpDispatchBuilder::FixupAF() {
@@ -270,10 +270,10 @@ void OpDispatchBuilder::FixupAF() {
//
// (AF[4] ^ PF[4]) ^ PF[4] = AF[4]
auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
auto AFByte = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC);
auto PFRaw = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
auto AFRaw = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC);
OrderedNode *XorRes = _Xor(OpSize::i32Bit, AFByte, PFByte);
OrderedNode *XorRes = _Xor(OpSize::i32Bit, AFRaw, PFRaw);
SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
}
@@ -435,13 +435,6 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
break;
case FlagsGenerationType::TYPE_FCMP:
CalculateFlags_FCMP(
CurrentDeferredFlags.SrcSize,
CurrentDeferredFlags.Res,
CurrentDeferredFlags.Sources.TwoSource.Src1,
CurrentDeferredFlags.Sources.TwoSource.Src2);
break;
case FlagsGenerationType::TYPE_BEXTR:
CalculateFlags_BEXTR(CurrentDeferredFlags.Res);
break;
@@ -977,30 +970,6 @@ void OpDispatchBuilder::CalculateFlags_RotateLeftImmediate(uint8_t SrcSize, Orde
}
}
void OpDispatchBuilder::CalculateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
OrderedNode *HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT);
OrderedNode *HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ);
OrderedNode *HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED);
SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(HostFlag_ZF);
// PF is stored inverted, so invert from the host flag.
// TODO: This could perhaps be optimized?
auto PF = _Xor(OpSize::i32Bit, HostFlag_Unordered, _Constant(1));
SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(PF);
// Zero AF. Note that we set the PF byte to 0/1 above, so PF[4] is 0 so the
// XOR with PF will have no effect, so setting the AF byte to zero will indeed
// zero AF as intended.
uint32_t FlagsMaskToZero =
(1U << X86State::RFLAG_AF_RAW_LOC) |
(1U << X86State::RFLAG_SF_RAW_LOC) |
(1U << X86State::RFLAG_OF_RAW_LOC);
ZeroMultipleFlags(FlagsMaskToZero);
}
void OpDispatchBuilder::CalculateFlags_BEXTR(OrderedNode *Src) {
auto Zero = _Constant(0);
auto One = _Constant(1);
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+10 -9
View File
@@ -3422,20 +3422,21 @@ void OpDispatchBuilder::VPALIGNROp(OpcodeArgs) {
template<size_t ElementSize>
void OpDispatchBuilder::UCOMISxOp(OpcodeArgs) {
InvalidateDeferredFlags();
const auto SrcSize = Op->Src[0].IsGPR() ? GetGuestVectorLength() : GetSrcSize(Op);
OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetGuestVectorLength(), Op->Flags);
OrderedNode *Src2 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags);
OrderedNode *Res = _FCmp(ElementSize, Src1, Src2,
(1 << FCMP_FLAG_EQ) |
(1 << FCMP_FLAG_LT) |
(1 << FCMP_FLAG_UNORDERED));
GenerateFlags_FCMP(Op, Res, Src1, Src2);
CachedNZCV = nullptr;
_FCmp(ElementSize, Src1, Src2);
PossiblySetNZCVBits = ~0;
ConvertNZCVToSSE();
flagsOp = SelectionFlag::FCMP;
flagsOpDest = Src1;
flagsOpSrc = Src2;
flagsOpSize = GetSrcSize(Op);
// Zero AF. Note that the comparison sets the raw PF to 0/1 above, so PF[4] is
// 0 so the XOR with PF will have no effect, so setting the AF byte to zero
// will indeed zero AF as intended.
SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(_Constant(0));
}
template
FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
+15 -37
View File
@@ -601,21 +601,13 @@ void OpDispatchBuilder::FTSTF64(OpcodeArgs) {
auto low = _Constant(0);
OrderedNode *data = _VCastFromGPR(8, 8, low);
OrderedNode *Res = _FCmp(8, a, data,
(1 << FCMP_FLAG_EQ) |
(1 << FCMP_FLAG_LT) |
(1 << FCMP_FLAG_UNORDERED));
// We are going to clobber NZCV, make sure it's in a GPR first.
GetNZCV();
OrderedNode *HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT);
OrderedNode *HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ);
OrderedNode *HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED);
HostFlag_CF = _Or(OpSize::i32Bit, HostFlag_CF, HostFlag_Unordered);
HostFlag_ZF = _Or(OpSize::i32Bit, HostFlag_ZF, HostFlag_Unordered);
SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(HostFlag_Unordered);
SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(HostFlag_ZF);
// Now we do our comparison.
_FCmp(8, a, data);
PossiblySetNZCVBits = ~0;
ConvertNZCVToX87();
}
//TODO: This should obey rounding mode
@@ -681,36 +673,22 @@ void OpDispatchBuilder::FCOMIF64(OpcodeArgs) {
auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass);
OrderedNode *Res = _FCmp(8, a, b,
(1 << FCMP_FLAG_EQ) |
(1 << FCMP_FLAG_LT) |
(1 << FCMP_FLAG_UNORDERED));
OrderedNode *HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT);
OrderedNode *HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ);
OrderedNode *HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED);
HostFlag_CF = _Or(OpSize::i32Bit, HostFlag_CF, HostFlag_Unordered);
HostFlag_ZF = _Or(OpSize::i32Bit, HostFlag_ZF, HostFlag_Unordered);
if constexpr (whichflags == FCOMIFlags::FLAGS_X87) {
SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(HostFlag_Unordered);
SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(HostFlag_ZF);
// We are going to clobber NZCV, make sure it's in a GPR first.
GetNZCV();
_FCmp(8, a, b);
PossiblySetNZCVBits = ~0;
ConvertNZCVToX87();
}
else {
// Invalidate deferred flags early
// OF, SF, AF, PF all undefined
InvalidateDeferredFlags();
SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(HostFlag_ZF);
// PF is stored inverted, so invert from the host flag.
// TODO: This could perhaps be optimized?
auto PF = _Xor(OpSize::i32Bit, HostFlag_Unordered, _Constant(1));
SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(PF);
_FCmp(8, a, b);
PossiblySetNZCVBits = ~0;
ConvertNZCVToSSE();
}
if constexpr (poptwice) {
FEXCore/Source/Interface/IR/IR.json
+8 -4
View File
@@ -964,6 +964,10 @@
"Desc": ["Invert carry flag in NZCV"],
"HasSideEffects": true
},
"AXFlag": {
"Desc": ["After an FCmp, converts NZCV flags from the Arm format to a mysterious eXternal format"],
"HasSideEffects": true
},
"RmifNZCV GPR:$Src, u8:$Rotate, u8:$Mask": {
"Desc": ["Rotate, mask, and insert into NZCV on FlagM platforms"],
"HasSideEffects": true
@@ -1347,12 +1351,12 @@
"DestSize": "DestElementSize"
},
"GPR = FCmp u8:$ElementSize, FPR:$Scalar1, FPR:$Scalar2, u32:$Flags": {
"Desc": ["Does a scalar unordered compare and stores the asked for flags in to a GPR",
"FCmp u8:$ElementSize, FPR:$Scalar1, FPR:$Scalar2": {
"Desc": ["Does a scalar unordered compare and sets NZCV accordingly.",
"NZCV follows Arm conventions, a separate AXFLAG instruction is required for x86",
"Ordering flag result is true if either float input is NaN"
],
"ImplicitFlagClobber": true,
"DestSize": "4"
"HasSideEffects": true
}
},
"VectorScalar": {
FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
-25
View File
@@ -194,7 +194,6 @@ public:
private:
bool HandleConstantPools(IREmitter *IREmit, const IRListView& CurrentIR);
void FCMPOptimization(IREmitter *IREmit, const IRListView& CurrentIR);
void LoadMemStoreMemImmediatePooling(IREmitter *IREmit, const IRListView& CurrentIR);
bool ZextAndMaskingElimination(IREmitter *IREmit, const IRListView& CurrentIR,
OrderedNode* CodeNode, IROp_Header* IROp);
@@ -266,29 +265,6 @@ bool ConstProp::HandleConstantPools(IREmitter *IREmit, const IRListView& Current
return Changed;
}
void ConstProp::FCMPOptimization(IREmitter *IREmit, const IRListView& CurrentIR) {
// Make all FCMPs set no flags
for (auto [CodeNode, IROp] : CurrentIR.GetAllCode()) {
if (IROp->Op == OP_FCMP) {
auto fcmp = IROp->CW<IR::IROp_FCmp>();
fcmp->Flags = 0;
}
}
// Set needed flags
for (auto [CodeNode, IROp] : CurrentIR.GetAllCode()) {
if (IROp->Op == OP_GETHOSTFLAG) {
auto ghf = IROp->CW<IR::IROp_GetHostFlag>();
auto fcmp = IREmit->GetOpHeader(ghf->Value)->CW<IR::IROp_FCmp>();
LOGMAN_THROW_AA_FMT(fcmp->Header.Op == OP_FCMP || fcmp->Header.Op == OP_F80CMP, "Unexpected OP_GETHOSTFLAG source");
if(fcmp->Header.Op == OP_FCMP) {
fcmp->Flags |= 1 << ghf->Flag;
}
}
}
}
// LoadMem / StoreMem imm pooling
// If imms are close by, use address gen to generate the values instead of using a new imm
void ConstProp::LoadMemStoreMemImmediatePooling(IREmitter *IREmit, const IRListView& CurrentIR) {
@@ -1261,7 +1237,6 @@ bool ConstProp::Run(IREmitter *IREmit) {
Changed = true;
}
FCMPOptimization(IREmit, CurrentIR);
LoadMemStoreMemImmediatePooling(IREmit, CurrentIR);
for (auto [CodeNode, IROp] : CurrentIR.GetAllCode()) {
FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp
+22
View File
@@ -277,6 +277,24 @@ namespace {
});
}
ContextClassification->emplace_back(ContextMemberInfo{
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, pf_raw),
sizeof(FEXCore::Core::CPUState::pf_raw),
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
ContextClassification->emplace_back(ContextMemberInfo{
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, af_raw),
sizeof(FEXCore::Core::CPUState::af_raw),
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo{
ContextMemberClassification {
@@ -419,6 +437,10 @@ namespace {
SetAccess(Offset++, LastAccessType::NONE);
}
// PF/AF
SetAccess(Offset++, LastAccessType::NONE);
SetAccess(Offset++, LastAccessType::NONE);
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+23 -4
View File
@@ -6,6 +6,7 @@ $end_info$
*/
#include "Interface/IR/Passes/RegisterAllocationPass.h"
#include "FEXCore/Core/X86Enums.h"
#include "Interface/IR/Passes.h"
#include <FEXCore/Core/CoreState.h>
#include <FEXCore/IR/IR.h>
@@ -518,12 +519,21 @@ namespace {
const auto GetRegAndClassFromOffset = [&, this](uint32_t Offset) {
const auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
const auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
const auto pf = offsetof(FEXCore::Core::CpuStateFrame, State.pf_raw);
const auto af = offsetof(FEXCore::Core::CpuStateFrame, State.af_raw);
const auto [beginFpr, endFpr] = GetFPRBeginAndEnd();
LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset);
LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr) || (Offset == pf) || (Offset == af), "Unexpected Offset {}", Offset);
if (Offset >= beginGpr && Offset < endGpr) {
unsigned FlagOffset =
Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount - 2;
if (Offset == pf) {
return PhysicalRegister(GPRFixedClass, FlagOffset);
} else if (Offset == af) {
return PhysicalRegister(GPRFixedClass, FlagOffset + 1);
} else if (Offset >= beginGpr && Offset < endGpr) {
auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE;
return PhysicalRegister(GPRFixedClass, reg);
} else if (Offset >= beginFpr && Offset < endFpr) {
@@ -544,12 +554,21 @@ namespace {
const auto GetStaticMapFromOffset = [&](uint32_t Offset) -> LiveRange** {
const auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
const auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
const auto pf = offsetof(FEXCore::Core::CpuStateFrame, State.pf_raw);
const auto af = offsetof(FEXCore::Core::CpuStateFrame, State.af_raw);
const auto [beginFpr, endFpr] = GetFPRBeginAndEnd();
LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset);
LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr) || (Offset == pf) || (Offset == af), "Unexpected Offset {}", Offset);
if (Offset >= beginGpr && Offset < endGpr) {
unsigned FlagOffset =
Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount - 2;
if (Offset == pf) {
return &StaticMaps[FlagOffset];
} else if (Offset == af) {
return &StaticMaps[FlagOffset + 1];
} else if (Offset >= beginGpr && Offset < endGpr) {
auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE;
return &StaticMaps[reg];
} else if (Offset >= beginFpr && Offset < endFpr) {
FEXCore/include/FEXCore/Core/Context.h
+14 -2
View File
@@ -270,8 +270,20 @@ namespace FEXCore::Context {
///< State reconstruction helpers
///< Reconstructs the guest RIP from the passed in thread context and related Host PC.
FEX_DEFAULT_VISIBILITY virtual uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) = 0;
///< Reconstructs a compacted EFLAGS from FEX's internal EFLAG representation.
FEX_DEFAULT_VISIBILITY virtual uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread) = 0;
/**
* @brief Reconstructs a compacted EFLAGS from FEX's internal EFLAG representation.
*
* @param Thread The thread getting the state reconstructed
* @param WasInJIT If the code was in the JIT at the time.
* @param HostGPRs The host Arm64 GPRs at the point of state inside the JIT.
* @param PSTATE The Arm64 PState value.
*
* If WasInJIT is false then HostGPRs and PSTATE is ignored, with the assumption that the FEX JIT has already stored all state in to the
* ThreadState object.
*
* @return x86 EFLAGS reconstructed
*/
FEX_DEFAULT_VISIBILITY virtual uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, bool WasInJIT, uint64_t *HostGPRs, uint64_t PSTATE) = 0;
///< Sets FEX's internal EFLAGS representation to the passed in compacted form.
FEX_DEFAULT_VISIBILITY virtual void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, uint32_t EFLAGS) = 0;
FEXCore/include/FEXCore/Core/CoreState.h
+2
View File
@@ -102,6 +102,8 @@ namespace FEXCore::Core {
uint64_t InlineJITBlockHeader{};
XMMRegs xmm{};
uint8_t flags[48]{};
uint64_t pf_raw{};
uint64_t af_raw{};
uint64_t mm[8][2]{};
// 32bit x86 state
FEXCore/unittests/Emitter/ALU_Tests.cpp
+6
View File
@@ -1712,6 +1712,12 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Evaluate into flags") {
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Carry flag invert") {
TEST_SINGLE(cfinv(), "cfinv");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Arm to eXternal FLAG") {
TEST_SINGLE(axflag(), "axflag");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: eXternal to Arm FLAG") {
TEST_SINGLE(xaflag(), "xaflag");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: Conditional compare - register") {
TEST_SINGLE(ccmn(Size::i32Bit, Reg::r29, Reg::r28, StatusFlags::None, Condition::CC_AL), "ccmn w29, w28, #nzcv, al");
TEST_SINGLE(ccmn(Size::i32Bit, Reg::r29, Reg::r28, StatusFlags::Flag_N, Condition::CC_AL), "ccmn w29, w28, #Nzcv, al");
Source/Tools/FEXLoader/ArchHelpers/MContext.h
+8
View File
@@ -143,6 +143,10 @@ static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
return GetMContext(ucontext)->regs[id];
}
static inline uint64_t GetArmPState(void* ucontext) {
return GetMContext(ucontext)->pstate;
}
static inline uint64_t *GetArmGPRs(void* ucontext) {
return reinterpret_cast<uint64_t*>(GetMContext(ucontext)->regs);
}
@@ -313,6 +317,10 @@ static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
ERROR_AND_DIE_FMT("Not implemented for x86 host");
}
static inline uint64_t GetArmPState(void* ucontext) {
ERROR_AND_DIE_FMT("Not implemented for x86 host");
}
static inline uint64_t *GetArmGPRs(void* ucontext) {
ERROR_AND_DIE_FMT("Not implemented for x86 host");
}
Source/Tools/FEXLoader/LinuxSyscalls/GdbServer.cpp
+2 -2
View File
@@ -306,7 +306,7 @@ fextl::string GdbServer::readRegs() {
memcpy(&GDB.gregs[0], &state.gregs[0], sizeof(GDB.gregs));
memcpy(&GDB.rip, &state.rip, sizeof(GDB.rip));
GDB.eflags = CTX->ReconstructCompactedEFLAGS(CurrentThread);
GDB.eflags = CTX->ReconstructCompactedEFLAGS(CurrentThread, false, nullptr, 0);
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
memcpy(&GDB.mm[i], &state.mm[i], sizeof(GDB.mm));
@@ -362,7 +362,7 @@ GdbServer::HandledPacketType GdbServer::readReg(const fextl::string& packet) {
return {encodeHex((unsigned char *)(&state.rip), sizeof(uint64_t)), HandledPacketType::TYPE_ACK};
}
else if (addr == offsetof(GDBContextDefinition, eflags)) {
uint32_t eflags = CTX->ReconstructCompactedEFLAGS(CurrentThread);
uint32_t eflags = CTX->ReconstructCompactedEFLAGS(CurrentThread, false, nullptr, 0);
return {encodeHex((unsigned char *)(&eflags), sizeof(uint32_t)), HandledPacketType::TYPE_ACK};
}
Source/Tools/FEXLoader/LinuxSyscalls/SignalDelegator.cpp
+3 -2
View File
@@ -1137,12 +1137,13 @@ namespace FEX::HLE {
++Thread->CurrentFrame->SignalHandlerRefCounter;
uint64_t OldPC = ArchHelpers::Context::GetPc(ucontext);
const bool WasInJIT = Thread->CPUBackend->IsAddressInCodeBuffer(OldPC);
// Spill the SRA regardless of signal handler type
// We are going to be returning to the top of the dispatcher which will fill again
// Otherwise we might load garbage
if (Config.StaticRegisterAllocation) {
if (Thread->CPUBackend->IsAddressInCodeBuffer(OldPC)) {
if (WasInJIT) {
uint32_t IgnoreMask{};
#ifdef _M_ARM_64
if (Frame->InSyscallInfo != 0) {
@@ -1207,7 +1208,7 @@ namespace FEX::HLE {
// Backup where we think the RIP currently is
ContextBackup->OriginalRIP = CTX->RestoreRIPFromHostPC(Thread, ArchHelpers::Context::GetPc(ucontext));
// Calculate eflags upfront.
uint32_t eflags = CTX->ReconstructCompactedEFLAGS(Thread);
uint32_t eflags = CTX->ReconstructCompactedEFLAGS(Thread, WasInJIT, ArchHelpers::Context::GetArmGPRs(ucontext), ArchHelpers::Context::GetArmPState(ucontext));
if (Is64BitMode) {
NewGuestSP = SetupFrame_x64(Thread, ContextBackup, Frame, Signal, HostSigInfo, ucontext, GuestAction, GuestStack, NewGuestSP, eflags);
Source/Windows/WOW64/Module.cpp
+1 -1
View File
@@ -179,7 +179,7 @@ namespace Context {
Context->Esp = State.gregs[FEXCore::X86State::REG_RSP];
Context->Eip = State.rip;
Context->EFlags = CTX->ReconstructCompactedEFLAGS(Thread);
Context->EFlags = CTX->ReconstructCompactedEFLAGS(Thread, false, nullptr, 0);
Context->SegEs = State.es_idx;
Context->SegCs = State.cs_idx;
unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+1 -1
View File
@@ -25,7 +25,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"scvtf v16.2s, v2.2s"
]
}
unittests/InstructionCountCI/AFP/Secondary.json
+1 -1
View File
@@ -26,7 +26,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"scvtf v16.2s, v2.2s"
]
}
unittests/InstructionCountCI/Atomics.json
+682 -862
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Crypto/H0F3A.json
+2 -2
View File
@@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/DDD.json
+63 -63
View File
@@ -20,11 +20,11 @@
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pi2fd mm0, mm1": {
@@ -33,9 +33,9 @@
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pf2iw mm0, mm1": {
@@ -44,11 +44,11 @@
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fcvtzs v2.2s, v2.2s",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pf2id mm0, mm1": {
@@ -57,9 +57,9 @@
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpv mm0, mm1": {
@@ -68,10 +68,10 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -80,57 +80,57 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v2.4s",
"fdiv v2.4s, v0.4s, v1.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"dup v4.2s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.4s, v3.4s, v3.4s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bif v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcp mm0, mm1": {
@@ -139,11 +139,11 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov s0, #0x70 (1.0000)",
"fdiv s2, s0, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrt mm0, mm1": {
@@ -152,61 +152,61 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s2",
"fdiv s2, s0, s1",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bit v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrcpit1 mm0, mm0": {
@@ -218,8 +218,8 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrsqit1 mm0, mm0": {
@@ -231,38 +231,38 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrcpit2 mm0, mm0": {
@@ -278,32 +278,32 @@
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"movi v3.4s, #0x80, lsl #8",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/FlagM/Atomics.json
+602 -790
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/H0F38.json
+3 -5
View File
@@ -12,7 +12,7 @@
},
"Instructions": {
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"0x66 0x0f 0x38 0x17"
],
@@ -25,16 +25,14 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/FlagM/HotBlocks.json
+101
View File
@@ -0,0 +1,101 @@
{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"FLAGM",
"FLAGM2"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256"
]
},
"Instructions": {
"Sonic Mania movie player": {
"ExpectedInstructionCount": 26,
"Comment": "Used to be hottest block in Sonic Mania",
"x86Insts": [
"movzx edx, byte [esi+ecx]",
"movzx ecx, byte [esi+edi]",
"or edx, 0xffff0000",
"shl edx, 0x8",
"inc esi",
"or edx, ecx",
"mov ecx, dword [ebp+0xc]",
"or dword [eax], edx",
"add eax, 0x4",
"cmp esi, ebx"
],
"ExpectedArm64ASM": [
"add x20, x5, x10",
"mov w20, w20",
"ldrb w6, [x20]",
"add x20, x11, x10",
"mov w20, w20",
"ldrb w5, [x20]",
"orr w6, w6, #0xffff0000",
"mov w20, w6",
"lsl w6, w20, #8",
"add w10, w10, #0x1 (1)",
"tst w6, w6",
"rmif x20, #23, #nzCv",
"mov x26, x6",
"orr w6, w6, w5",
"add x20, x9, #0xc (12)",
"mov w20, w20",
"ldr w5, [x20]",
"mov w20, w4",
"ldr w20, [x20]",
"orr w20, w20, w6",
"str w20, [x4]",
"add w4, w4, #0x4 (4)",
"sub w26, w10, w7",
"eor w27, w10, w7",
"cmp w10, w7",
"cfinv"
]
},
"wine mscrt.dll memmove": {
"ExpectedInstructionCount": 22,
"Comment": "Hot in Sonic Mania",
"x86Insts": [
"movdqu xmm0, [esi]",
"movdqu xmm1, [esi+0x10]",
"movdqu xmm2, [esi+0x20]",
"movdqu xmm3, [esi+0x30]",
"movdqa [edi], xmm0",
"movdqa [edi+0x10], xmm1",
"movdqa [edi+0x20], xmm2",
"movdqa [edi+0x30], xmm3",
"add esi, 0x40",
"add edi, 0x40",
"sub ecx, 0x40",
"cmp ecx, 0x40"
],
"ExpectedArm64ASM": [
"mov w20, w10",
"ldr q16, [x20]",
"add x20, x10, #0x10 (16)",
"mov w20, w20",
"ldr q17, [x20]",
"add x20, x10, #0x20 (32)",
"mov w20, w20",
"ldr q18, [x20]",
"add x20, x10, #0x30 (48)",
"mov w20, w20",
"ldr q19, [x20]",
"str q16, [x11]",
"str q17, [x11, #16]",
"str q18, [x11, #32]",
"str q19, [x11, #48]",
"add w10, w10, #0x40 (64)",
"add w11, w11, #0x40 (64)",
"sub w5, w5, #0x40 (64)",
"sub w26, w5, #0x40 (64)",
"mov x27, x5",
"cmp w5, #0x40 (64)",
"cfinv"
]
}
}
}
unittests/InstructionCountCI/FlagM/Primary.json
+891 -1121
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+544 -661
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/Secondary.json
+138 -214
View File
@@ -14,59 +14,25 @@
},
"Instructions": {
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"comiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"cmovo ax, bx": {
@@ -296,11 +262,10 @@
]
},
"cmovpe ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -311,11 +276,10 @@
]
},
"cmovpe eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -325,11 +289,10 @@
]
},
"cmovpe rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -339,11 +302,10 @@
]
},
"cmovnp ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -354,11 +316,10 @@
]
},
"cmovnp eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -368,11 +329,10 @@
]
},
"cmovnp rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -553,11 +513,10 @@
]
},
"setpe al": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mvn w20, w20",
@@ -566,11 +525,10 @@
]
},
"setnp al": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"and x20, x20, #0x1",
@@ -680,64 +638,60 @@
]
},
"shld ax, bx, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #1",
"lsr w20, w20, #15",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #14, #nzCv",
"strb w20, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w26, w21",
"rmif x20, #15, #nzcV"
]
},
"shld ax, bx, 15": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #15",
"lsr w20, w20, #1",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv"
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #16",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #63, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #31",
"lsr w20, w20, #17",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv"
]
},
"shld eax, ebx, 1": {
@@ -749,7 +703,7 @@
"extr w4, w21, w20, #31",
"tst w4, w4",
"rmif x21, #30, #nzCv",
"strb w4, [x28, #706]",
"mov x26, x4",
"eor w20, w4, w21",
"rmif x20, #31, #nzcV"
]
@@ -763,7 +717,7 @@
"extr w4, w21, w20, #17",
"tst w4, w4",
"rmif x21, #16, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld eax, ebx, 16": {
@@ -775,7 +729,7 @@
"extr w4, w21, w20, #16",
"tst w4, w4",
"rmif x21, #15, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld eax, ebx, 31": {
@@ -787,7 +741,7 @@
"extr w4, w21, w20, #1",
"tst w4, w4",
"rmif x21, #0, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 1": {
@@ -798,7 +752,7 @@
"extr x4, x20, x7, #63",
"tst x4, x4",
"rmif x20, #62, #nzCv",
"strb w4, [x28, #706]",
"mov x26, x4",
"eor x20, x4, x20",
"rmif x20, #63, #nzcV"
]
@@ -811,7 +765,7 @@
"extr x4, x20, x7, #49",
"tst x4, x4",
"rmif x20, #48, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 32": {
@@ -822,7 +776,7 @@
"extr x4, x20, x7, #32",
"tst x4, x4",
"rmif x20, #31, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 63": {
@@ -833,7 +787,7 @@
"extr x4, x20, x7, #1",
"tst x4, x4",
"rmif x20, #0, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld ax, bx, cl": {
@@ -861,7 +815,7 @@
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV"
]
@@ -891,7 +845,7 @@
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #31, #nzcV"
]
@@ -919,7 +873,7 @@
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"strb w22, [x28, #706]",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
]
@@ -1104,7 +1058,7 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -1116,20 +1070,18 @@
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #8",
"bfxil x4, x20, #0, #8",
"sub x20, x22, x23",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #24",
"rmif x20, #7, #nzCv",
"eor w21, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w21",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"cmpxchg [rax], bl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -1138,20 +1090,18 @@
"casalb w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #8",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1163,20 +1113,18 @@
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #16",
"bfxil x4, x20, #0, #16",
"sub x20, x22, x23",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"rmif x20, #15, #nzCv",
"eor w21, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w21",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"cmpxchg [rax], bx": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1185,20 +1133,18 @@
"casalh w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #16",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1212,10 +1158,8 @@
"cmp x24, x23",
"csel x4, x21, x22, eq",
"mov x4, x20",
"sub x20, x23, x24",
"eor w21, w23, w24",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"sub x26, x23, x24",
"eor w27, w23, w24",
"cmp w23, w24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1223,7 +1167,7 @@
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1233,10 +1177,8 @@
"mov w20, w1",
"cmp w20, w21",
"csel x4, x4, x20, eq",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmp w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1244,7 +1186,7 @@
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
@@ -1254,10 +1196,8 @@
"csel x22, x7, x20, eq",
"mov x4, x21",
"mov x4, x22",
"sub x22, x20, x21",
"eor x23, x20, x21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"sub x26, x20, x21",
"eor x27, x20, x21",
"cmp x20, x21",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1265,17 +1205,15 @@
]
},
"cmpxchg [rax], rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x1, x20",
"casal x1, x7, [x20]",
"mov x4, x1",
"sub x21, x20, x4",
"eor x22, x20, x4",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"sub x26, x20, x4",
"eor x27, x20, x4",
"cmp x20, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1644,134 +1582,120 @@
]
},
"xadd al, bl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w7",
"add w22, w20, w21",
"add w26, w20, w21",
"bfxil x7, x20, #0, #8",
"bfxil x4, x22, #0, #8",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"bfxil x4, x26, #0, #8",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w21, w20, w21",
"eor w20, w22, w20",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"xadd [rax], bl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"add w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"xadd ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"add w22, w20, w21",
"add w26, w20, w21",
"bfxil x7, x20, #0, #16",
"bfxil x4, x22, #0, #16",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"bfxil x4, x26, #0, #16",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w21, w20, w21",
"eor w20, w22, w20",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
"xadd [rax], bx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"add w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"xadd eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w7",
"add w4, w20, w21",
"mov x7, x20",
"eor w22, w20, w21",
"strb w22, [x28, #708]",
"strb w4, [x28, #706]",
"eor w27, w20, w21",
"mov x26, x4",
"cmn w20, w21"
]
},
"xadd [rax], ebx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"add w21, w7, w20",
"eor w22, w7, w20",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"add w26, w7, w20",
"eor w27, w7, w20",
"cmn w7, w20"
]
},
"xadd rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x7",
"add x4, x20, x21",
"mov x7, x20",
"eor x22, x20, x21",
"strb w22, [x28, #708]",
"strb w4, [x28, #706]",
"eor x27, x20, x21",
"mov x26, x4",
"cmn x20, x21"
]
},
"xadd [rax], rbx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x21, x7, x20",
"eor x22, x7, x20",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"add x26, x7, x20",
"eor x27, x7, x20",
"cmn x7, x20"
]
},
@@ -1779,7 +1703,7 @@
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"mov x20, #0x201",
"movk x20, #0x804, lsl #16",
"movk x20, #0x2010, lsl #32",
@@ -1797,9 +1721,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xf7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"cmlt v2.16b, v2.16b, #0",
"ldr d3, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d4, [x11]",
"bsl v2.8b, v3.8b, v4.8b",
"str d2, [x11]"
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+99 -111
View File
@@ -759,7 +759,7 @@
"mov w24, w2",
"mov w25, w3",
"mov w20, w24",
"mov w26, w25",
"mov w30, w25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -767,7 +767,7 @@
"rmif x22, #62, #nZcv",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"cmpxchg16b [rbp]": {
@@ -786,7 +786,7 @@
"mov x24, x2",
"mov x25, x3",
"mov x20, x24",
"mov x26, x25",
"mov x30, x25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -794,11 +794,11 @@
"rmif x22, #62, #nZcv",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -806,16 +806,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -823,32 +821,28 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -856,16 +850,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -873,26 +865,22 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
@@ -908,9 +896,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw mm0, 16": {
@@ -918,9 +906,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw xmm0, 0": {
@@ -956,9 +944,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, 16": {
@@ -966,9 +954,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw xmm0, 0": {
@@ -1004,9 +992,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, 16": {
@@ -1014,9 +1002,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw xmm0, 0": {
@@ -1052,9 +1040,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, 32": {
@@ -1062,9 +1050,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld xmm0, 0": {
@@ -1100,9 +1088,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, 32": {
@@ -1110,9 +1098,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad xmm0, 0": {
@@ -1148,9 +1136,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, 32": {
@@ -1158,9 +1146,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld xmm0, 0": {
@@ -1196,9 +1184,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, 64": {
@@ -1206,9 +1194,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq xmm0, 0": {
@@ -1267,9 +1255,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, 64": {
@@ -1277,9 +1265,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq xmm0, 0": {
@@ -1308,7 +1296,7 @@
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1008]",
"ldrh w20, [x28, #1024]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
@@ -1322,23 +1310,23 @@
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"ldrb w20, [x28, #1026]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #752]",
"str q2, [x4, #32]",
"ldr q2, [x28, #768]",
"str q2, [x4, #48]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"str q2, [x4, #64]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"str q2, [x4, #80]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"str q2, [x4, #96]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"str q2, [x4, #112]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"str q2, [x4, #128]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1387,7 +1375,7 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1008]",
"strh w20, [x28, #1024]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
@@ -1400,23 +1388,23 @@
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1010]",
"strb w20, [x28, #1026]",
"ldr q2, [x4, #32]",
"str q2, [x28, #752]",
"ldr q2, [x4, #48]",
"str q2, [x28, #768]",
"ldr q2, [x4, #64]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"ldr q2, [x4, #80]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"ldr q2, [x4, #96]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"ldr q2, [x4, #112]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"ldr q2, [x4, #128]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"ldr q2, [x4, #144]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1525,7 +1513,7 @@
"ubfx x22, x20, #0, #1",
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x28, #1008]",
"ldrh w22, [x28, #1024]",
"strh w22, [x21]",
"mov w22, #0x0",
"ldrb w23, [x28, #747]",
@@ -1533,29 +1521,29 @@
"ldrb w23, [x28, #744]",
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"ldrb w30, [x28, #750]",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"orr x22, x22, x30, lsl #14",
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"ldrb w22, [x28, #1026]",
"strb w22, [x21, #4]",
"ldr q2, [x28, #752]",
"str q2, [x21, #32]",
"ldr q2, [x28, #768]",
"str q2, [x21, #48]",
"str q2, [x21, #32]",
"ldr q2, [x28, #784]",
"str q2, [x21, #64]",
"str q2, [x21, #48]",
"ldr q2, [x28, #800]",
"str q2, [x21, #80]",
"str q2, [x21, #64]",
"ldr q2, [x28, #816]",
"str q2, [x21, #96]",
"str q2, [x21, #80]",
"ldr q2, [x28, #832]",
"str q2, [x21, #112]",
"str q2, [x21, #96]",
"ldr q2, [x28, #848]",
"str q2, [x21, #128]",
"str q2, [x21, #112]",
"ldr q2, [x28, #864]",
"str q2, [x21, #128]",
"ldr q2, [x28, #880]",
"str q2, [x21, #144]",
"ubfx x22, x20, #1, #1",
"cbnz x22, #+0x8",
@@ -1610,7 +1598,7 @@
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x20]",
"strh w22, [x28, #1008]",
"strh w22, [x28, #1024]",
"ldrh w22, [x20, #2]",
"ubfx w23, w22, #11, #3",
"strb w23, [x28, #747]",
@@ -1623,35 +1611,34 @@
"strb w25, [x28, #746]",
"strb w22, [x28, #750]",
"ldrb w22, [x20, #4]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"ldr q2, [x20, #32]",
"str q2, [x28, #752]",
"ldr q2, [x20, #48]",
"str q2, [x28, #768]",
"ldr q2, [x20, #64]",
"ldr q2, [x20, #48]",
"str q2, [x28, #784]",
"ldr q2, [x20, #80]",
"ldr q2, [x20, #64]",
"str q2, [x28, #800]",
"ldr q2, [x20, #96]",
"ldr q2, [x20, #80]",
"str q2, [x28, #816]",
"ldr q2, [x20, #112]",
"ldr q2, [x20, #96]",
"str q2, [x28, #832]",
"ldr q2, [x20, #128]",
"ldr q2, [x20, #112]",
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"ldr q2, [x20, #128]",
"str q2, [x28, #864]",
"ldr q2, [x20, #144]",
"str q2, [x28, #880]",
"b #+0x4c",
"mov w22, #0x0",
"mov w23, #0x37f",
"strh w23, [x28, #1008]",
"strh w23, [x28, #1024]",
"strb w22, [x28, #747]",
"strb w22, [x28, #744]",
"strb w22, [x28, #745]",
"strb w22, [x28, #746]",
"strb w22, [x28, #750]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"movi v2.2d, #0x0",
"str q2, [x28, #752]",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
@@ -1659,6 +1646,7 @@
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"ubfx x22, x21, #1, #1",
"cbnz x22, #+0x8",
"b #+0x48",
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+9 -5
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"xgetbv": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 54,
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xf0 (240)",
@@ -34,13 +34,15 @@
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"ldr x0, [x28, #1096]",
"ldr x2, [x28, #1112]",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"mov w1, w5",
"blr x2",
"ldr w4, [x28, #728]",
@@ -58,6 +60,8 @@
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@@ -81,7 +85,7 @@
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1040]",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -92,7 +96,7 @@
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1040]",
"str xzr, [x28, #1056]",
"orr x5, x0, x1, lsl #12"
]
}
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+10 -44
View File
@@ -13,59 +13,25 @@
},
"Instructions": {
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"pmovmskb eax, xmm0": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+13 -19
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"popcnt ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -23,18 +23,16 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -42,31 +40,27 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/FlagM/VEX_map1.json
+20 -88
View File
@@ -15,123 +15,55 @@
},
"Instructions": {
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
]
},
"vpmovmskb rax, xmm0": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+28 -40
View File
@@ -12,7 +12,7 @@
},
"Instructions": {
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0e 128-bit"
],
@@ -29,26 +29,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0e 256-bit"
],
@@ -73,26 +71,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0f 128-bit"
],
@@ -109,26 +105,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0f 256-bit"
],
@@ -153,26 +147,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"Map 2 0b01 0x16 128-bit"
],
@@ -185,21 +177,19 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Comment": [
"Map 2 0b01 0x16 256-bit"
],
@@ -220,16 +210,14 @@
"add v3.8h, v0.8h, v1.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -438,7 +426,7 @@
"mov w20, w7",
"mov w21, w5",
"bic w4, w21, w20",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst w4, w4"
]
},
@@ -449,7 +437,7 @@
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst x4, x4"
]
},
unittests/InstructionCountCI/FlagM/x87.json
+4935 -3753
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+2672 -3355
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/H0F38.json
+165 -153
View File
@@ -17,12 +17,12 @@
"NP 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"movi v4.16b, #0x87",
"and v3.16b, v3.16b, v4.16b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pshufb xmm0, xmm1": {
@@ -42,10 +42,10 @@
"NP 0x0f 0x38 0x01"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"addp v2.4h, v3.4h, v2.4h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddw xmm0, xmm1": {
@@ -63,10 +63,10 @@
"NP 0x0f 0x38 0x02"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"addp v2.2s, v3.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddd xmm0, xmm1": {
@@ -84,12 +84,12 @@
"NP 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqadd v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddsw xmm0, xmm1": {
@@ -109,15 +109,15 @@
"NP 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uxtl v2.8h, v2.8b",
"sxtl v3.8h, v3.8b",
"smull v4.4s, v2.4h, v3.4h",
"smull2 v2.4s, v2.8h, v3.8h",
"addp v2.4s, v4.4s, v2.4s",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pmaddubsw xmm0, xmm1": {
@@ -147,12 +147,12 @@
"NP 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubw xmm0, xmm1": {
@@ -172,12 +172,12 @@
"NP 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"sub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubd xmm0, xmm1": {
@@ -197,12 +197,12 @@
"NP 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqsub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubsw xmm0, xmm1": {
@@ -222,12 +222,12 @@
"NP 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.8b, v2.8b, #7",
"srshr v2.8b, v2.8b, #7",
"mul v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignb xmm0, xmm1": {
@@ -247,12 +247,12 @@
"NP 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.4h, v2.4h, #15",
"srshr v2.4h, v2.4h, #15",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignw xmm0, xmm1": {
@@ -272,12 +272,12 @@
"NP 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.2s, v2.2s, #31",
"srshr v2.2s, v2.2s, #31",
"mul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignd xmm0, xmm1": {
@@ -298,14 +298,14 @@
"NP 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pmulhrsw xmm0, xmm1": {
@@ -389,7 +389,7 @@
]
},
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"0x66 0x0f 0x38 0x17"
],
@@ -402,16 +402,14 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -421,9 +419,9 @@
"NP 0x0f 0x38 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsb xmm0, xmm1": {
@@ -441,9 +439,9 @@
"NP 0x0f 0x38 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsw xmm0, xmm1": {
@@ -461,9 +459,9 @@
"NP 0x0f 0x38 0x1e"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsd xmm0, xmm1": {
@@ -629,7 +627,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1952]",
"ldr q2, [x28, #1968]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -684,117 +682,131 @@
]
},
"sha256rnds2 xmm0, xmm1": {
"ExpectedInstructionCount": 106,
"ExpectedInstructionCount": 120,
"Comment": [
"0x66 0x0f 0x38 0xcb"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x120 (288)",
"sub sp, sp, #0x200 (512)",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"str w23, [sp]",
"mov w23, v17.s[1]",
"mov w24, v17.s[0]",
"str w20, [sp, #96]",
"mov w20, v17.s[2]",
"str w20, [sp, #64]",
"mov w20, v16.s[3]",
"mov w21, v16.s[2]",
"str w21, [sp]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"mov w22, v16.s[1]",
"mov w23, v16.s[0]",
"mov w24, v16.s[0]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"mov w27, v16.s[0]",
"mov w30, v16.s[1]",
"str w30, [sp, #32]",
"and w30, w23, w24",
"str w24, [sp, #64]",
"bic w24, w25, w23",
"str w25, [sp, #96]",
"eor w24, w30, w24",
"ror w25, w23, #6",
"ror w30, w23, #11",
"eor w25, w25, w30",
"ror w30, w23, #25",
"eor w25, w25, w30",
"add w24, w24, w25",
"add w24, w24, w27",
"add w24, w24, w26",
"and w25, w20, w21",
"and w30, w20, w22",
"eor w25, w25, w30",
"and w30, w21, w22",
"str w25, [sp, #128]",
"ldr w25, [sp, #32]",
"and w30, w25, w21",
"str w21, [sp, #160]",
"str w22, [sp, #128]",
"eor w21, w25, w30",
"add w21, w24, w21",
"ror w22, w20, #2",
"ror w24, w20, #13",
"eor w22, w22, w24",
"ror w24, w20, #22",
"eor w22, w22, w24",
"bic w21, w22, w25",
"str w22, [sp, #192]",
"eor w21, w30, w21",
"ror w22, w25, #6",
"ror w30, w25, #11",
"eor w22, w22, w30",
"ror w30, w25, #25",
"eor w22, w22, w30",
"add w21, w21, w22",
"str w21, [sp, #192]",
"ldr w21, [sp, #64]",
"and w22, w23, w21",
"ldr w24, [sp, #96]",
"bic w25, w24, w23",
"eor w22, w22, w25",
"ror w25, w23, #6",
"ror w30, w23, #11",
"eor w25, w25, w30",
"ror w30, w23, #25",
"eor w25, w25, w30",
"add w22, w22, w25",
"add w22, w22, w27",
"add w22, w22, w26",
"ldr w25, [sp]",
"add w22, w22, w25",
"and w25, w22, w23",
"bic w26, w21, w22",
"eor w25, w25, w26",
"ror w26, w22, #6",
"ror w27, w22, #11",
"eor w26, w26, w27",
"ror w27, w22, #25",
"eor w26, w26, w27",
"add w25, w25, w26",
"ldr w26, [sp, #32]",
"add w25, w25, w26",
"str w26, [sp, #256]",
"add w25, w25, w24",
"str w24, [sp, #224]",
"ldr w24, [sp, #192]",
"and w26, w24, w20",
"ldr w27, [sp, #160]",
"and w30, w24, w27",
"eor w26, w26, w30",
"and w20, w20, w27",
"eor w20, w26, w20",
"add w20, w25, w20",
"ror w25, w24, #2",
"ror w26, w24, #13",
"eor w25, w25, w26",
"ror w26, w24, #22",
"eor w25, w25, w26",
"add w20, w20, w25",
"and w23, w22, w23",
"bic w21, w21, w22",
"eor w21, w23, w21",
"ror w23, w22, #6",
"add w21, w21, w24",
"str w24, [sp, #256]",
"add w21, w21, w23",
"str w23, [sp, #224]",
"ldr w22, [sp, #64]",
"ldr w23, [sp, #96]",
"and w24, w23, w22",
"and w30, w23, w20",
"eor w24, w24, w30",
"and w30, w22, w20",
"str w22, [sp, #320]",
"str w20, [sp, #288]",
"eor w20, w24, w30",
"add w20, w21, w20",
"ror w21, w23, #2",
"ror w22, w23, #13",
"eor w21, w21, w22",
"ror w22, w23, #22",
"eor w21, w21, w22",
"add w20, w20, w21",
"str w20, [sp, #352]",
"ldr w20, [sp, #160]",
"and w21, w25, w20",
"ldr w22, [sp, #192]",
"bic w24, w22, w25",
"eor w21, w21, w24",
"ror w24, w25, #6",
"ror w30, w25, #11",
"eor w24, w24, w30",
"ror w30, w25, #25",
"eor w24, w24, w30",
"add w21, w21, w24",
"ldr w24, [sp, #256]",
"add w21, w21, w24",
"ldr w24, [sp, #224]",
"add w21, w21, w24",
"ldr w24, [sp]",
"add w21, w21, w24",
"and w24, w21, w25",
"bic w30, w20, w21",
"str w20, [sp, #384]",
"eor w20, w24, w30",
"ror w24, w21, #6",
"ror w30, w21, #11",
"eor w24, w24, w30",
"ror w30, w21, #25",
"str w21, [sp, #480]",
"eor w21, w24, w30",
"add w20, w20, w21",
"ldr w21, [sp, #128]",
"add w20, w20, w21",
"str w21, [sp, #448]",
"add w20, w20, w22",
"str w22, [sp, #416]",
"ldr w21, [sp, #352]",
"and w22, w21, w23",
"ldr w24, [sp, #320]",
"and w30, w21, w24",
"eor w22, w22, w30",
"and w23, w23, w24",
"eor w22, w22, w23",
"add w20, w20, w22",
"ror w22, w21, #2",
"ror w23, w21, #13",
"eor w22, w22, w23",
"ror w23, w21, #22",
"eor w22, w22, w23",
"add w20, w20, w22",
"ldr w22, [sp, #480]",
"and w23, w22, w25",
"ldr w24, [sp, #384]",
"bic w24, w24, w22",
"eor w23, w23, w24",
"ror w24, w22, #6",
"ror w25, w22, #11",
"eor w23, w23, w25",
"eor w24, w24, w25",
"ror w25, w22, #25",
"eor w23, w23, w25",
"add w21, w21, w23",
"ldr w23, [sp, #256]",
"add w21, w21, w23",
"ldr w23, [sp, #224]",
"add w21, w21, w23",
"ldr w23, [sp, #128]",
"add w21, w21, w23",
"eor w24, w24, w25",
"add w23, w23, w24",
"ldr w24, [sp, #448]",
"add w23, w23, w24",
"ldr w24, [sp, #416]",
"add w23, w23, w24",
"ldr w24, [sp, #288]",
"add w23, w23, w24",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v2.s[2], w21",
"mov v2.s[1], w23",
"mov v16.16b, v2.16b",
"mov v16.s[0], w22",
"add sp, sp, #0x120 (288)"
"add sp, sp, #0x200 (512)"
]
},
"sha256msg1 xmm0, xmm1": {
@@ -809,26 +821,26 @@
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"ror w25, w20, #7",
"ror w26, w20, #18",
"eor w25, w25, w26",
"ror w30, w20, #18",
"eor w25, w25, w30",
"lsr w20, w20, #3",
"eor w20, w25, w20",
"add w20, w21, w20",
"ror w25, w21, #7",
"ror w26, w21, #18",
"eor w25, w25, w26",
"ror w30, w21, #18",
"eor w25, w25, w30",
"lsr w21, w21, #3",
"eor w21, w25, w21",
"add w21, w22, w21",
"ror w25, w22, #7",
"ror w26, w22, #18",
"eor w25, w25, w26",
"ror w30, w22, #18",
"eor w25, w25, w30",
"lsr w22, w22, #3",
"eor w22, w25, w22",
"add w22, w23, w22",
"ror w25, w23, #7",
"ror w26, w23, #18",
"eor w25, w25, w26",
"ror w30, w23, #18",
"eor w25, w25, w30",
"lsr w23, w23, #3",
"eor w23, w25, w23",
"add w23, w24, w23",
unittests/InstructionCountCI/H0F3A.json
+238 -212
View File
@@ -20,8 +20,8 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 1": {
@@ -30,10 +30,10 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ext v2.8b, v2.8b, v3.8b, #1",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 255": {
@@ -43,7 +43,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"roundps xmm0, xmm1, 00000000b": {
@@ -315,7 +315,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2080]",
"ldr q2, [x28, #2096]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -325,7 +325,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2096]",
"ldr q2, [x28, #2112]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -344,7 +344,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2112]",
"ldr q2, [x28, #2128]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -364,7 +364,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2128]",
"ldr q2, [x28, #2144]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -383,7 +383,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2144]",
"ldr q2, [x28, #2160]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -393,7 +393,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -462,7 +462,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1704]",
"ldr x0, [x28, #1720]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
@@ -1338,271 +1338,297 @@
]
},
"sha1rnds4 xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 59,
"ExpectedInstructionCount": 65,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0x7999",
"movk w20, #0x5a82, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"and w27, w24, w25",
"bic w30, w26, w24",
"eor w27, w27, w30",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0x7999",
"movk w27, #0x5a82, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"and w27, w23, w24",
"bic w30, w25, w23",
"eor w27, w27, w30",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0x7999",
"movk w26, #0x5a82, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"and w27, w20, w23",
"bic w30, w24, w20",
"eor w27, w27, w30",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"bic w30, w24, w22",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"and w25, w21, w20",
"bic w23, w23, w21",
"eor w23, w25, w23",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"bic w30, w23, w21",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"bic w30, w22, w20",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w30, w24, w20",
"bic w21, w21, w24",
"eor w21, w30, w21",
"ror w30, w23, #27",
"add w21, w21, w30",
"ldr w30, [sp]",
"add w21, w21, w30",
"add w21, w21, w22",
"add w21, w21, w25",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xeba1",
"movk w20, #0x6ed9, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"eor w27, w24, w25",
"eor w27, w27, w26",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xeba1",
"movk w27, #0x6ed9, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"eor w27, w23, w24",
"eor w27, w27, w25",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xeba1",
"movk w26, #0x6ed9, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"eor w27, w20, w23",
"eor w27, w27, w24",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"eor w25, w21, w20",
"eor w23, w25, w23",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 67,
"ExpectedInstructionCount": 75,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xbcdc",
"movk w20, #0x8f1b, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"and w27, w24, w25",
"and w30, w24, w26",
"eor w27, w27, w30",
"and w30, w25, w26",
"eor w27, w27, w30",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xbcdc",
"movk w27, #0x8f1b, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"and w27, w23, w24",
"and w30, w23, w25",
"eor w27, w27, w30",
"and w30, w24, w25",
"eor w27, w27, w30",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xbcdc",
"movk w26, #0x8f1b, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"and w27, w20, w23",
"and w30, w20, w24",
"eor w27, w27, w30",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"and w30, w22, w24",
"eor w25, w25, w30",
"and w30, w23, w24",
"eor w27, w27, w30",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"and w25, w21, w20",
"and w27, w21, w23",
"eor w25, w25, w27",
"and w23, w20, w23",
"eor w23, w25, w23",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"and w30, w21, w23",
"eor w25, w25, w30",
"and w30, w22, w23",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"and w30, w20, w22",
"eor w25, w25, w30",
"and w30, w21, w22",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w25, w24, w20",
"and w30, w24, w21",
"eor w25, w25, w30",
"and w21, w20, w21",
"eor w21, w25, w21",
"ror w25, w23, #27",
"add w21, w21, w25",
"ldr w25, [sp]",
"add w21, w21, w25",
"add w21, w21, w22",
"mov w22, #0xbcdc",
"movk w22, #0x8f1b, lsl #16",
"add w21, w21, w22",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xc1d6",
"movk w20, #0xca62, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"eor w27, w24, w25",
"eor w27, w27, w26",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xc1d6",
"movk w27, #0xca62, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"eor w27, w23, w24",
"eor w27, w27, w25",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xc1d6",
"movk w26, #0xca62, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"eor w27, w20, w23",
"eor w27, w27, w24",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"eor w25, w21, w20",
"eor w23, w25, w23",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
}
}
unittests/InstructionCountCI/Primary.json
+1021 -1253
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+678 -787
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+109 -137
View File
@@ -27,7 +27,7 @@
"strh w20, [x28, #136]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #152]"
]
},
@@ -56,7 +56,7 @@
"strh w20, [x28, #140]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
]
},
@@ -77,18 +77,16 @@
"strh w20, [x28, #142]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #164]"
]
},
"daa": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 56,
"Comment": "0x27",
"ExpectedArm64ASM": [
"cset w20, hs",
"ldrb w21, [x28, #708]",
"ldrb w22, [x28, #706]",
"eor w21, w21, w22",
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"uxtb w22, w4",
"mrs x23, nzcv",
@@ -100,10 +98,9 @@
"cset x23, hi",
"orr x21, x21, x23",
"msr nzcv, x24",
"cbnz x21, #+0x10",
"mov w21, #0x0",
"strb w21, [x28, #708]",
"b #+0x30",
"cbnz x21, #+0xc",
"mov w27, #0x0",
"b #+0x2c",
"add x21, x22, #0x6 (6)",
"bfxil w4, w21, #0, #8",
"cset w21, hs",
@@ -112,8 +109,7 @@
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"mov w23, #0x10",
"strb w23, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x21",
"mrs x21, nzcv",
"cmp x22, #0x99 (153)",
@@ -131,33 +127,28 @@
"mrs x20, nzcv",
"orr w20, w20, #0x20000000",
"msr nzcv, x20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"mrs x22, nzcv",
"uxtb w26, w4",
"and x20, x26, #0x80",
"mrs x21, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, hs",
"mov w0, w21",
"bfi w0, w20, #31, #1",
"mov w20, w0",
"and x21, x26, #0xff",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"cset x21, eq",
"bfi w20, w21, #30, #1",
"eor w27, w27, w26",
"msr nzcv, x20"
]
},
"das": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 56,
"Comment": "0x2f",
"ExpectedArm64ASM": [
"cset w20, hs",
"ldrb w21, [x28, #708]",
"ldrb w22, [x28, #706]",
"eor w21, w21, w22",
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"uxtb w22, w4",
"mrs x23, nzcv",
@@ -169,10 +160,9 @@
"cset x23, hi",
"orr x21, x21, x23",
"msr nzcv, x24",
"cbnz x21, #+0x10",
"mov w21, #0x0",
"strb w21, [x28, #708]",
"b #+0x30",
"cbnz x21, #+0xc",
"mov w27, #0x0",
"b #+0x2c",
"sub x21, x22, #0x6 (6)",
"bfxil w4, w21, #0, #8",
"cset w21, hs",
@@ -181,8 +171,7 @@
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"mov w23, #0x10",
"strb w23, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x21",
"mrs x21, nzcv",
"cmp x22, #0x99 (153)",
@@ -200,32 +189,27 @@
"mrs x20, nzcv",
"orr w20, w20, #0x20000000",
"msr nzcv, x20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"mrs x22, nzcv",
"uxtb w26, w4",
"and x20, x26, #0x80",
"mrs x21, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, hs",
"mov w0, w21",
"bfi w0, w20, #31, #1",
"mov w20, w0",
"and x21, x26, #0xff",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"cset x21, eq",
"bfi w20, w21, #30, #1",
"eor w27, w27, w26",
"msr nzcv, x20"
]
},
"aaa": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 24,
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w27, w26",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -235,31 +219,27 @@
"cset x21, hi",
"orr x20, x20, x21",
"msr nzcv, x23",
"cbnz x20, #+0x20",
"cbnz x20, #+0x1c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"msr nzcv, x20",
"b #+0x24",
"mov w27, #0x0",
"msr nzcv, x27",
"b #+0x20",
"add x20, x22, #0x106 (262)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x20"
]
},
"aas": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 25,
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w27, w26",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -269,75 +249,70 @@
"cset x21, hi",
"orr x20, x20, x21",
"msr nzcv, x23",
"cbnz x20, #+0x20",
"cbnz x20, #+0x1c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"msr nzcv, x20",
"b #+0x28",
"mov w27, #0x0",
"msr nzcv, x27",
"b #+0x24",
"sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x20"
]
},
"inc ax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x40",
"ExpectedArm64ASM": [
"uxth w20, w4",
"add w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"cset w22, hs",
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"uxth w27, w4",
"add w26, w27, #0x1 (1)",
"bfxil w4, w26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w26, w27",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"inc eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"add w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"cset w21, hs",
"cmn w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w27, w4",
"add w4, w27, #0x1 (1)",
"mov w26, w4",
"cset w20, hs",
"cmn w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"dec ax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x48",
"ExpectedArm64ASM": [
"uxth w20, w4",
"sub w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"cset w22, hs",
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"uxth w27, w4",
"sub w26, w27, #0x1 (1)",
"bfxil w4, w26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w27, w26",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
@@ -356,17 +331,18 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"sub w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"cset w21, hs",
"cmp w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w27, w4",
"sub w4, w27, #0x1 (1)",
"mov w26, w4",
"cset w20, hs",
"cmp w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
@@ -443,7 +419,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0xd4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@@ -454,13 +430,12 @@
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"aad": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0xd5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@@ -471,13 +446,12 @@
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"aam with a different immediate byte base",
"0xd4"
@@ -491,13 +465,12 @@
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": [
"aad with a different immediate byte base",
"0xd5"
@@ -510,9 +483,8 @@
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"salc": {
unittests/InstructionCountCI/RPRES/DDD.json
+8 -8
View File
@@ -16,9 +16,9 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frecpe v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -27,9 +27,9 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frsqrte v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcp mm0, mm1": {
@@ -38,10 +38,10 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frecpe s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrt mm0, mm1": {
@@ -50,10 +50,10 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frsqrte s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/Secondary.json
+424 -484
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+99 -111
View File
@@ -825,7 +825,7 @@
"mov w24, w2",
"mov w25, w3",
"mov w20, w24",
"mov w26, w25",
"mov w30, w25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -833,7 +833,7 @@
"msr nzcv, x21",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"cmpxchg16b [rbp]": {
@@ -852,7 +852,7 @@
"mov x24, x2",
"mov x25, x3",
"mov x20, x24",
"mov x26, x25",
"mov x30, x25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -860,11 +860,11 @@
"msr nzcv, x21",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -872,16 +872,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -889,32 +887,28 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -922,16 +916,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -939,26 +931,22 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
@@ -974,9 +962,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw mm0, 16": {
@@ -984,9 +972,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw xmm0, 0": {
@@ -1022,9 +1010,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, 16": {
@@ -1032,9 +1020,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw xmm0, 0": {
@@ -1070,9 +1058,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, 16": {
@@ -1080,9 +1068,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw xmm0, 0": {
@@ -1118,9 +1106,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, 32": {
@@ -1128,9 +1116,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld xmm0, 0": {
@@ -1166,9 +1154,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, 32": {
@@ -1176,9 +1164,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad xmm0, 0": {
@@ -1214,9 +1202,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, 32": {
@@ -1224,9 +1212,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld xmm0, 0": {
@@ -1262,9 +1250,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, 64": {
@@ -1272,9 +1260,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq xmm0, 0": {
@@ -1333,9 +1321,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, 64": {
@@ -1343,9 +1331,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq xmm0, 0": {
@@ -1374,7 +1362,7 @@
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1008]",
"ldrh w20, [x28, #1024]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
@@ -1388,23 +1376,23 @@
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"ldrb w20, [x28, #1026]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #752]",
"str q2, [x4, #32]",
"ldr q2, [x28, #768]",
"str q2, [x4, #48]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"str q2, [x4, #64]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"str q2, [x4, #80]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"str q2, [x4, #96]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"str q2, [x4, #112]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"str q2, [x4, #128]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1453,7 +1441,7 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1008]",
"strh w20, [x28, #1024]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
@@ -1466,23 +1454,23 @@
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1010]",
"strb w20, [x28, #1026]",
"ldr q2, [x4, #32]",
"str q2, [x28, #752]",
"ldr q2, [x4, #48]",
"str q2, [x28, #768]",
"ldr q2, [x4, #64]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"ldr q2, [x4, #80]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"ldr q2, [x4, #96]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"ldr q2, [x4, #112]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"ldr q2, [x4, #128]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"ldr q2, [x4, #144]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1591,7 +1579,7 @@
"ubfx x22, x20, #0, #1",
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x28, #1008]",
"ldrh w22, [x28, #1024]",
"strh w22, [x21]",
"mov w22, #0x0",
"ldrb w23, [x28, #747]",
@@ -1599,29 +1587,29 @@
"ldrb w23, [x28, #744]",
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"ldrb w30, [x28, #750]",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"orr x22, x22, x30, lsl #14",
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"ldrb w22, [x28, #1026]",
"strb w22, [x21, #4]",
"ldr q2, [x28, #752]",
"str q2, [x21, #32]",
"ldr q2, [x28, #768]",
"str q2, [x21, #48]",
"str q2, [x21, #32]",
"ldr q2, [x28, #784]",
"str q2, [x21, #64]",
"str q2, [x21, #48]",
"ldr q2, [x28, #800]",
"str q2, [x21, #80]",
"str q2, [x21, #64]",
"ldr q2, [x28, #816]",
"str q2, [x21, #96]",
"str q2, [x21, #80]",
"ldr q2, [x28, #832]",
"str q2, [x21, #112]",
"str q2, [x21, #96]",
"ldr q2, [x28, #848]",
"str q2, [x21, #128]",
"str q2, [x21, #112]",
"ldr q2, [x28, #864]",
"str q2, [x21, #128]",
"ldr q2, [x28, #880]",
"str q2, [x21, #144]",
"ubfx x22, x20, #1, #1",
"cbnz x22, #+0x8",
@@ -1676,7 +1664,7 @@
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x20]",
"strh w22, [x28, #1008]",
"strh w22, [x28, #1024]",
"ldrh w22, [x20, #2]",
"ubfx w23, w22, #11, #3",
"strb w23, [x28, #747]",
@@ -1689,35 +1677,34 @@
"strb w25, [x28, #746]",
"strb w22, [x28, #750]",
"ldrb w22, [x20, #4]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"ldr q2, [x20, #32]",
"str q2, [x28, #752]",
"ldr q2, [x20, #48]",
"str q2, [x28, #768]",
"ldr q2, [x20, #64]",
"ldr q2, [x20, #48]",
"str q2, [x28, #784]",
"ldr q2, [x20, #80]",
"ldr q2, [x20, #64]",
"str q2, [x28, #800]",
"ldr q2, [x20, #96]",
"ldr q2, [x20, #80]",
"str q2, [x28, #816]",
"ldr q2, [x20, #112]",
"ldr q2, [x20, #96]",
"str q2, [x28, #832]",
"ldr q2, [x20, #128]",
"ldr q2, [x20, #112]",
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"ldr q2, [x20, #128]",
"str q2, [x28, #864]",
"ldr q2, [x20, #144]",
"str q2, [x28, #880]",
"b #+0x4c",
"mov w22, #0x0",
"mov w23, #0x37f",
"strh w23, [x28, #1008]",
"strh w23, [x28, #1024]",
"strb w22, [x28, #747]",
"strb w22, [x28, #744]",
"strb w22, [x28, #745]",
"strb w22, [x28, #746]",
"strb w22, [x28, #750]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"movi v2.2d, #0x0",
"str q2, [x28, #752]",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
@@ -1725,6 +1712,7 @@
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"ubfx x22, x21, #1, #1",
"cbnz x22, #+0x8",
"b #+0x48",
unittests/InstructionCountCI/SecondaryModRM.json
+9 -5
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"xgetbv": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 54,
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xf0 (240)",
@@ -34,13 +34,15 @@
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"ldr x0, [x28, #1096]",
"ldr x2, [x28, #1112]",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"mov w1, w5",
"blr x2",
"ldr w4, [x28, #728]",
@@ -58,6 +60,8 @@
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@@ -81,7 +85,7 @@
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1040]",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -92,7 +96,7 @@
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1040]",
"str xzr, [x28, #1056]",
"orr x5, x0, x1, lsl #12"
]
},
unittests/InstructionCountCI/Secondary_32Bit.json
+2 -2
View File
@@ -25,7 +25,7 @@
"strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
]
},
@@ -46,7 +46,7 @@
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
]
}
unittests/InstructionCountCI/Secondary_OpSize.json
+26 -44
View File
@@ -109,7 +109,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0x2a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
@@ -127,7 +127,7 @@
"ExpectedArm64ASM": [
"fcvtn v2.2s, v16.2d",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"cvtpd2pi mm0, xmm0": {
@@ -137,58 +137,40 @@
"fcvtn v2.2s, v16.2d",
"frinti v2.2s, v2.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@@ -540,7 +522,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1672]",
"ldr x0, [x28, #1688]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -554,7 +536,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #1672]",
"ldr x0, [x28, #1688]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -1032,7 +1014,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2016]",
"ldr q2, [x28, #2032]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
unittests/InstructionCountCI/Secondary_REP.json
+15 -21
View File
@@ -354,7 +354,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1664]",
"ldr x0, [x28, #1680]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -399,7 +399,7 @@
]
},
"popcnt ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -408,18 +408,16 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -427,31 +425,27 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
@@ -637,7 +631,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf3 0x0f 0xd6",
"ExpectedArm64ASM": [
"ldr d16, [x28, #752]"
"ldr d16, [x28, #768]"
]
},
"cvtdq2pd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+3 -3
View File
@@ -296,7 +296,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1656]",
"ldr x0, [x28, #1672]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -452,7 +452,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #1984]",
"ldr q2, [x28, #2000]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
@@ -461,7 +461,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf2 0x0f 0xd6",
"ExpectedArm64ASM": [
"str d16, [x28, #752]"
"str d16, [x28, #768]"
]
},
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_SVE128.json
+24 -24
View File
@@ -35,80 +35,80 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"asr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"asr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+47 -83
View File
@@ -2755,7 +2755,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2824,7 +2824,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2893,7 +2893,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -3307,114 +3307,78 @@
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 11,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp d16, d17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@@ -4374,7 +4338,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2016]",
"ldr q2, [x28, #2032]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@@ -4385,7 +4349,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1576]",
"ldr x0, [x28, #1592]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@@ -4397,7 +4361,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1984]",
"ldr q2, [x28, #2000]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@@ -4408,7 +4372,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1560]",
"ldr x0, [x28, #1576]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
unittests/InstructionCountCI/VEX_map2.json
+29 -41
View File
@@ -499,7 +499,7 @@
]
},
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0e 128-bit"
],
@@ -516,26 +516,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0e 256-bit"
],
@@ -560,26 +558,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0f 128-bit"
],
@@ -596,26 +592,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0f 256-bit"
],
@@ -640,21 +634,19 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -691,7 +683,7 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"Map 2 0b01 0x16 128-bit"
],
@@ -704,21 +696,19 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Comment": [
"Map 2 0b01 0x16 256-bit"
],
@@ -739,16 +729,14 @@
"add v3.8h, v0.8h, v1.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -1649,7 +1637,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1952]",
"ldr q2, [x28, #1968]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -3249,7 +3237,7 @@
"mov w20, w7",
"mov w21, w5",
"bic w4, w21, w20",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst w4, w4"
]
},
@@ -3260,7 +3248,7 @@
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst x4, x4"
]
},
unittests/InstructionCountCI/VEX_map3.json
+2 -2
View File
@@ -4799,7 +4799,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -4812,7 +4812,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/x87.json
+4935 -3753
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+2858 -3306
View File
File diff suppressed because it is too large. Load diff