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Merge pull request #3114 from lioncash/ins
Arm64/VectorOps: Improve handling of 128-bit vector VInsElement
This commit is contained in:
5 files changed
+133
-160
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@@ -2802,14 +2802,29 @@ DEF_OP(VInsElement) {
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ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
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if (Dst.Idx() != Reg.Idx()) {
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// If nothing aliases the destination, then we can just
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// move the DestVector over and directly insert.
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if (Dst != Reg && Dst != SrcVector) {
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mov(Dst.Q(), Reg.Q());
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ins(SubRegSize, Dst.Q(), DestIdx, SrcVector.Q(), SrcIdx);
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return;
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}
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// If our vector data to insert into is within a register
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// that aliases the destination, then we can avoid using a
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// temporary and just perform the insert.
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//
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// Otherwise, if the source vector to select from aliases
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// the destination, then we hit the worst case where we
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// need to use a temporary to avoid clobbering data.
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if (Dst != Reg) {
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mov(VTMP1.Q(), Reg.Q());
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Reg = VTMP1;
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}
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ins(SubRegSize, Reg.Q(), DestIdx, SrcVector.Q(), SrcIdx);
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if (Dst.Idx() != Reg.Idx()) {
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if (Dst != Reg) {
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mov(Dst.Q(), Reg.Q());
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}
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}
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@@ -328,48 +328,42 @@
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]
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},
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"blendps xmm0, xmm1, 0101b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[0], v17.s[0]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[2], v17.s[2]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[0], v17.s[0]",
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"mov v16.16b, v2.16b",
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"mov v16.s[2], v17.s[2]"
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]
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},
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"blendps xmm0, xmm1, 0110b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[1], v17.s[1]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[2], v17.s[2]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[1], v17.s[1]",
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"mov v16.16b, v2.16b",
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"mov v16.s[2], v17.s[2]"
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]
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},
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"blendps xmm0, xmm1, 0111b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.d[0], v17.d[0]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[2], v17.s[2]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.d[0], v17.d[0]",
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"mov v16.16b, v2.16b",
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"mov v16.s[2], v17.s[2]"
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]
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},
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"blendps xmm0, xmm1, 1000b": {
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@@ -383,48 +377,42 @@
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]
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},
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"blendps xmm0, xmm1, 1001b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[0], v17.s[0]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[3], v17.s[3]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[0], v17.s[0]",
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"mov v16.16b, v2.16b",
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"mov v16.s[3], v17.s[3]"
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]
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},
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"blendps xmm0, xmm1, 1010b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[1], v17.s[1]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[3], v17.s[3]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[1], v17.s[1]",
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"mov v16.16b, v2.16b",
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"mov v16.s[3], v17.s[3]"
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]
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},
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"blendps xmm0, xmm1, 1011b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.d[0], v17.d[0]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.s[3], v17.s[3]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.d[0], v17.d[0]",
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"mov v16.16b, v2.16b",
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"mov v16.s[3], v17.s[3]"
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]
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},
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"blendps xmm0, xmm1, 1100b": {
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@@ -438,33 +426,29 @@
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]
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},
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"blendps xmm0, xmm1, 1101b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[0], v17.s[0]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.d[1], v17.d[1]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[0], v17.s[0]",
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"mov v16.16b, v2.16b",
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"mov v16.d[1], v17.d[1]"
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]
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},
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"blendps xmm0, xmm1, 1110b": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 4,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.s[1], v17.s[1]",
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"mov v2.16b, v0.16b",
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"mov v0.16b, v2.16b",
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"mov v0.d[1], v17.d[1]",
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"mov v16.16b, v0.16b"
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"mov v2.16b, v16.16b",
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"mov v2.s[1], v17.s[1]",
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"mov v16.16b, v2.16b",
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"mov v16.d[1], v17.d[1]"
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]
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},
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"blendps xmm0, xmm1, 1111b": {
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@@ -537,24 +521,22 @@
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]
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},
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"pblendw xmm0, xmm1, 11111111b": {
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"ExpectedInstructionCount": 12,
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"ExpectedInstructionCount": 10,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x0e"
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],
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"ExpectedArm64ASM": [
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"mov v0.16b, v16.16b",
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"mov v0.h[0], v17.h[0]",
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"mov v2.16b, v0.16b",
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"mov v2.16b, v16.16b",
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"mov v2.h[0], v17.h[0]",
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"mov v2.h[1], v17.h[1]",
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"mov v2.h[2], v17.h[2]",
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"mov v2.h[3], v17.h[3]",
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"mov v2.h[4], v17.h[4]",
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"mov v2.h[5], v17.h[5]",
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"mov v2.h[6], v17.h[6]",
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"mov v0.16b, v2.16b",
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"mov v0.h[7], v17.h[7]",
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"mov v16.16b, v0.16b"
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"mov v16.16b, v2.16b",
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"mov v16.h[7], v17.h[7]"
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]
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},
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"palignr xmm0, xmm1, 0": {
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@@ -968,7 +950,7 @@
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]
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},
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"dpps xmm0, xmm1, 00001111b": {
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"ExpectedInstructionCount": 14,
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"ExpectedInstructionCount": 13,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x40"
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@@ -985,9 +967,8 @@
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"mov v2.s[0], v3.s[0]",
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"mov v2.s[1], v3.s[0]",
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"mov v2.s[2], v3.s[0]",
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"mov v0.16b, v2.16b",
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"mov v0.s[3], v3.s[0]",
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"mov v16.16b, v0.16b"
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"mov v16.16b, v2.16b",
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"mov v16.s[3], v3.s[0]"
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]
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},
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"dpps xmm0, xmm1, 11110000b": {
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@@ -1001,7 +982,7 @@
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]
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},
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"dpps xmm0, xmm1, 11111111b": {
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"ExpectedInstructionCount": 10,
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"ExpectedInstructionCount": 9,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x40"
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@@ -1014,9 +995,8 @@
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"mov v2.s[0], v3.s[0]",
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"mov v2.s[1], v3.s[0]",
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"mov v2.s[2], v3.s[0]",
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"mov v0.16b, v2.16b",
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"mov v0.s[3], v3.s[0]",
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"mov v16.16b, v0.16b"
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"mov v16.16b, v2.16b",
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"mov v16.s[3], v3.s[0]"
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]
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},
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"dppd xmm0, xmm1, 00000000b": {
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@@ -1030,7 +1010,7 @@
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]
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},
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"dppd xmm0, xmm1, 00001111b": {
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"ExpectedInstructionCount": 9,
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"ExpectedInstructionCount": 8,
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"Optimal": "No",
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"Comment": [
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"0x66 0x0f 0x3a 0x41"
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@@ -1042,9 +1022,8 @@
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"mov v3.d[1], v2.d[0]",
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"faddp v3.2d, v3.2d, v2.2d",
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"mov v2.d[0], v3.d[0]",
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"mov v0.16b, v2.16b",
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"mov v0.d[1], v3.d[0]",
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"mov v16.16b, v0.16b"
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"mov v16.16b, v2.16b",
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"mov v16.d[1], v3.d[0]"
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]
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},
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"dppd xmm0, xmm1, 11110000b": {
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@@ -1058,7 +1037,7 @@
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]
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},
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"dppd xmm0, xmm1, 11111111b": {
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"ExpectedInstructionCount": 7,
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"ExpectedInstructionCount": 6,
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"Optimal": "No",
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||||
"Comment": [
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"0x66 0x0f 0x3a 0x41"
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@@ -1068,9 +1047,8 @@
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"fmul v3.2d, v16.2d, v17.2d",
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"faddp v3.2d, v3.2d, v2.2d",
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"mov v2.d[0], v3.d[0]",
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"mov v0.16b, v2.16b",
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"mov v0.d[1], v3.d[0]",
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"mov v16.16b, v0.16b"
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"mov v16.16b, v2.16b",
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"mov v16.d[1], v3.d[0]"
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]
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},
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"mpsadbw xmm0, xmm1, 000b": {
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@@ -3904,7 +3904,7 @@
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]
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},
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"shufps xmm0, xmm1, 01000111b": {
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"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
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||||
"Optimal": "No",
|
||||
"Comment": [
|
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"odd elements inverted, Low 64-bits inserted",
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@@ -3913,14 +3913,13 @@
|
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"0x0f 0xc6"
|
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],
|
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"ExpectedArm64ASM": [
|
||||
"mov v0.16b, v16.16b",
|
||||
"mov v0.s[0], v16.s[3]",
|
||||
"mov v2.16b, v0.16b",
|
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"mov v2.16b, v16.16b",
|
||||
"mov v2.s[0], v16.s[3]",
|
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"zip1 v16.2d, v2.2d, v17.2d"
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]
|
||||
},
|
||||
"shufps xmm0, xmm1, 11100111b": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"odd elements inverted, Top 64-bits inserted",
|
||||
@@ -3929,16 +3928,14 @@
|
||||
"0x0f 0xc6"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov v0.16b, v16.16b",
|
||||
"mov v0.s[0], v16.s[3]",
|
||||
"mov v2.16b, v0.16b",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.d[1], v17.d[1]",
|
||||
"mov v16.16b, v0.16b"
|
||||
"mov v2.16b, v16.16b",
|
||||
"mov v2.s[0], v16.s[3]",
|
||||
"mov v16.16b, v2.16b",
|
||||
"mov v16.d[1], v17.d[1]"
|
||||
]
|
||||
},
|
||||
"shufps xmm0, xmm1, 11100001b": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Optimal": "Yes",
|
||||
"Comment": [
|
||||
"Lower 32-bit elements inverted, Top 64-bits inserted",
|
||||
@@ -3946,9 +3943,8 @@
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"rev64 v2.4s, v16.4s",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.d[1], v17.d[1]",
|
||||
"mov v16.16b, v0.16b"
|
||||
"mov v16.16b, v2.16b",
|
||||
"mov v16.d[1], v17.d[1]"
|
||||
]
|
||||
},
|
||||
"shufps xmm0, xmm1, 01000001b": {
|
||||
|
||||
@@ -1355,16 +1355,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufd xmm0, xmm1, 00b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.s[0], v2.s[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.s[0], v2.s[0]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1375,16 +1374,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufd xmm0, xmm1, 01b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.s[0], v2.s[1]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.s[0], v2.s[1]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1395,16 +1393,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufd xmm0, xmm1, 10b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.s[0], v2.s[2]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.s[0], v2.s[2]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1415,16 +1412,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufd xmm0, xmm1, 11b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.s[0], v2.s[3]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.s[0], v2.s[3]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1615,16 +1611,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufhw xmm0, xmm1, 00b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[4], v2.h[4]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[4], v2.h[4]",
|
||||
"mov v3.h[5], v2.h[4]",
|
||||
"mov v3.h[6], v2.h[4]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1635,16 +1630,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufhw xmm0, xmm1, 01b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[4], v2.h[5]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[4], v2.h[5]",
|
||||
"mov v3.h[5], v2.h[4]",
|
||||
"mov v3.h[6], v2.h[4]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1655,16 +1649,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufhw xmm0, xmm1, 10b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[4], v2.h[6]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[4], v2.h[6]",
|
||||
"mov v3.h[5], v2.h[4]",
|
||||
"mov v3.h[6], v2.h[4]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1675,16 +1668,15 @@
|
||||
]
|
||||
},
|
||||
"vpshufhw xmm0, xmm1, 11b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[4], v2.h[7]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[4], v2.h[7]",
|
||||
"mov v3.h[5], v2.h[4]",
|
||||
"mov v3.h[6], v2.h[4]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1875,16 +1867,15 @@
|
||||
]
|
||||
},
|
||||
"vpshuflw xmm0, xmm1, 00b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[0], v2.h[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[0], v2.h[0]",
|
||||
"mov v3.h[1], v2.h[0]",
|
||||
"mov v3.h[2], v2.h[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1895,16 +1886,15 @@
|
||||
]
|
||||
},
|
||||
"vpshuflw xmm0, xmm1, 01b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[0], v2.h[1]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[0], v2.h[1]",
|
||||
"mov v3.h[1], v2.h[0]",
|
||||
"mov v3.h[2], v2.h[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1915,16 +1905,15 @@
|
||||
]
|
||||
},
|
||||
"vpshuflw xmm0, xmm1, 10b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[0], v2.h[2]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[0], v2.h[2]",
|
||||
"mov v3.h[1], v2.h[0]",
|
||||
"mov v3.h[2], v2.h[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -1935,16 +1924,15 @@
|
||||
]
|
||||
},
|
||||
"vpshuflw xmm0, xmm1, 11b": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x70 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov z2.d, p7/m, z17.d",
|
||||
"mov v0.16b, v2.16b",
|
||||
"mov v0.h[0], v2.h[3]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v2.16b",
|
||||
"mov v3.h[0], v2.h[3]",
|
||||
"mov v3.h[1], v2.h[0]",
|
||||
"mov v3.h[2], v2.h[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
|
||||
@@ -3624,7 +3624,7 @@
|
||||
]
|
||||
},
|
||||
"vdpps xmm0, xmm1, xmm2, 00001111b": {
|
||||
"ExpectedInstructionCount": 20,
|
||||
"ExpectedInstructionCount": 19,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 3 0b01 0x40 128-bit"
|
||||
@@ -3640,9 +3640,8 @@
|
||||
"mov v2.s[3], v4.s[0]",
|
||||
"faddp v2.4s, v2.4s, v4.4s",
|
||||
"faddp v2.4s, v2.4s, v4.4s",
|
||||
"mov v0.16b, v4.16b",
|
||||
"mov v0.s[0], v2.s[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v4.16b",
|
||||
"mov v3.s[0], v2.s[0]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -3665,7 +3664,7 @@
|
||||
]
|
||||
},
|
||||
"vdpps xmm0, xmm1, xmm2, 11111111b": {
|
||||
"ExpectedInstructionCount": 16,
|
||||
"ExpectedInstructionCount": 15,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 3 0b01 0x40 128-bit"
|
||||
@@ -3677,9 +3676,8 @@
|
||||
"fmul v2.4s, v2.4s, v3.4s",
|
||||
"faddp v2.4s, v2.4s, v4.4s",
|
||||
"faddp v2.4s, v2.4s, v4.4s",
|
||||
"mov v0.16b, v4.16b",
|
||||
"mov v0.s[0], v2.s[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v4.16b",
|
||||
"mov v3.s[0], v2.s[0]",
|
||||
"mov v3.s[1], v2.s[0]",
|
||||
"mov v3.s[2], v2.s[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
@@ -3872,7 +3870,7 @@
|
||||
]
|
||||
},
|
||||
"vdppd xmm0, xmm1, xmm2, 00001111b": {
|
||||
"ExpectedInstructionCount": 15,
|
||||
"ExpectedInstructionCount": 14,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 3 0b01 0x41 128-bit"
|
||||
@@ -3885,9 +3883,8 @@
|
||||
"mov v2.d[0], v4.d[0]",
|
||||
"mov v2.d[1], v4.d[0]",
|
||||
"faddp v2.2d, v2.2d, v4.2d",
|
||||
"mov v0.16b, v4.16b",
|
||||
"mov v0.d[0], v2.d[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v4.16b",
|
||||
"mov v3.d[0], v2.d[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
"mov v0.d[1], v2.d[0]",
|
||||
"mov v2.16b, v0.16b",
|
||||
@@ -3908,7 +3905,7 @@
|
||||
]
|
||||
},
|
||||
"vdppd xmm0, xmm1, xmm2, 11111111b": {
|
||||
"ExpectedInstructionCount": 13,
|
||||
"ExpectedInstructionCount": 12,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"Map 3 0b01 0x41 128-bit"
|
||||
@@ -3919,9 +3916,8 @@
|
||||
"movi v4.2d, #0x0",
|
||||
"fmul v2.2d, v2.2d, v3.2d",
|
||||
"faddp v2.2d, v2.2d, v4.2d",
|
||||
"mov v0.16b, v4.16b",
|
||||
"mov v0.d[0], v2.d[0]",
|
||||
"mov v3.16b, v0.16b",
|
||||
"mov v3.16b, v4.16b",
|
||||
"mov v3.d[0], v2.d[0]",
|
||||
"mov v0.16b, v3.16b",
|
||||
"mov v0.d[1], v2.d[0]",
|
||||
"mov v2.16b, v0.16b",
|
||||
|
||||
Reference in new issue
Block a user