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Merge pull request #3079 from Sonicadvance1/recover_two_temps

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Arm64: Recover two unused vector vector temporary registers
This commit is contained in:
Mai authored and GitHub committed 2023-09-11 22:06:03 -04:00
2 parents 98f148766d 9c44e295fa
commit 90f7937146
22 files changed
+11360 -10692
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FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+43 -11
View File
@@ -66,11 +66,11 @@ namespace x64 {
};
// v8..v15 = (lower 64bits) Callee saved
constexpr std::array<FEXCore::ARMEmitter::VRegister, 12> RAFPR = {
// v0 ~ v3 are used as temps.
constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> RAFPR = {
// v0 ~ v1 are used as temps.
// FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
// FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
@@ -127,11 +127,11 @@ namespace x32 {
};
// v8..v15 = (lower 64bits) Callee saved
constexpr std::array<FEXCore::ARMEmitter::VRegister, 20> RAFPR = {
// v0 ~ v3 are used as temps.
constexpr std::array<FEXCore::ARMEmitter::VRegister, 22> RAFPR = {
// v0 ~ v1 are used as temps.
// FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
// FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
@@ -545,8 +545,19 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
// rsp capable move
add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);
LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 2 == 0, "Needs to have multiple of 2 FPRs for RA");
if (CanUseSVE) {
for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
size_t i = 0;
for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0);
add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2);
}
for (; i < GeneralFPRegisters.size(); i += 4) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -555,8 +566,14 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
}
} else {
LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 4 == 0, "Needs to have multiple of 4 FPRs for RA");
for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
size_t i = 0;
for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), TmpReg, 32);
}
for (; i < GeneralFPRegisters.size(); i += 4) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -578,7 +595,15 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
if (CanUseSVE) {
for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
size_t i = 0;
for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2);
}
for (; i < GeneralFPRegisters.size(); i += 4) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -587,7 +612,14 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
}
} else {
for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
size_t i = 0;
for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32);
}
for (; i < GeneralFPRegisters.size(); i += 4) {
const auto Reg1 = GeneralFPRegisters[i];
const auto Reg2 = GeneralFPRegisters[i + 1];
const auto Reg3 = GeneralFPRegisters[i + 2];
FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
-2
View File
@@ -42,8 +42,6 @@ constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
// Vector temporaries
constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
constexpr auto VTMP3 = FEXCore::ARMEmitter::VReg::v2;
constexpr auto VTMP4 = FEXCore::ARMEmitter::VReg::v3;
// Predicate register temporaries (used when AVX support is enabled)
// PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
unittests/InstructionCountCI/DDD.json
+109 -109
View File
@@ -23,11 +23,11 @@
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"mov v4.h[1], v4.h[2]",
"sxtl v4.4s, v4.4h",
"scvtf v4.2s, v4.2s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"mov v2.h[1], v2.h[2]",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"pi2fd mm0, mm1": {
@@ -39,9 +39,9 @@
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"scvtf v4.2s, v4.2s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"pf2iw mm0, mm1": {
@@ -54,11 +54,11 @@
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fcvtzs v4.2s, v4.2s",
"mov v4.h[1], v4.h[2]",
"sxtl v4.4s, v4.4h",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"fcvtzs v2.2s, v2.2s",
"mov v2.h[1], v2.h[2]",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #752]"
]
},
"pf2id mm0, mm1": {
@@ -70,9 +70,9 @@
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fcvtzs v4.2s, v4.2s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"pfrcpv mm0, mm1": {
@@ -83,10 +83,10 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d2, [x28, #768]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v4.4s, v0.4s, v4.4s",
"str d4, [x28, #752]"
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -97,11 +97,11 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d2, [x28, #768]",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v4.4s",
"fdiv v4.4s, v0.4s, v1.4s",
"str d4, [x28, #752]"
"fsqrt v1.4s, v2.4s",
"fdiv v2.4s, v0.4s, v1.4s",
"str d2, [x28, #752]"
]
},
"pfnacc mm0, mm1": {
@@ -109,12 +109,12 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uzp1 v6.2s, v4.2s, v5.2s",
"uzp2 v4.2s, v4.2s, v5.2s",
"fsub v4.4s, v6.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfpnacc mm0, mm1": {
@@ -122,13 +122,13 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"dup v6.4s, v4.s[1]",
"fsub s4, s4, s6",
"faddp v5.4s, v5.4s, v5.4s",
"mov v4.s[1], v5.s[0]",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"dup v4.4s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.4s, v3.4s, v3.4s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #752]"
]
},
"pfcmpge mm0, mm1": {
@@ -136,10 +136,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmge v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfmin mm0, mm1": {
@@ -147,11 +147,11 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v0.4s, v5.4s, v4.4s",
"bif v4.16b, v5.16b, v0.16b",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bif v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
]
},
"pfrcp mm0, mm1": {
@@ -162,11 +162,11 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d2, [x28, #768]",
"fmov s0, #0x70 (1.0000)",
"fdiv s4, s0, s4",
"dup v4.4s, v4.s[0]",
"str d4, [x28, #752]"
"fdiv s2, s0, s2",
"dup v2.4s, v2.s[0]",
"str d2, [x28, #752]"
]
},
"pfrsqrt mm0, mm1": {
@@ -177,12 +177,12 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d2, [x28, #768]",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s4",
"fdiv s4, s0, s1",
"dup v4.4s, v4.s[0]",
"str d4, [x28, #752]"
"fsqrt s1, s2",
"fdiv s2, s0, s1",
"dup v2.4s, v2.s[0]",
"str d2, [x28, #752]"
]
},
"pfsub mm0, mm1": {
@@ -190,10 +190,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fsub v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfadd mm0, mm1": {
@@ -201,10 +201,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fadd v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfcmpgt mm0, mm1": {
@@ -212,10 +212,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfmax mm0, mm1": {
@@ -223,11 +223,11 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v0.4s, v5.4s, v4.4s",
"bit v4.16b, v5.16b, v0.16b",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bit v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
]
},
"pfrcpit1 mm0, mm1": {
@@ -235,8 +235,8 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
]
},
"pfrcpit1 mm0, mm0": {
@@ -244,8 +244,8 @@
"Optimal": "No",
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
},
"pfrsqit1 mm0, mm1": {
@@ -253,8 +253,8 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
]
},
"pfrsqit1 mm0, mm0": {
@@ -262,8 +262,8 @@
"Optimal": "No",
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
},
"pfsubr mm0, mm1": {
@@ -271,10 +271,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fsub v4.4s, v4.4s, v5.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #752]"
]
},
"pfcmpeq mm0, mm1": {
@@ -282,10 +282,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmeq v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfmul mm0, mm1": {
@@ -293,10 +293,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fmul v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pfrcpit2 mm0, mm1": {
@@ -304,8 +304,8 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
]
},
"pfrcpit2 mm0, mm0": {
@@ -313,8 +313,8 @@
"Optimal": "No",
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"str d2, [x28, #752]"
]
},
"db 0x0f, 0x0f, 0xc1, 0xb7": {
@@ -327,14 +327,14 @@
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"smull v4.4s, v4.4h, v5.4h",
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"smull v2.4s, v2.4h, v3.4h",
"mov x20, #0x800000008000",
"dup v5.2d, x20",
"add v4.4s, v4.4s, v5.4s",
"shrn v4.4h, v4.4s, #16",
"str d4, [x28, #752]"
"dup v3.2d, x20",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #752]"
]
},
"pswapd mm0, mm1": {
@@ -342,9 +342,9 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"rev64 v4.2s, v4.2s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"pavgusb mm0, mm1": {
@@ -352,10 +352,10 @@
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"urhadd v4.16b, v5.16b, v4.16b",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
]
}
}
unittests/InstructionCountCI/H0F38.json
+184 -184
View File
@@ -15,12 +15,12 @@
"NP 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"movi v6.16b, #0x87",
"and v5.16b, v5.16b, v6.16b",
"tbl v4.8b, {v4.16b}, v5.8b",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"movi v4.16b, #0x87",
"and v3.16b, v3.16b, v4.16b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #752]"
]
},
"pshufb xmm0, xmm1": {
@@ -30,9 +30,9 @@
"0x66 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"movi v4.16b, #0x8f",
"and v4.16b, v17.16b, v4.16b",
"tbl v16.16b, {v16.16b}, v4.16b"
"movi v2.16b, #0x8f",
"and v2.16b, v17.16b, v2.16b",
"tbl v16.16b, {v16.16b}, v2.16b"
]
},
"phaddw mm0, mm1": {
@@ -42,10 +42,10 @@
"NP 0x0f 0x38 0x01"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"addp v4.4h, v5.4h, v4.4h",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"addp v2.4h, v3.4h, v2.4h",
"str d2, [x28, #752]"
]
},
"phaddw xmm0, xmm1": {
@@ -65,10 +65,10 @@
"NP 0x0f 0x38 0x02"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"addp v4.2s, v5.2s, v4.2s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"addp v2.2s, v3.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"phaddd xmm0, xmm1": {
@@ -88,12 +88,12 @@
"NP 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uzp1 v6.4h, v4.4h, v5.4h",
"uzp2 v4.4h, v4.4h, v5.4h",
"sqadd v4.8h, v6.8h, v4.8h",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqadd v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
]
},
"phaddsw xmm0, xmm1": {
@@ -103,9 +103,9 @@
"0x66 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"uzp1 v4.8h, v16.8h, v17.8h",
"uzp2 v5.8h, v16.8h, v17.8h",
"sqadd v16.8h, v4.8h, v5.8h"
"uzp1 v2.8h, v16.8h, v17.8h",
"uzp2 v3.8h, v16.8h, v17.8h",
"sqadd v16.8h, v2.8h, v3.8h"
]
},
"pmaddubsw mm0, mm1": {
@@ -115,15 +115,15 @@
"NP 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uxtl v4.8h, v4.8b",
"sxtl v5.8h, v5.8b",
"smull v6.4s, v4.4h, v5.4h",
"smull2 v4.4s, v4.8h, v5.8h",
"addp v4.4s, v6.4s, v4.4s",
"sqxtn v4.4h, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uxtl v2.8h, v2.8b",
"sxtl v3.8h, v3.8b",
"smull v4.4s, v2.4h, v3.4h",
"smull2 v2.4s, v2.8h, v3.8h",
"addp v2.4s, v4.4s, v2.4s",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #752]"
]
},
"pmaddubsw xmm0, xmm1": {
@@ -137,15 +137,15 @@
"0x66 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"uxtl v4.8h, v16.8b",
"sxtl v5.8h, v17.8b",
"mul v4.8h, v4.8h, v5.8h",
"uxtl2 v5.8h, v16.16b",
"sxtl2 v6.8h, v17.16b",
"mul v5.8h, v5.8h, v6.8h",
"uzp1 v6.8h, v4.8h, v5.8h",
"uzp2 v4.8h, v4.8h, v5.8h",
"sqadd v16.8h, v6.8h, v4.8h"
"uxtl v2.8h, v16.8b",
"sxtl v3.8h, v17.8b",
"mul v2.8h, v2.8h, v3.8h",
"uxtl2 v3.8h, v16.16b",
"sxtl2 v4.8h, v17.16b",
"mul v3.8h, v3.8h, v4.8h",
"uzp1 v4.8h, v2.8h, v3.8h",
"uzp2 v2.8h, v2.8h, v3.8h",
"sqadd v16.8h, v4.8h, v2.8h"
]
},
"phsubw mm0, mm1": {
@@ -155,12 +155,12 @@
"NP 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uzp1 v6.4h, v4.4h, v5.4h",
"uzp2 v4.4h, v4.4h, v5.4h",
"sub v4.8h, v6.8h, v4.8h",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
]
},
"phsubw xmm0, xmm1": {
@@ -170,9 +170,9 @@
"0x66 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"uzp1 v4.8h, v16.8h, v17.8h",
"uzp2 v5.8h, v16.8h, v17.8h",
"sub v16.8h, v4.8h, v5.8h"
"uzp1 v2.8h, v16.8h, v17.8h",
"uzp2 v3.8h, v16.8h, v17.8h",
"sub v16.8h, v2.8h, v3.8h"
]
},
"phsubd mm0, mm1": {
@@ -182,12 +182,12 @@
"NP 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uzp1 v6.2s, v4.2s, v5.2s",
"uzp2 v4.2s, v4.2s, v5.2s",
"sub v4.4s, v6.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"sub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"phsubd xmm0, xmm1": {
@@ -197,9 +197,9 @@
"0x66 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"uzp1 v4.4s, v16.4s, v17.4s",
"uzp2 v5.4s, v16.4s, v17.4s",
"sub v16.4s, v4.4s, v5.4s"
"uzp1 v2.4s, v16.4s, v17.4s",
"uzp2 v3.4s, v16.4s, v17.4s",
"sub v16.4s, v2.4s, v3.4s"
]
},
"phsubsw mm0, mm1": {
@@ -209,12 +209,12 @@
"NP 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"uzp1 v6.4h, v4.4h, v5.4h",
"uzp2 v4.4h, v4.4h, v5.4h",
"sqsub v4.8h, v6.8h, v4.8h",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqsub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
]
},
"phsubsw xmm0, xmm1": {
@@ -224,9 +224,9 @@
"0x66 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"uzp1 v4.8h, v16.8h, v17.8h",
"uzp2 v5.8h, v16.8h, v17.8h",
"sqsub v16.8h, v4.8h, v5.8h"
"uzp1 v2.8h, v16.8h, v17.8h",
"uzp2 v3.8h, v16.8h, v17.8h",
"sqsub v16.8h, v2.8h, v3.8h"
]
},
"psignb mm0, mm1": {
@@ -236,12 +236,12 @@
"NP 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"sqshl v4.8b, v4.8b, #7",
"srshr v4.8b, v4.8b, #7",
"mul v4.16b, v5.16b, v4.16b",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"sqshl v2.8b, v2.8b, #7",
"srshr v2.8b, v2.8b, #7",
"mul v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
]
},
"psignb xmm0, xmm1": {
@@ -251,9 +251,9 @@
"0x66 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"sqshl v4.16b, v17.16b, #7",
"srshr v4.16b, v4.16b, #7",
"mul v16.16b, v16.16b, v4.16b"
"sqshl v2.16b, v17.16b, #7",
"srshr v2.16b, v2.16b, #7",
"mul v16.16b, v16.16b, v2.16b"
]
},
"psignw mm0, mm1": {
@@ -263,12 +263,12 @@
"NP 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"sqshl v4.4h, v4.4h, #15",
"srshr v4.4h, v4.4h, #15",
"mul v4.8h, v5.8h, v4.8h",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"sqshl v2.4h, v2.4h, #15",
"srshr v2.4h, v2.4h, #15",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #752]"
]
},
"psignw xmm0, xmm1": {
@@ -278,9 +278,9 @@
"0x66 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"sqshl v4.8h, v17.8h, #15",
"srshr v4.8h, v4.8h, #15",
"mul v16.8h, v16.8h, v4.8h"
"sqshl v2.8h, v17.8h, #15",
"srshr v2.8h, v2.8h, #15",
"mul v16.8h, v16.8h, v2.8h"
]
},
"psignd mm0, mm1": {
@@ -290,12 +290,12 @@
"NP 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"sqshl v4.2s, v4.2s, #31",
"srshr v4.2s, v4.2s, #31",
"mul v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"sqshl v2.2s, v2.2s, #31",
"srshr v2.2s, v2.2s, #31",
"mul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"psignd xmm0, xmm1": {
@@ -305,9 +305,9 @@
"0x66 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"sqshl v4.4s, v17.4s, #31",
"srshr v4.4s, v4.4s, #31",
"mul v16.4s, v16.4s, v4.4s"
"sqshl v2.4s, v17.4s, #31",
"srshr v2.4s, v2.4s, #31",
"mul v16.4s, v16.4s, v2.4s"
]
},
"pmulhrsw mm0, mm1": {
@@ -318,14 +318,14 @@
"NP 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"smull v4.4s, v4.4h, v5.4h",
"sshr v4.4s, v4.4s, #14",
"movi v5.4s, #0x1, lsl #0",
"add v4.4s, v4.4s, v5.4s",
"shrn v4.4h, v4.4s, #1",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #752]"
]
},
"pmulhrsw xmm0, xmm1": {
@@ -336,16 +336,16 @@
"0x66 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"smull v4.4s, v16.4h, v17.4h",
"smull2 v5.4s, v16.8h, v17.8h",
"sshr v4.4s, v4.4s, #14",
"sshr v5.4s, v5.4s, #14",
"movi v6.4s, #0x1, lsl #0",
"add v4.4s, v4.4s, v6.4s",
"add v5.4s, v5.4s, v6.4s",
"shrn v4.4h, v4.4s, #1",
"mov v0.16b, v4.16b",
"shrn2 v0.8h, v5.4s, #1",
"smull v2.4s, v16.4h, v17.4h",
"smull2 v3.4s, v16.8h, v17.8h",
"sshr v2.4s, v2.4s, #14",
"sshr v3.4s, v3.4s, #14",
"movi v4.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v4.4s",
"add v3.4s, v3.4s, v4.4s",
"shrn v2.4h, v2.4s, #1",
"mov v0.16b, v2.16b",
"shrn2 v0.8h, v3.4s, #1",
"mov v16.16b, v0.16b"
]
},
@@ -356,8 +356,8 @@
"0x66 0x0f 0x38 0x10"
],
"ExpectedArm64ASM": [
"sshr v4.16b, v16.16b, #7",
"bit v16.16b, v17.16b, v4.16b"
"sshr v2.16b, v16.16b, #7",
"bit v16.16b, v17.16b, v2.16b"
]
},
"blendvps xmm0, xmm1": {
@@ -367,8 +367,8 @@
"0x66 0x0f 0x38 0x14"
],
"ExpectedArm64ASM": [
"sshr v4.4s, v16.4s, #31",
"bit v16.16b, v17.16b, v4.16b"
"sshr v2.4s, v16.4s, #31",
"bit v16.16b, v17.16b, v2.16b"
]
},
"blendvpd xmm0, xmm1": {
@@ -378,8 +378,8 @@
"0x66 0x0f 0x38 0x15"
],
"ExpectedArm64ASM": [
"sshr v4.2d, v16.2d, #63",
"bit v16.16b, v17.16b, v4.16b"
"sshr v2.2d, v16.2d, #63",
"bit v16.16b, v17.16b, v2.16b"
]
},
"pblendvb xmm1, xmm2": {
@@ -389,8 +389,8 @@
"0x66 0x0f 0x38 0x10"
],
"ExpectedArm64ASM": [
"sshr v4.16b, v16.16b, #7",
"bit v17.16b, v18.16b, v4.16b"
"sshr v2.16b, v16.16b, #7",
"bit v17.16b, v18.16b, v2.16b"
]
},
"blendvps xmm1, xmm2": {
@@ -400,8 +400,8 @@
"0x66 0x0f 0x38 0x14"
],
"ExpectedArm64ASM": [
"sshr v4.4s, v16.4s, #31",
"bit v17.16b, v18.16b, v4.16b"
"sshr v2.4s, v16.4s, #31",
"bit v17.16b, v18.16b, v2.16b"
]
},
"blendvpd xmm1, xmm2": {
@@ -411,8 +411,8 @@
"0x66 0x0f 0x38 0x15"
],
"ExpectedArm64ASM": [
"sshr v4.2d, v16.2d, #63",
"bit v17.16b, v18.16b, v4.16b"
"sshr v2.2d, v16.2d, #63",
"bit v17.16b, v18.16b, v2.16b"
]
},
"ptest xmm0, xmm1": {
@@ -422,14 +422,14 @@
"0x66 0x0f 0x38 0x17"
],
"ExpectedArm64ASM": [
"and v4.16b, v16.16b, v17.16b",
"bic v5.16b, v17.16b, v16.16b",
"cnt v4.16b, v4.16b",
"cnt v5.16b, v5.16b",
"addv h4, v4.8h",
"addv h5, v5.8h",
"umov w20, v4.h[0]",
"umov w21, v5.h[0]",
"and v2.16b, v16.16b, v17.16b",
"bic v3.16b, v17.16b, v16.16b",
"cnt v2.16b, v2.16b",
"cnt v3.16b, v3.16b",
"addv h2, v2.8h",
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
@@ -452,9 +452,9 @@
"NP 0x0f 0x38 0x1c"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"abs v4.16b, v4.16b",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"abs v2.16b, v2.16b",
"str d2, [x28, #752]"
]
},
"pabsb xmm0, xmm1": {
@@ -474,9 +474,9 @@
"NP 0x0f 0x38 0x1d"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"abs v4.8h, v4.8h",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"abs v2.8h, v2.8h",
"str d2, [x28, #752]"
]
},
"pabsw xmm0, xmm1": {
@@ -496,9 +496,9 @@
"NP 0x0f 0x38 0x1e"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"abs v4.4s, v4.4s",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"abs v2.4s, v2.4s",
"str d2, [x28, #752]"
]
},
"pabsd xmm0, xmm1": {
@@ -528,8 +528,8 @@
"0x66 0x0f 0x38 0x31"
],
"ExpectedArm64ASM": [
"uxtl v4.8h, v17.8b",
"uxtl v16.4s, v4.4h"
"uxtl v2.8h, v17.8b",
"uxtl v16.4s, v2.4h"
]
},
"pmovzxbq xmm0, xmm1": {
@@ -539,9 +539,9 @@
"0x66 0x0f 0x38 0x32"
],
"ExpectedArm64ASM": [
"uxtl v4.8h, v17.8b",
"uxtl v4.4s, v4.4h",
"uxtl v16.2d, v4.2s"
"uxtl v2.8h, v17.8b",
"uxtl v2.4s, v2.4h",
"uxtl v16.2d, v2.2s"
]
},
"pmovzxwd xmm0, xmm1": {
@@ -561,8 +561,8 @@
"0x66 0x0f 0x38 0x34"
],
"ExpectedArm64ASM": [
"uxtl v4.4s, v17.4h",
"uxtl v16.2d, v4.2s"
"uxtl v2.4s, v17.4h",
"uxtl v16.2d, v2.2s"
]
},
"pmovzxdq xmm0, xmm1": {
@@ -683,12 +683,12 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1552]",
"ldr q4, [x0]",
"zip1 v5.8h, v4.8h, v17.8h",
"zip2 v4.8h, v4.8h, v17.8h",
"umin v4.4s, v5.4s, v4.4s",
"uminv s4, v4.4s",
"rev32 v16.8h, v4.8h"
"ldr q2, [x0]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
"uminv s2, v2.4s",
"rev32 v16.8h, v2.8h"
]
},
"sha1nexte xmm0, xmm1": {
@@ -713,8 +713,8 @@
"0x66 0x0f 0x38 0xc9"
],
"ExpectedArm64ASM": [
"ext v4.16b, v17.16b, v16.16b, #8",
"eor v16.16b, v16.16b, v4.16b"
"ext v2.16b, v17.16b, v16.16b, #8",
"eor v16.16b, v16.16b, v2.16b"
]
},
"sha1msg2 xmm0, xmm1": {
@@ -739,11 +739,11 @@
"mov w23, v16.s[0]",
"eor w23, w23, w20",
"ror w23, w23, #31",
"mov v4.16b, v16.16b",
"mov v4.s[3], w20",
"mov v4.s[2], w21",
"mov v4.s[1], w22",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w21",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w23"
]
},
@@ -853,11 +853,11 @@
"add w21, w21, w23",
"ldr w23, [sp, #128]",
"add w21, w21, w23",
"mov v4.16b, v16.16b",
"mov v4.s[3], w20",
"mov v4.s[2], w24",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w22",
"add sp, sp, #0x120 (288)"
]
@@ -898,11 +898,11 @@
"lsr w23, w23, #3",
"eor w23, w25, w23",
"add w23, w24, w23",
"mov v4.16b, v16.16b",
"mov v4.s[3], w20",
"mov v4.s[2], w21",
"mov v4.s[1], w22",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w21",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w23"
]
},
@@ -943,11 +943,11 @@
"lsr w25, w21, #10",
"eor w24, w24, w25",
"add w23, w23, w24",
"mov v4.16b, v16.16b",
"mov v4.s[3], w23",
"mov v4.s[2], w22",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
},
@@ -968,7 +968,7 @@
"0x66 0x0f 0x38 0xdc"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"movi v2.2d, #0x0",
"unimplemented (Unimplemented)",
"unimplemented (Unimplemented)",
"eor v16.16b, v16.16b, v17.16b"
@@ -981,7 +981,7 @@
"0x66 0x0f 0x38 0xdd"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"movi v2.2d, #0x0",
"unimplemented (Unimplemented)",
"eor v16.16b, v16.16b, v17.16b"
]
@@ -993,7 +993,7 @@
"0x66 0x0f 0x38 0xde"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"movi v2.2d, #0x0",
"unimplemented (Unimplemented)",
"unimplemented (Unimplemented)",
"eor v16.16b, v16.16b, v17.16b"
@@ -1006,7 +1006,7 @@
"0x66 0x0f 0x38 0xdf"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"movi v2.2d, #0x0",
"unimplemented (Unimplemented)",
"eor v16.16b, v16.16b, v17.16b"
]
unittests/InstructionCountCI/H0F3A.json
+248 -248
View File
@@ -19,10 +19,10 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"ext v4.8b, v5.8b, v4.8b, #0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ext v2.8b, v3.8b, v2.8b, #0",
"str d2, [x28, #752]"
]
},
"palignr mm0, mm1, 1": {
@@ -32,10 +32,10 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"ext v4.8b, v5.8b, v4.8b, #1",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ext v2.8b, v3.8b, v2.8b, #1",
"str d2, [x28, #752]"
]
},
"palignr mm0, mm1, 255": {
@@ -45,8 +45,8 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"roundps xmm0, xmm1, 00000000b": {
@@ -167,8 +167,8 @@
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintn s4, s17",
"mov v16.s[0], v4.s[0]"
"frintn s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"roundss xmm0, xmm1, 00000001b": {
@@ -179,8 +179,8 @@
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintm s4, s17",
"mov v16.s[0], v4.s[0]"
"frintm s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"roundss xmm0, xmm1, 00000010b": {
@@ -191,8 +191,8 @@
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintp s4, s17",
"mov v16.s[0], v4.s[0]"
"frintp s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"roundss xmm0, xmm1, 00000011b": {
@@ -203,8 +203,8 @@
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintz s4, s17",
"mov v16.s[0], v4.s[0]"
"frintz s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"roundss xmm0, xmm1, 00000100b": {
@@ -215,8 +215,8 @@
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frinti s4, s17",
"mov v16.s[0], v4.s[0]"
"frinti s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"roundsd xmm0, xmm1, 00000000b": {
@@ -227,8 +227,8 @@
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintn d4, d17",
"mov v16.d[0], v4.d[0]"
"frintn d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"roundsd xmm0, xmm1, 00000001b": {
@@ -239,8 +239,8 @@
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintm d4, d17",
"mov v16.d[0], v4.d[0]"
"frintm d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"roundsd xmm0, xmm1, 00000010b": {
@@ -251,8 +251,8 @@
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintp d4, d17",
"mov v16.d[0], v4.d[0]"
"frintp d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"roundsd xmm0, xmm1, 00000011b": {
@@ -263,8 +263,8 @@
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintz d4, d17",
"mov v16.d[0], v4.d[0]"
"frintz d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"roundsd xmm0, xmm1, 00000100b": {
@@ -275,8 +275,8 @@
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frinti d4, d17",
"mov v16.d[0], v4.d[0]"
"frinti d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"blendps xmm0, xmm1, 0000b": {
@@ -286,8 +286,8 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v4.16b, v16.16b",
"mov v16.16b, v4.16b"
"mov v2.16b, v16.16b",
"mov v16.16b, v2.16b"
]
},
"blendps xmm0, xmm1, 0001b": {
@@ -319,8 +319,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[1], v17.s[1]",
"mov v16.16b, v0.16b"
]
@@ -344,8 +344,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[2], v17.s[2]",
"mov v16.16b, v0.16b"
]
@@ -359,8 +359,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[1], v17.s[1]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[2], v17.s[2]",
"mov v16.16b, v0.16b"
]
@@ -374,9 +374,9 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v4.s[1], v17.s[1]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.s[1], v17.s[1]",
"mov v0.16b, v2.16b",
"mov v0.s[2], v17.s[2]",
"mov v16.16b, v0.16b"
]
@@ -400,8 +400,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -415,8 +415,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[1], v17.s[1]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -430,9 +430,9 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v4.s[1], v17.s[1]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.s[1], v17.s[1]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -446,8 +446,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[2], v17.s[2]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -461,9 +461,9 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v4.s[2], v17.s[2]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.s[2], v17.s[2]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -477,9 +477,9 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[1], v17.s[1]",
"mov v4.16b, v0.16b",
"mov v4.s[2], v17.s[2]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.s[2], v17.s[2]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -493,10 +493,10 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"mov v4.s[1], v17.s[1]",
"mov v4.s[2], v17.s[2]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v17.s[3]",
"mov v16.16b, v0.16b"
]
@@ -508,8 +508,8 @@
"0x66 0x0f 0x3a 0x0d"
],
"ExpectedArm64ASM": [
"mov v4.16b, v16.16b",
"mov v16.16b, v4.16b"
"mov v2.16b, v16.16b",
"mov v16.16b, v2.16b"
]
},
"blendpd xmm0, xmm1, 01b": {
@@ -541,8 +541,8 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.d[0], v17.d[0]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v0.16b, v2.16b",
"mov v0.d[1], v17.d[1]",
"mov v16.16b, v0.16b"
]
@@ -554,8 +554,8 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v4.16b, v16.16b",
"mov v16.16b, v4.16b"
"mov v2.16b, v16.16b",
"mov v16.16b, v2.16b"
]
},
"pblendw xmm0, xmm1, 00000001b": {
@@ -577,14 +577,14 @@
"ExpectedArm64ASM": [
"mov v0.16b, v16.16b",
"mov v0.h[0], v17.h[0]",
"mov v4.16b, v0.16b",
"mov v4.h[1], v17.h[1]",
"mov v4.h[2], v17.h[2]",
"mov v4.h[3], v17.h[3]",
"mov v4.h[4], v17.h[4]",
"mov v4.h[5], v17.h[5]",
"mov v4.h[6], v17.h[6]",
"mov v0.16b, v4.16b",
"mov v2.16b, v0.16b",
"mov v2.h[1], v17.h[1]",
"mov v2.h[2], v17.h[2]",
"mov v2.h[3], v17.h[3]",
"mov v2.h[4], v17.h[4]",
"mov v2.h[5], v17.h[5]",
"mov v2.h[6], v17.h[6]",
"mov v0.16b, v2.16b",
"mov v0.h[7], v17.h[7]",
"mov v16.16b, v0.16b"
]
@@ -856,19 +856,19 @@
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"fmul v5.4s, v16.4s, v17.4s",
"mov v5.s[0], v4.s[0]",
"mov v5.s[1], v4.s[0]",
"mov v5.s[2], v4.s[0]",
"mov v5.s[3], v4.s[0]",
"faddp v5.4s, v5.4s, v4.4s",
"faddp v5.4s, v5.4s, v4.4s",
"mov v4.s[0], v5.s[0]",
"mov v4.s[1], v5.s[0]",
"mov v4.s[2], v5.s[0]",
"mov v0.16b, v4.16b",
"mov v0.s[3], v5.s[0]",
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"mov v3.s[0], v2.s[0]",
"mov v3.s[1], v2.s[0]",
"mov v3.s[2], v2.s[0]",
"mov v3.s[3], v2.s[0]",
"faddp v3.4s, v3.4s, v2.4s",
"faddp v3.4s, v3.4s, v2.4s",
"mov v2.s[0], v3.s[0]",
"mov v2.s[1], v3.s[0]",
"mov v2.s[2], v3.s[0]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v3.s[0]",
"mov v16.16b, v0.16b"
]
},
@@ -889,15 +889,15 @@
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"fmul v5.4s, v16.4s, v17.4s",
"faddp v5.4s, v5.4s, v4.4s",
"faddp v5.4s, v5.4s, v4.4s",
"mov v4.s[0], v5.s[0]",
"mov v4.s[1], v5.s[0]",
"mov v4.s[2], v5.s[0]",
"mov v0.16b, v4.16b",
"mov v0.s[3], v5.s[0]",
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v2.4s",
"faddp v3.4s, v3.4s, v2.4s",
"mov v2.s[0], v3.s[0]",
"mov v2.s[1], v3.s[0]",
"mov v2.s[2], v3.s[0]",
"mov v0.16b, v2.16b",
"mov v0.s[3], v3.s[0]",
"mov v16.16b, v0.16b"
]
},
@@ -918,14 +918,14 @@
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"fmul v5.2d, v16.2d, v17.2d",
"mov v5.d[0], v4.d[0]",
"mov v5.d[1], v4.d[0]",
"faddp v5.2d, v5.2d, v4.2d",
"mov v4.d[0], v5.d[0]",
"mov v0.16b, v4.16b",
"mov v0.d[1], v5.d[0]",
"movi v2.2d, #0x0",
"fmul v3.2d, v16.2d, v17.2d",
"mov v3.d[0], v2.d[0]",
"mov v3.d[1], v2.d[0]",
"faddp v3.2d, v3.2d, v2.2d",
"mov v2.d[0], v3.d[0]",
"mov v0.16b, v2.16b",
"mov v0.d[1], v3.d[0]",
"mov v16.16b, v0.16b"
]
},
@@ -946,12 +946,12 @@
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"fmul v5.2d, v16.2d, v17.2d",
"faddp v5.2d, v5.2d, v4.2d",
"mov v4.d[0], v5.d[0]",
"mov v0.16b, v4.16b",
"mov v0.d[1], v5.d[0]",
"movi v2.2d, #0x0",
"fmul v3.2d, v16.2d, v17.2d",
"faddp v3.2d, v3.2d, v2.2d",
"mov v2.d[0], v3.d[0]",
"mov v0.16b, v2.16b",
"mov v0.d[1], v3.d[0]",
"mov v16.16b, v0.16b"
]
},
@@ -962,20 +962,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[0]",
"ext v5.16b, v16.16b, v16.16b, #0",
"ext v6.16b, v16.16b, v16.16b, #1",
"ext v7.16b, v16.16b, v16.16b, #2",
"ext v8.16b, v16.16b, v16.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[0]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 001b": {
@@ -985,20 +985,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[1]",
"ext v5.16b, v16.16b, v16.16b, #0",
"ext v6.16b, v16.16b, v16.16b, #1",
"ext v7.16b, v16.16b, v16.16b, #2",
"ext v8.16b, v16.16b, v16.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[1]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 010b": {
@@ -1008,20 +1008,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[2]",
"ext v5.16b, v16.16b, v16.16b, #0",
"ext v6.16b, v16.16b, v16.16b, #1",
"ext v7.16b, v16.16b, v16.16b, #2",
"ext v8.16b, v16.16b, v16.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[2]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 011b": {
@@ -1031,20 +1031,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[3]",
"ext v5.16b, v16.16b, v16.16b, #0",
"ext v6.16b, v16.16b, v16.16b, #1",
"ext v7.16b, v16.16b, v16.16b, #2",
"ext v8.16b, v16.16b, v16.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[3]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 100b": {
@@ -1054,20 +1054,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[0]",
"ext v5.16b, v16.16b, v16.16b, #4",
"ext v6.16b, v16.16b, v16.16b, #5",
"ext v7.16b, v16.16b, v16.16b, #6",
"ext v8.16b, v16.16b, v16.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[0]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 101b": {
@@ -1077,20 +1077,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[1]",
"ext v5.16b, v16.16b, v16.16b, #4",
"ext v6.16b, v16.16b, v16.16b, #5",
"ext v7.16b, v16.16b, v16.16b, #6",
"ext v8.16b, v16.16b, v16.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[1]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 110b": {
@@ -1100,20 +1100,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[2]",
"ext v5.16b, v16.16b, v16.16b, #4",
"ext v6.16b, v16.16b, v16.16b, #5",
"ext v7.16b, v16.16b, v16.16b, #6",
"ext v8.16b, v16.16b, v16.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[2]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 111b": {
@@ -1123,20 +1123,20 @@
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v4.4s, v17.s[3]",
"ext v5.16b, v16.16b, v16.16b, #4",
"ext v6.16b, v16.16b, v16.16b, #5",
"ext v7.16b, v16.16b, v16.16b, #6",
"ext v8.16b, v16.16b, v16.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h"
"dup v2.4s, v17.s[3]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"pclmulqdq xmm0, xmm1, 00000b": {
@@ -1240,11 +1240,11 @@
"add w23, w23, w24",
"add w23, w23, w26",
"ror w21, w21, #2",
"mov v4.16b, v16.16b",
"mov v4.s[3], w23",
"mov v4.s[2], w22",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
]
@@ -1304,11 +1304,11 @@
"add w23, w23, w24",
"add w23, w23, w26",
"ror w21, w21, #2",
"mov v4.16b, v16.16b",
"mov v4.s[3], w23",
"mov v4.s[2], w22",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
]
@@ -1380,11 +1380,11 @@
"add w23, w23, w24",
"add w23, w23, w26",
"ror w21, w21, #2",
"mov v4.16b, v16.16b",
"mov v4.s[3], w23",
"mov v4.s[2], w22",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
]
@@ -1444,11 +1444,11 @@
"add w23, w23, w24",
"add w23, w23, w26",
"ror w21, w21, #2",
"mov v4.16b, v16.16b",
"mov v4.s[3], w23",
"mov v4.s[2], w22",
"mov v4.s[1], w21",
"mov v16.16b, v4.16b",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
]
@@ -1461,11 +1461,11 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1608]",
"ldr q4, [x0]",
"movi v5.2d, #0x0",
"ldr q2, [x0]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v4.16b"
"tbl v16.16b, {v16.16b}, v2.16b"
]
},
"aeskeygenassist xmm0, xmm1, 0xFF": {
@@ -1476,11 +1476,11 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1608]",
"ldr q4, [x0]",
"movi v5.2d, #0x0",
"ldr q2, [x0]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v4.16b",
"tbl v16.16b, {v16.16b}, v2.16b",
"mov x0, #0xff00000000",
"dup v1.2d, x0",
"eor v16.16b, v16.16b, v1.16b"
unittests/InstructionCountCI/Primary.json
+9 -9
View File
@@ -3109,9 +3109,9 @@
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
@@ -3160,9 +3160,9 @@
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
@@ -3284,9 +3284,9 @@
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
unittests/InstructionCountCI/Secondary.json
+445 -445
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+148 -136
View File
@@ -85,13 +85,15 @@
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"orr x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"mov x0, x20",
"bfxil x0, x21, #0, #16",
"mov x4, x0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
@@ -161,13 +163,15 @@
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov x20, x4",
"and x21, x20, #0xfffffffffffffffe",
"bfxil x4, x21, #0, #16",
"mov x0, x20",
"bfxil x0, x21, #0, #16",
"mov x4, x0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
@@ -237,13 +241,15 @@
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"eor x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"mov x0, x20",
"bfxil x0, x21, #0, #16",
"mov x4, x0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
@@ -491,9 +497,9 @@
"Optimal": "Yes",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ushr v4.8h, v4.8h, #15",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
]
},
"psrlw mm0, 16": {
@@ -502,9 +508,9 @@
"Optimal": "No",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"psrlw xmm0, 0": {
@@ -545,9 +551,9 @@
"Optimal": "Yes",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"sshr v4.8h, v4.8h, #15",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
]
},
"psraw mm0, 16": {
@@ -556,9 +562,9 @@
"Optimal": "Yes",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"sshr v4.8h, v4.8h, #15",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
]
},
"psraw xmm0, 0": {
@@ -599,9 +605,9 @@
"Optimal": "Yes",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"shl v4.8h, v4.8h, #15",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
]
},
"psllw mm0, 16": {
@@ -610,9 +616,9 @@
"Optimal": "No",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"psllw xmm0, 0": {
@@ -653,9 +659,9 @@
"Optimal": "Yes",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ushr v4.4s, v4.4s, #31",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
]
},
"psrld mm0, 32": {
@@ -664,9 +670,9 @@
"Optimal": "No",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"psrld xmm0, 0": {
@@ -707,9 +713,9 @@
"Optimal": "Yes",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"sshr v4.4s, v4.4s, #31",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
]
},
"psrad mm0, 32": {
@@ -718,9 +724,9 @@
"Optimal": "Yes",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"sshr v4.4s, v4.4s, #31",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
]
},
"psrad xmm0, 0": {
@@ -761,9 +767,9 @@
"Optimal": "Yes",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"shl v4.4s, v4.4s, #31",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
]
},
"pslld mm0, 32": {
@@ -772,9 +778,9 @@
"Optimal": "No",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"pslld xmm0, 0": {
@@ -815,9 +821,9 @@
"Optimal": "No",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ushr v4.2d, v4.2d, #63",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
]
},
"psrlq mm0, 64": {
@@ -826,9 +832,9 @@
"Optimal": "No",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"psrlq xmm0, 0": {
@@ -869,8 +875,8 @@
"Optimal": "No",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"ext v16.16b, v16.16b, v4.16b, #15"
"movi v2.2d, #0x0",
"ext v16.16b, v16.16b, v2.16b, #15"
]
},
"psrldq xmm0, 16": {
@@ -895,9 +901,9 @@
"Optimal": "Yes",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"shl v4.2d, v4.2d, #63",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
]
},
"psllq mm0, 64": {
@@ -906,9 +912,9 @@
"Optimal": "No",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"movi v4.2d, #0x0",
"str d4, [x28, #752]"
"ldr d2, [x28, #752]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
]
},
"psllq xmm0, 0": {
@@ -962,22 +968,22 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"strb w20, [x4, #4]",
"ldr q4, [x28, #752]",
"str q4, [x4, #32]",
"ldr q4, [x28, #768]",
"str q4, [x4, #48]",
"ldr q4, [x28, #784]",
"str q4, [x4, #64]",
"ldr q4, [x28, #800]",
"str q4, [x4, #80]",
"ldr q4, [x28, #816]",
"str q4, [x4, #96]",
"ldr q4, [x28, #832]",
"str q4, [x4, #112]",
"ldr q4, [x28, #848]",
"str q4, [x4, #128]",
"ldr q4, [x28, #864]",
"str q4, [x4, #144]",
"ldr q2, [x28, #752]",
"str q2, [x4, #32]",
"ldr q2, [x28, #768]",
"str q2, [x4, #48]",
"ldr q2, [x28, #784]",
"str q2, [x4, #64]",
"ldr q2, [x28, #800]",
"str q2, [x4, #80]",
"ldr q2, [x28, #816]",
"str q2, [x4, #96]",
"ldr q2, [x28, #832]",
"str q2, [x4, #112]",
"ldr q2, [x28, #848]",
"str q2, [x4, #128]",
"ldr q2, [x28, #864]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
"str q18, [x4, #192]",
@@ -1033,7 +1039,7 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 103,
"ExpectedInstructionCount": 105,
"Optimal": "No",
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
@@ -1051,8 +1057,9 @@
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xd0 (208)",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1060,6 +1067,7 @@
"uxth w0, w20",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1091,22 +1099,22 @@
"strb w20, [x28, #750]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1010]",
"ldr q4, [x4, #32]",
"str q4, [x28, #752]",
"ldr q4, [x4, #48]",
"str q4, [x28, #768]",
"ldr q4, [x4, #64]",
"str q4, [x28, #784]",
"ldr q4, [x4, #80]",
"str q4, [x28, #800]",
"ldr q4, [x4, #96]",
"str q4, [x28, #816]",
"ldr q4, [x4, #112]",
"str q4, [x28, #832]",
"ldr q4, [x4, #128]",
"str q4, [x28, #848]",
"ldr q4, [x4, #144]",
"str q4, [x28, #864]",
"ldr q2, [x4, #32]",
"str q2, [x28, #752]",
"ldr q2, [x4, #48]",
"str q2, [x28, #768]",
"ldr q2, [x4, #64]",
"str q2, [x28, #784]",
"ldr q2, [x4, #80]",
"str q2, [x28, #800]",
"ldr q2, [x4, #96]",
"str q2, [x28, #816]",
"ldr q2, [x4, #112]",
"str q2, [x28, #832]",
"ldr q2, [x4, #128]",
"str q2, [x28, #848]",
"ldr q2, [x4, #144]",
"str q2, [x28, #864]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1271,22 +1279,22 @@
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"strb w22, [x21, #4]",
"ldr q4, [x28, #752]",
"str q4, [x21, #32]",
"ldr q4, [x28, #768]",
"str q4, [x21, #48]",
"ldr q4, [x28, #784]",
"str q4, [x21, #64]",
"ldr q4, [x28, #800]",
"str q4, [x21, #80]",
"ldr q4, [x28, #816]",
"str q4, [x21, #96]",
"ldr q4, [x28, #832]",
"str q4, [x21, #112]",
"ldr q4, [x28, #848]",
"str q4, [x21, #128]",
"ldr q4, [x28, #864]",
"str q4, [x21, #144]",
"ldr q2, [x28, #752]",
"str q2, [x21, #32]",
"ldr q2, [x28, #768]",
"str q2, [x21, #48]",
"ldr q2, [x28, #784]",
"str q2, [x21, #64]",
"ldr q2, [x28, #800]",
"str q2, [x21, #80]",
"ldr q2, [x28, #816]",
"str q2, [x21, #96]",
"ldr q2, [x28, #832]",
"str q2, [x21, #112]",
"ldr q2, [x28, #848]",
"str q2, [x21, #128]",
"ldr q2, [x28, #864]",
"str q2, [x21, #144]",
"ubfx x22, x20, #1, #1",
"cbnz x22, #+0x8",
"b #+0x44",
@@ -1342,7 +1350,7 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 190,
"ExpectedInstructionCount": 194,
"Optimal": "No",
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
@@ -1350,7 +1358,7 @@
"ldr x21, [x20, #512]",
"ubfx x22, x21, #0, #1",
"cbnz x22, #+0x8",
"b #+0x120",
"b #+0x128",
"ldrh w22, [x20]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
@@ -1365,8 +1373,9 @@
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xd0 (208)",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1374,6 +1383,7 @@
"uxth w0, w22",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1405,23 +1415,23 @@
"strb w22, [x28, #750]",
"ldrb w22, [x20, #4]",
"strb w22, [x28, #1010]",
"ldr q4, [x20, #32]",
"str q4, [x28, #752]",
"ldr q4, [x20, #48]",
"str q4, [x28, #768]",
"ldr q4, [x20, #64]",
"str q4, [x28, #784]",
"ldr q4, [x20, #80]",
"str q4, [x28, #800]",
"ldr q4, [x20, #96]",
"str q4, [x28, #816]",
"ldr q4, [x20, #112]",
"str q4, [x28, #832]",
"ldr q4, [x20, #128]",
"str q4, [x28, #848]",
"ldr q4, [x20, #144]",
"str q4, [x28, #864]",
"b #+0xe8",
"ldr q2, [x20, #32]",
"str q2, [x28, #752]",
"ldr q2, [x20, #48]",
"str q2, [x28, #768]",
"ldr q2, [x20, #64]",
"str q2, [x28, #784]",
"ldr q2, [x20, #80]",
"str q2, [x28, #800]",
"ldr q2, [x20, #96]",
"str q2, [x28, #816]",
"ldr q2, [x20, #112]",
"str q2, [x28, #832]",
"ldr q2, [x20, #128]",
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"str q2, [x28, #864]",
"b #+0xf0",
"mov w22, #0x0",
"mov w23, #0x37f",
"stp x4, x5, [x28, #8]",
@@ -1437,8 +1447,9 @@
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xd0 (208)",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1446,6 +1457,7 @@
"uxth w0, w23",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1470,15 +1482,15 @@
"strb w22, [x28, #746]",
"strb w22, [x28, #750]",
"strb w22, [x28, #1010]",
"movi v4.2d, #0x0",
"str q4, [x28, #752]",
"str q4, [x28, #768]",
"str q4, [x28, #784]",
"str q4, [x28, #800]",
"str q4, [x28, #816]",
"str q4, [x28, #832]",
"str q4, [x28, #848]",
"str q4, [x28, #864]",
"movi v2.2d, #0x0",
"str q2, [x28, #752]",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
"str q2, [x28, #816]",
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"ubfx x22, x21, #1, #1",
"cbnz x22, #+0x8",
"b #+0x48",
unittests/InstructionCountCI/SecondaryModRM.json
+4 -2
View File
@@ -11,12 +11,13 @@
},
"Instructions": {
"xgetbv": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 46,
"Optimal": "No",
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xd0 (208)",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -51,6 +52,7 @@
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
unittests/InstructionCountCI/Secondary_OpSize.json
+69 -69
View File
@@ -110,9 +110,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x2a",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"sxtl v4.2d, v4.2s",
"scvtf v16.2d, v4.2d"
"ldr d2, [x28, #752]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
},
"movntpd [rax], xmm0": {
@@ -128,9 +128,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtn v4.2s, v16.2d",
"fcvtzs v4.2s, v4.2s",
"str d4, [x28, #752]"
"fcvtn v2.2s, v16.2d",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"cvtpd2pi mm0, xmm0": {
@@ -138,10 +138,10 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x2d",
"ExpectedArm64ASM": [
"fcvtn v4.2s, v16.2d",
"frinti v4.2s, v4.2s",
"fcvtzs v4.2s, v4.2s",
"str d4, [x28, #752]"
"fcvtn v2.2s, v16.2d",
"frinti v2.2s, v2.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
]
},
"ucomisd xmm0, xmm1": {
@@ -204,8 +204,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x50",
"ExpectedArm64ASM": [
"uzp2 v4.4s, v16.4s, v16.4s",
"mov x20, v4.d[0]",
"uzp2 v2.4s, v16.4s, v16.4s",
"mov x20, v2.d[0]",
"bfi x20, x20, #31, #32",
"lsr x4, x20, #62"
]
@@ -247,8 +247,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x5a",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"fcvtn v16.2s, v4.2d"
"ldr q2, [x4]",
"fcvtn v16.2s, v2.2d"
]
},
"cvtps2dq xmm0, xmm1": {
@@ -265,8 +265,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x5b",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"frinti v16.4s, v4.4s",
"ldr q2, [x4]",
"frinti v16.4s, v2.4s",
"fcvtzs v16.4s, v16.4s"
]
},
@@ -317,8 +317,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x60",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip1 v16.16b, v16.16b, v4.16b"
"ldr q2, [x4]",
"zip1 v16.16b, v16.16b, v2.16b"
]
},
"punpcklwd xmm0, xmm1": {
@@ -334,8 +334,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x61",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip1 v16.8h, v16.8h, v4.8h"
"ldr q2, [x4]",
"zip1 v16.8h, v16.8h, v2.8h"
]
},
"punpckldq xmm0, xmm1": {
@@ -351,8 +351,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x62",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip1 v16.4s, v16.4s, v4.4s"
"ldr q2, [x4]",
"zip1 v16.4s, v16.4s, v2.4s"
]
},
"packsswb xmm0, xmm1": {
@@ -369,9 +369,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x63",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"ldr q2, [x4]",
"sqxtn v16.8b, v16.8h",
"sqxtn2 v16.16b, v4.8h"
"sqxtn2 v16.16b, v2.8h"
]
},
"packsswb xmm0, xmm0": {
@@ -421,8 +421,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x68",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip2 v16.16b, v16.16b, v4.16b"
"ldr q2, [x4]",
"zip2 v16.16b, v16.16b, v2.16b"
]
},
"punpckhwd xmm0, xmm1": {
@@ -438,8 +438,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x69",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip2 v16.8h, v16.8h, v4.8h"
"ldr q2, [x4]",
"zip2 v16.8h, v16.8h, v2.8h"
]
},
"punpckhdq xmm0, xmm1": {
@@ -455,8 +455,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x6a",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"zip2 v16.4s, v16.4s, v4.4s"
"ldr q2, [x4]",
"zip2 v16.4s, v16.4s, v2.4s"
]
},
"packssdw xmm0, xmm1": {
@@ -573,8 +573,8 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"dup v16.4s, v4.s[0]"
"ldr q2, [x4]",
"dup v16.4s, v2.s[0]"
]
},
"pshufd xmm0, xmm1, 1": {
@@ -587,8 +587,8 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1632]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
},
"pshufd xmm0, [rax], 1": {
@@ -600,10 +600,10 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"ldr q2, [x4]",
"ldr x0, [x28, #1632]",
"ldr q5, [x0, #16]",
"tbl v16.16b, {v4.16b}, v5.16b"
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
},
"pshufd xmm0, xmm1, 0xff": {
@@ -625,8 +625,8 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"dup v16.4s, v4.s[3]"
"ldr q2, [x4]",
"dup v16.4s, v2.s[3]"
]
},
"pcmpeqb xmm0, xmm1": {
@@ -702,9 +702,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0x7c",
"ExpectedArm64ASM": [
"uzp1 v4.2d, v16.2d, v17.2d",
"uzp2 v5.2d, v16.2d, v17.2d",
"fsub v16.2d, v4.2d, v5.2d"
"uzp1 v2.2d, v16.2d, v17.2d",
"uzp2 v3.2d, v16.2d, v17.2d",
"fsub v16.2d, v2.2d, v3.2d"
]
},
"movd dword [rax], xmm0": {
@@ -737,9 +737,9 @@
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1584]",
"ldr q4, [x0]",
"eor v4.16b, v17.16b, v4.16b",
"fadd v16.2d, v16.2d, v4.2d"
"ldr q2, [x0]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
},
"psrlw xmm0, xmm1": {
@@ -803,13 +803,13 @@
"movk x20, #0x804, lsl #16",
"movk x20, #0x2010, lsl #32",
"movk x20, #0x8040, lsl #48",
"dup v4.2d, x20",
"cmlt v5.16b, v16.16b, #0",
"and v4.16b, v5.16b, v4.16b",
"addp v4.16b, v4.16b, v4.16b",
"addp v4.8b, v4.8b, v4.8b",
"addp v4.8b, v4.8b, v4.8b",
"umov w4, v4.h[0]"
"dup v2.2d, x20",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"addp v2.8b, v2.8b, v2.8b",
"umov w4, v2.h[0]"
]
},
"psubusb xmm0, xmm1": {
@@ -941,8 +941,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xe6",
"ExpectedArm64ASM": [
"fcvtn v4.2s, v17.2d",
"fcvtzs v16.4s, v4.4s"
"fcvtn v2.2s, v17.2d",
"fcvtzs v16.4s, v2.4s"
]
},
"movntdq [rax], xmm0": {
@@ -1055,9 +1055,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xf4",
"ExpectedArm64ASM": [
"uzp1 v4.4s, v16.4s, v16.4s",
"uzp1 v5.4s, v17.4s, v17.4s",
"umull v16.2d, v4.2s, v5.2s"
"uzp1 v2.4s, v16.4s, v16.4s",
"uzp1 v3.4s, v17.4s, v17.4s",
"umull v16.2d, v2.2s, v3.2s"
]
},
"pmaddwd xmm0, xmm1": {
@@ -1065,9 +1065,9 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xf5",
"ExpectedArm64ASM": [
"smull v4.4s, v16.4h, v17.4h",
"smull2 v5.4s, v16.8h, v17.8h",
"addp v16.4s, v4.4s, v5.4s"
"smull v2.4s, v16.4h, v17.4h",
"smull2 v3.4s, v16.8h, v17.8h",
"addp v16.4s, v2.4s, v3.4s"
]
},
"psadbw xmm0, xmm1": {
@@ -1075,11 +1075,11 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xf6",
"ExpectedArm64ASM": [
"uabdl v4.8h, v16.8b, v17.8b",
"uabdl2 v5.8h, v16.16b, v17.16b",
"addv h4, v4.8h",
"addv h5, v5.8h",
"zip1 v16.2d, v4.2d, v5.2d"
"uabdl v2.8h, v16.8b, v17.8b",
"uabdl2 v3.8h, v16.16b, v17.16b",
"addv h2, v2.8h",
"addv h3, v3.8h",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"maskmovdqu xmm0, xmm1": {
@@ -1087,10 +1087,10 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xf7",
"ExpectedArm64ASM": [
"cmlt v4.16b, v17.16b, #0",
"ldr q5, [x11]",
"bsl v4.16b, v16.16b, v5.16b",
"str q4, [x11]"
"cmlt v2.16b, v17.16b, #0",
"ldr q3, [x11]",
"bsl v2.16b, v16.16b, v3.16b",
"str q2, [x11]"
]
},
"psubb xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+2 -2
View File
@@ -15,8 +15,8 @@
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ext v4.16b, v17.16b, v17.16b, #8",
"fcadd v16.2d, v16.2d, v4.2d, #90"
"ext v2.16b, v17.16b, v17.16b, #8",
"fcadd v16.2d, v16.2d, v2.2d, #90"
]
}
}
unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+10 -10
View File
@@ -16,11 +16,11 @@
"0x66 0x0f 0xe4"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z16.d",
"mov z5.d, p7/m, z17.d",
"umulh z4.h, p6/m, z4.h, z5.h",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z16.d",
"mov z3.d, p7/m, z17.d",
"umulh z2.h, p6/m, z2.h, z3.h",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"pmulhw xmm0, xmm1": {
@@ -31,11 +31,11 @@
"0x66 0x0f 0xe5"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z16.d",
"mov z5.d, p7/m, z17.d",
"smulh z4.h, p6/m, z4.h, z5.h",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z16.d",
"mov z3.d, p7/m, z17.d",
"smulh z2.h, p6/m, z2.h, z3.h",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
}
}
unittests/InstructionCountCI/Secondary_REP.json
+77 -77
View File
@@ -45,8 +45,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x12",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"trn1 v16.4s, v4.4s, v4.4s"
"ldr q2, [x4]",
"trn1 v16.4s, v2.4s, v2.4s"
]
},
"movshdup xmm0, xmm1": {
@@ -62,8 +62,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x16",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"trn2 v16.4s, v4.4s, v4.4s"
"ldr q2, [x4]",
"trn2 v16.4s, v2.4s, v2.4s"
]
},
"cvtsi2ss xmm0, eax": {
@@ -74,8 +74,8 @@
"0xf3 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"scvtf s4, w4",
"mov v16.s[0], v4.s[0]"
"scvtf s2, w4",
"mov v16.s[0], v2.s[0]"
]
},
"cvtsi2ss xmm0, dword [rax]": {
@@ -86,9 +86,9 @@
"0xf3 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr s4, [x4]",
"scvtf s4, s4",
"mov v16.s[0], v4.s[0]"
"ldr s2, [x4]",
"scvtf s2, s2",
"mov v16.s[0], v2.s[0]"
]
},
"cvtsi2ss xmm0, rax": {
@@ -96,8 +96,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2a",
"ExpectedArm64ASM": [
"scvtf s4, x4",
"mov v16.s[0], v4.s[0]"
"scvtf s2, x4",
"mov v16.s[0], v2.s[0]"
]
},
"cvtsi2ss xmm0, qword [rax]": {
@@ -109,8 +109,8 @@
],
"ExpectedArm64ASM": [
"ldr x20, [x4]",
"scvtf s4, x20",
"mov v16.s[0], v4.s[0]"
"scvtf s2, x20",
"mov v16.s[0], v2.s[0]"
]
},
"movntss [rax], xmm0": {
@@ -134,8 +134,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr s4, [x7]",
"fcvtzs w4, s4"
"ldr s2, [x7]",
"fcvtzs w4, s2"
]
},
"cvttss2si rax, xmm0": {
@@ -151,8 +151,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs x4, s4"
"ldr d2, [x7]",
"fcvtzs x4, s2"
]
},
"cvtss2si eax, xmm0": {
@@ -169,8 +169,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr s4, [x7]",
"frinti s0, s4",
"ldr s2, [x7]",
"frinti s0, s2",
"fcvtzs w4, s0"
]
},
@@ -188,8 +188,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti s0, s4",
"ldr d2, [x7]",
"frinti s0, s2",
"fcvtzs x4, s0"
]
},
@@ -198,8 +198,8 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0x51",
"ExpectedArm64ASM": [
"fsqrt s4, s17",
"mov v16.s[0], v4.s[0]"
"fsqrt s2, s17",
"mov v16.s[0], v2.s[0]"
]
},
"rsqrtss xmm0, xmm1": {
@@ -212,8 +212,8 @@
"ExpectedArm64ASM": [
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s17",
"fdiv s4, s0, s1",
"mov v16.s[0], v4.s[0]"
"fdiv s2, s0, s1",
"mov v16.s[0], v2.s[0]"
]
},
"rcpss xmm0, xmm1": {
@@ -225,8 +225,8 @@
],
"ExpectedArm64ASM": [
"fmov s0, #0x70 (1.0000)",
"fdiv s4, s0, s17",
"mov v16.s[0], v4.s[0]"
"fdiv s2, s0, s17",
"mov v16.s[0], v2.s[0]"
]
},
"addss xmm0, xmm1": {
@@ -237,8 +237,8 @@
"0xf3 0x0f 0x58"
],
"ExpectedArm64ASM": [
"fadd s4, s16, s17",
"mov v16.s[0], v4.s[0]"
"fadd s2, s16, s17",
"mov v16.s[0], v2.s[0]"
]
},
"mulss xmm0, xmm1": {
@@ -249,8 +249,8 @@
"0xf3 0x0f 0x59"
],
"ExpectedArm64ASM": [
"fmul s4, s16, s17",
"mov v16.s[0], v4.s[0]"
"fmul s2, s16, s17",
"mov v16.s[0], v2.s[0]"
]
},
"cvtss2sd xmm0, xmm1": {
@@ -258,8 +258,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x5a",
"ExpectedArm64ASM": [
"fcvt d4, s17",
"mov v16.d[0], v4.d[0]"
"fcvt d2, s17",
"mov v16.d[0], v2.d[0]"
]
},
"cvtss2sd xmm0, [rax]": {
@@ -267,9 +267,9 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x5a",
"ExpectedArm64ASM": [
"ldr s4, [x4]",
"fcvt d4, s4",
"mov v16.d[0], v4.d[0]"
"ldr s2, [x4]",
"fcvt d2, s2",
"mov v16.d[0], v2.d[0]"
]
},
"cvttps2dq xmm0, xmm1": {
@@ -288,8 +288,8 @@
"0xf3 0x0f 0x5c"
],
"ExpectedArm64ASM": [
"fsub s4, s16, s17",
"mov v16.s[0], v4.s[0]"
"fsub s2, s16, s17",
"mov v16.s[0], v2.s[0]"
]
},
"minss xmm0, xmm1": {
@@ -301,8 +301,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"fcsel s4, s16, s17, mi",
"mov v16.s[0], v4.s[0]"
"fcsel s2, s16, s17, mi",
"mov v16.s[0], v2.s[0]"
]
},
"divss xmm0, xmm1": {
@@ -313,8 +313,8 @@
"0xf3 0x0f 0x5e"
],
"ExpectedArm64ASM": [
"fdiv s4, s16, s17",
"mov v16.s[0], v4.s[0]"
"fdiv s2, s16, s17",
"mov v16.s[0], v2.s[0]"
]
},
"maxss xmm0, xmm1": {
@@ -326,8 +326,8 @@
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"fcsel s4, s17, s16, mi",
"mov v16.s[0], v4.s[0]"
"fcsel s2, s17, s16, mi",
"mov v16.s[0], v2.s[0]"
]
},
"movdqu xmm0, xmm1": {
@@ -354,8 +354,8 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"dup v4.8h, v17.h[4]",
"trn1 v16.2d, v17.2d, v4.2d"
"dup v2.8h, v17.h[4]",
"trn1 v16.2d, v17.2d, v2.2d"
]
},
"pshufhw xmm0, xmm1, 11100100b": {
@@ -377,8 +377,8 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"zip1 v4.8h, v17.8h, v17.8h",
"zip1 v16.2d, v17.2d, v4.2d"
"zip1 v2.8h, v17.8h, v17.8h",
"zip1 v16.2d, v17.2d, v2.2d"
]
},
"pshufhw xmm0, xmm1, 1": {
@@ -391,8 +391,8 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1624]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
},
"pshufhw xmm0, xmm1, 0xff": {
@@ -403,8 +403,8 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"dup v4.8h, v17.h[7]",
"trn1 v16.2d, v17.2d, v4.2d"
"dup v2.8h, v17.h[7]",
"trn1 v16.2d, v17.2d, v2.2d"
]
},
"movq xmm0, xmm1": {
@@ -595,8 +595,8 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s4, s16, s17",
"mov v16.s[0], v4.s[0]"
"fcmeq s2, s16, s17",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 1": {
@@ -607,8 +607,8 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmgt s4, s17, s16",
"mov v16.s[0], v4.s[0]"
"fcmgt s2, s17, s16",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 2": {
@@ -619,8 +619,8 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge s4, s17, s16",
"mov v16.s[0], v4.s[0]"
"fcmge s2, s17, s16",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 3": {
@@ -633,9 +633,9 @@
"ExpectedArm64ASM": [
"fcmge s0, s16, s17",
"fcmgt s1, s17, s16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
"orr v2.8b, v0.8b, v1.8b",
"mvn v2.8b, v2.8b",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 4": {
@@ -646,9 +646,9 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s4, s16, s17",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
"fcmeq s2, s16, s17",
"mvn v2.8b, v2.8b",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 5": {
@@ -659,9 +659,9 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmgt s4, s17, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
"fcmgt s2, s17, s16",
"mvn v2.16b, v2.16b",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 6": {
@@ -672,9 +672,9 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge s4, s17, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
"fcmge s2, s17, s16",
"mvn v2.16b, v2.16b",
"mov v16.s[0], v2.s[0]"
]
},
"cmpss xmm0, xmm1, 7": {
@@ -687,8 +687,8 @@
"ExpectedArm64ASM": [
"fcmge s0, s16, s17",
"fcmgt s1, s17, s16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.s[0], v4.s[0]"
"orr v2.8b, v0.8b, v1.8b",
"mov v16.s[0], v2.s[0]"
]
},
"movq2dq xmm0, mm0": {
@@ -704,8 +704,8 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0xe6",
"ExpectedArm64ASM": [
"sxtl v4.2d, v17.2s",
"scvtf v16.2d, v4.2d"
"sxtl v2.2d, v17.2s",
"scvtf v16.2d, v2.2d"
]
},
"cvtdq2pd xmm0, [rax]": {
@@ -713,9 +713,9 @@
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0xe6",
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"sxtl v4.2d, v4.2s",
"scvtf v16.2d, v4.2d"
"ldr d2, [x4]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
}
}
unittests/InstructionCountCI/Secondary_REPNE.json
+74 -74
View File
@@ -46,8 +46,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x12",
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"dup v16.2d, v4.d[0]"
"ldr d2, [x4]",
"dup v16.2d, v2.d[0]"
]
},
"cvtsi2sd xmm0, eax": {
@@ -58,8 +58,8 @@
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"scvtf d4, w4",
"mov v16.d[0], v4.d[0]"
"scvtf d2, w4",
"mov v16.d[0], v2.d[0]"
]
},
"cvtsi2sd xmm0, dword [rax]": {
@@ -71,8 +71,8 @@
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"scvtf d4, w20",
"mov v16.d[0], v4.d[0]"
"scvtf d2, w20",
"mov v16.d[0], v2.d[0]"
]
},
"cvtsi2sd xmm0, rax": {
@@ -83,8 +83,8 @@
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"scvtf d4, x4",
"mov v16.d[0], v4.d[0]"
"scvtf d2, x4",
"mov v16.d[0], v2.d[0]"
]
},
"cvtsi2sd xmm0, qword [rax]": {
@@ -95,9 +95,9 @@
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"scvtf d4, d4",
"mov v16.d[0], v4.d[0]"
"ldr d2, [x4]",
"scvtf d2, d2",
"mov v16.d[0], v2.d[0]"
]
},
"movntsd [rax], xmm0": {
@@ -121,8 +121,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs w4, d4"
"ldr d2, [x7]",
"fcvtzs w4, d2"
]
},
"cvttsd2si rax, xmm0": {
@@ -138,8 +138,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs x4, d4"
"ldr d2, [x7]",
"fcvtzs x4, d2"
]
},
"cvtsd2si eax, xmm0": {
@@ -156,8 +156,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti d0, d4",
"ldr d2, [x7]",
"frinti d0, d2",
"fcvtzs x4, d0"
]
},
@@ -175,8 +175,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti d0, d4",
"ldr d2, [x7]",
"frinti d0, d2",
"fcvtzs x4, d0"
]
},
@@ -188,8 +188,8 @@
"0xf2 0x0f 0x51"
],
"ExpectedArm64ASM": [
"fsqrt d4, d17",
"mov v16.d[0], v4.d[0]"
"fsqrt d2, d17",
"mov v16.d[0], v2.d[0]"
]
},
"addsd xmm0, xmm1": {
@@ -200,8 +200,8 @@
"0xf2 0x0f 0x58"
],
"ExpectedArm64ASM": [
"fadd d4, d16, d17",
"mov v16.d[0], v4.d[0]"
"fadd d2, d16, d17",
"mov v16.d[0], v2.d[0]"
]
},
"mulsd xmm0, xmm1": {
@@ -212,8 +212,8 @@
"0xf2 0x0f 0x59"
],
"ExpectedArm64ASM": [
"fmul d4, d16, d17",
"mov v16.d[0], v4.d[0]"
"fmul d2, d16, d17",
"mov v16.d[0], v2.d[0]"
]
},
"cvtsd2ss xmm0, xmm1": {
@@ -224,8 +224,8 @@
"0xf2 0x0f 0x5a"
],
"ExpectedArm64ASM": [
"fcvt s4, d17",
"mov v16.s[0], v4.s[0]"
"fcvt s2, d17",
"mov v16.s[0], v2.s[0]"
]
},
"cvtsd2ss xmm0, [rax]": {
@@ -236,9 +236,9 @@
"0xf2 0x0f 0x5a"
],
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"fcvt s4, d4",
"mov v16.s[0], v4.s[0]"
"ldr d2, [x4]",
"fcvt s2, d2",
"mov v16.s[0], v2.s[0]"
]
},
"subsd xmm0, xmm1": {
@@ -249,8 +249,8 @@
"0xf2 0x0f 0x5c"
],
"ExpectedArm64ASM": [
"fsub d4, d16, d17",
"mov v16.d[0], v4.d[0]"
"fsub d2, d16, d17",
"mov v16.d[0], v2.d[0]"
]
},
"minsd xmm0, xmm1": {
@@ -262,8 +262,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"fcsel d4, d16, d17, mi",
"mov v16.d[0], v4.d[0]"
"fcsel d2, d16, d17, mi",
"mov v16.d[0], v2.d[0]"
]
},
"divsd xmm0, xmm1": {
@@ -274,8 +274,8 @@
"0xf2 0x0f 0x5e"
],
"ExpectedArm64ASM": [
"fdiv d4, d16, d17",
"mov v16.d[0], v4.d[0]"
"fdiv d2, d16, d17",
"mov v16.d[0], v2.d[0]"
]
},
"maxsd xmm0, xmm1": {
@@ -287,8 +287,8 @@
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"fcsel d4, d17, d16, mi",
"mov v16.d[0], v4.d[0]"
"fcsel d2, d17, d16, mi",
"mov v16.d[0], v2.d[0]"
]
},
"pshuflw xmm0, xmm1, 0": {
@@ -299,8 +299,8 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"dup v4.8h, v17.h[0]",
"trn2 v16.2d, v4.2d, v17.2d"
"dup v2.8h, v17.h[0]",
"trn2 v16.2d, v2.2d, v17.2d"
]
},
"pshuflw xmm0, xmm1, 11100100b": {
@@ -322,8 +322,8 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"zip1 v4.8h, v17.8h, v17.8h",
"zip1 v16.2d, v4.2d, v17.2d"
"zip1 v2.8h, v17.8h, v17.8h",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"pshuflw xmm0, xmm1, 1": {
@@ -336,8 +336,8 @@
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1616]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
},
"pshuflw xmm0, xmm1, 0xff": {
@@ -348,8 +348,8 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"dup v4.8h, v17.h[3]",
"trn2 v16.2d, v4.2d, v17.2d"
"dup v2.8h, v17.h[3]",
"trn2 v16.2d, v2.2d, v17.2d"
]
},
"insertq xmm0, xmm1, 0, 0": {
@@ -401,9 +401,9 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x7d",
"ExpectedArm64ASM": [
"uzp1 v4.4s, v16.4s, v17.4s",
"uzp2 v5.4s, v16.4s, v17.4s",
"fsub v16.4s, v4.4s, v5.4s"
"uzp1 v2.4s, v16.4s, v17.4s",
"uzp2 v3.4s, v16.4s, v17.4s",
"fsub v16.4s, v2.4s, v3.4s"
]
},
"cmpsd xmm0, xmm1, 0": {
@@ -414,8 +414,8 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d4, d16, d17",
"mov v16.d[0], v4.d[0]"
"fcmeq d2, d16, d17",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 1": {
@@ -426,8 +426,8 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmgt d4, d17, d16",
"mov v16.d[0], v4.d[0]"
"fcmgt d2, d17, d16",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 2": {
@@ -438,8 +438,8 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge d4, d17, d16",
"mov v16.d[0], v4.d[0]"
"fcmge d2, d17, d16",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 3": {
@@ -452,9 +452,9 @@
"ExpectedArm64ASM": [
"fcmge d0, d16, d17",
"fcmgt d1, d17, d16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
"orr v2.8b, v0.8b, v1.8b",
"mvn v2.8b, v2.8b",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 4": {
@@ -465,9 +465,9 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d4, d16, d17",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
"fcmeq d2, d16, d17",
"mvn v2.8b, v2.8b",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 5": {
@@ -478,9 +478,9 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmgt d4, d17, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
"fcmgt d2, d17, d16",
"mvn v2.16b, v2.16b",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 6": {
@@ -491,9 +491,9 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge d4, d17, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
"fcmge d2, d17, d16",
"mvn v2.16b, v2.16b",
"mov v16.d[0], v2.d[0]"
]
},
"cmpsd xmm0, xmm1, 7": {
@@ -506,8 +506,8 @@
"ExpectedArm64ASM": [
"fcmge d0, d16, d17",
"fcmgt d1, d17, d16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.d[0], v4.d[0]"
"orr v2.8b, v0.8b, v1.8b",
"mov v16.d[0], v2.d[0]"
]
},
"addsubps xmm0, xmm1": {
@@ -516,9 +516,9 @@
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1568]",
"ldr q4, [x0]",
"eor v4.16b, v17.16b, v4.16b",
"fadd v16.4s, v16.4s, v4.4s"
"ldr q2, [x0]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
},
"movdq2q mm0, xmm0": {
@@ -534,8 +534,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"fcvtn v4.2s, v17.2d",
"frinti v16.4s, v4.4s",
"fcvtn v2.2s, v17.2d",
"frinti v16.4s, v2.4s",
"fcvtzs v16.4s, v16.4s"
]
},
unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+2 -2
View File
@@ -15,8 +15,8 @@
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"rev64 v4.4s, v17.4s",
"fcadd v16.4s, v16.4s, v4.4s, #90"
"rev64 v2.4s, v17.4s",
"fcadd v16.4s, v16.4s, v2.4s, #90"
]
}
}
unittests/InstructionCountCI/Secondary_SVE128.json
+58 -58
View File
@@ -14,11 +14,11 @@
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v4.4s, v16.4s, #31",
"index z5.s, #0, #1",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
"ushr v2.4s, v16.4s, #31",
"index z3.s, #0, #1",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
]
},
"movmskps rax, xmm0": {
@@ -26,11 +26,11 @@
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v4.4s, v16.4s, #31",
"index z5.s, #0, #1",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
"ushr v2.4s, v16.4s, #31",
"index z3.s, #0, #1",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
]
},
"psrlw mm0, mm1": {
@@ -38,12 +38,12 @@
"Optimal": "No",
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsr z4.h, p6/m, z4.h, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsr z2.h, p6/m, z2.h, z0.d",
"str d2, [x28, #752]"
]
},
"psrld mm0, mm1": {
@@ -51,12 +51,12 @@
"Optimal": "No",
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsr z4.s, p6/m, z4.s, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsr z2.s, p6/m, z2.s, z0.d",
"str d2, [x28, #752]"
]
},
"psrlq mm0, mm1": {
@@ -64,12 +64,12 @@
"Optimal": "No",
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsr z4.d, p6/m, z4.d, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsr z2.d, p6/m, z2.d, z0.d",
"str d2, [x28, #752]"
]
},
"psraw mm0, mm1": {
@@ -77,12 +77,12 @@
"Optimal": "No",
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"asr z4.h, p6/m, z4.h, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"asr z2.h, p6/m, z2.h, z0.d",
"str d2, [x28, #752]"
]
},
"psrad mm0, mm1": {
@@ -90,12 +90,12 @@
"Optimal": "No",
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"asr z4.s, p6/m, z4.s, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"asr z2.s, p6/m, z2.s, z0.d",
"str d2, [x28, #752]"
]
},
"psllw mm0, mm1": {
@@ -103,12 +103,12 @@
"Optimal": "No",
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsl z4.h, p6/m, z4.h, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsl z2.h, p6/m, z2.h, z0.d",
"str d2, [x28, #752]"
]
},
"pslld mm0, mm1": {
@@ -116,12 +116,12 @@
"Optimal": "No",
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsl z4.s, p6/m, z4.s, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsl z2.s, p6/m, z2.s, z0.d",
"str d2, [x28, #752]"
]
},
"psllq mm0, mm1": {
@@ -129,12 +129,12 @@
"Optimal": "No",
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"mov z0.d, d4",
"movprfx z4, z5",
"lsl z4.d, p6/m, z4.d, z0.d",
"str d4, [x28, #752]"
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"mov z0.d, d2",
"movprfx z2, z3",
"lsl z2.d, p6/m, z2.d, z0.d",
"str d2, [x28, #752]"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+2422 -2422
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map1_FCMA.json
+22 -22
View File
@@ -16,12 +16,12 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"ext v5.16b, v5.16b, v5.16b, #8",
"fcadd v4.2d, v4.2d, v5.2d, #90",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"ext v3.16b, v3.16b, v3.16b, #8",
"fcadd v2.2d, v2.2d, v3.2d, #90",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vaddsubpd ymm0, ymm1, ymm2": {
@@ -31,11 +31,11 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"ext z5.b, z5.b, z5.b, #8",
"fcadd z4.d, p7/m, z4.d, z5.d, #90",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"ext z3.b, z3.b, z3.b, #8",
"fcadd z2.d, p7/m, z2.d, z3.d, #90",
"mov z16.d, p7/m, z2.d"
]
},
"vaddsubps xmm0, xmm1, xmm2": {
@@ -45,12 +45,12 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"rev64 v5.4s, v5.4s",
"fcadd v4.4s, v4.4s, v5.4s, #90",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"rev64 v3.4s, v3.4s",
"fcadd v2.4s, v2.4s, v3.4s, #90",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vaddsubps ymm0, ymm1, ymm2": {
@@ -60,11 +60,11 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"revw z5.d, p7/m, z5.d",
"fcadd z4.s, p7/m, z4.s, z5.s, #90",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"revw z3.d, p7/m, z3.d",
"fcadd z2.s, p7/m, z2.s, z3.s, #90",
"mov z16.d, p7/m, z2.d"
]
}
}
unittests/InstructionCountCI/VEX_map2.json
+878 -878
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map3.json
+2170 -2170
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map_group.json
+200 -200
View File
@@ -14,9 +14,9 @@
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlw xmm0, xmm1, 15": {
@@ -26,10 +26,10 @@
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"ushr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlw xmm0, xmm1, 16": {
@@ -39,10 +39,10 @@
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlw ymm0, ymm1, 0": {
@@ -52,8 +52,8 @@
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlw ymm0, ymm1, 15": {
@@ -63,9 +63,9 @@
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlw ymm0, ymm1, 16": {
@@ -75,9 +75,9 @@
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw xmm0, xmm1, 0": {
@@ -87,9 +87,9 @@
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw xmm0, xmm1, 15": {
@@ -99,10 +99,10 @@
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"sshr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw xmm0, xmm1, 16": {
@@ -112,10 +112,10 @@
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"sshr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw ymm0, ymm1, 0": {
@@ -125,8 +125,8 @@
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw ymm0, ymm1, 15": {
@@ -136,9 +136,9 @@
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"asr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"asr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
]
},
"vpsraw ymm0, ymm1, 16": {
@@ -148,9 +148,9 @@
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"asr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"asr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw xmm0, xmm1, 0": {
@@ -160,9 +160,9 @@
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw xmm0, xmm1, 15": {
@@ -172,10 +172,10 @@
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"shl v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw xmm0, xmm1, 16": {
@@ -185,10 +185,10 @@
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw ymm0, ymm1, 0": {
@@ -198,8 +198,8 @@
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw ymm0, ymm1, 15": {
@@ -209,9 +209,9 @@
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsl z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsl z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllw ymm0, ymm1, 16": {
@@ -221,9 +221,9 @@
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld xmm0, xmm1, 0": {
@@ -233,9 +233,9 @@
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld xmm0, xmm1, 31": {
@@ -245,10 +245,10 @@
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"ushr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld xmm0, xmm1, 32": {
@@ -258,10 +258,10 @@
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld ymm0, ymm1, 0": {
@@ -271,8 +271,8 @@
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld ymm0, ymm1, 31": {
@@ -282,9 +282,9 @@
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrld ymm0, ymm1, 32": {
@@ -294,9 +294,9 @@
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad xmm0, xmm1, 0": {
@@ -306,9 +306,9 @@
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad xmm0, xmm1, 31": {
@@ -318,10 +318,10 @@
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"sshr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad xmm0, xmm1, 32": {
@@ -331,10 +331,10 @@
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"sshr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad ymm0, ymm1, 0": {
@@ -344,8 +344,8 @@
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad ymm0, ymm1, 31": {
@@ -355,9 +355,9 @@
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"asr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"asr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrad ymm0, ymm1, 32": {
@@ -367,9 +367,9 @@
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"asr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"asr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld xmm0, xmm1, 0": {
@@ -379,9 +379,9 @@
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld xmm0, xmm1, 31": {
@@ -391,10 +391,10 @@
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"shl v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld xmm0, xmm1, 32": {
@@ -404,10 +404,10 @@
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld ymm0, ymm1, 0": {
@@ -417,8 +417,8 @@
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld ymm0, ymm1, 31": {
@@ -428,9 +428,9 @@
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsl z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsl z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
]
},
"vpslld ymm0, ymm1, 32": {
@@ -440,9 +440,9 @@
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq xmm0, xmm1, 0": {
@@ -452,9 +452,9 @@
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq xmm0, xmm1, 63": {
@@ -464,10 +464,10 @@
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.2d, v4.2d, #63",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"ushr v2.2d, v2.2d, #63",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq xmm0, xmm1, 64": {
@@ -477,10 +477,10 @@
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq ymm0, ymm1, 0": {
@@ -490,8 +490,8 @@
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq ymm0, ymm1, 63": {
@@ -501,9 +501,9 @@
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsr z4.d, p7/m, z4.d, #63",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsr z2.d, p7/m, z2.d, #63",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrlq ymm0, ymm1, 64": {
@@ -513,9 +513,9 @@
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq xmm0, xmm1, 0": {
@@ -525,9 +525,9 @@
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq xmm0, xmm1, 15": {
@@ -537,11 +537,11 @@
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v4.16b, v4.16b, v5.16b, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v2.16b, v2.16b, v3.16b, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq xmm0, xmm1, 16": {
@@ -551,9 +551,9 @@
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq ymm0, ymm1, 0": {
@@ -563,8 +563,8 @@
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq ymm0, ymm1, 15": {
@@ -574,15 +574,15 @@
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v6.16b, v4.16b, v5.16b, #15",
"ext z4.b, z4.b, z5.b, #31",
"mov z1.q, q4",
"mov z4.d, z6.d",
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v4.16b, v2.16b, v3.16b, #15",
"ext z2.b, z2.b, z3.b, #31",
"mov z1.q, q2",
"mov z2.d, z4.d",
"not p0.b, p7/z, p6.b",
"mov z4.b, p0/m, z1.b",
"mov z16.d, p7/m, z4.d"
"mov z2.b, p0/m, z1.b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq ymm0, ymm1, 16": {
@@ -592,8 +592,8 @@
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq xmm0, xmm1, 0": {
@@ -603,9 +603,9 @@
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq xmm0, xmm1, 63": {
@@ -615,10 +615,10 @@
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.2d, v4.2d, #63",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"shl v2.2d, v2.2d, #63",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq xmm0, xmm1, 64": {
@@ -628,10 +628,10 @@
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq ymm0, ymm1, 0": {
@@ -641,8 +641,8 @@
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq ymm0, ymm1, 63": {
@@ -652,9 +652,9 @@
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"lsl z4.d, p7/m, z4.d, #63",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"lsl z2.d, p7/m, z2.d, #63",
"mov z16.d, p7/m, z2.d"
]
},
"vpsllq ymm0, ymm1, 64": {
@@ -664,9 +664,9 @@
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq xmm0, xmm1, 0": {
@@ -676,9 +676,9 @@
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq xmm0, xmm1, 15": {
@@ -688,11 +688,11 @@
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v4.16b, v5.16b, v4.16b, #1",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v2.16b, v3.16b, v2.16b, #1",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq xmm0, xmm1, 16": {
@@ -702,9 +702,9 @@
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq ymm0, ymm1, 0": {
@@ -714,8 +714,8 @@
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq ymm0, ymm1, 15": {
@@ -725,17 +725,17 @@
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v6.16b, v5.16b, v4.16b, #1",
"movprfx z1, z5",
"ext z1.b, z1.b, z4.b, #17",
"mov z4.d, z1.d",
"mov z1.q, q4",
"mov z4.d, z6.d",
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v4.16b, v3.16b, v2.16b, #1",
"movprfx z1, z3",
"ext z1.b, z1.b, z2.b, #17",
"mov z2.d, z1.d",
"mov z1.q, q2",
"mov z2.d, z4.d",
"not p0.b, p7/z, p6.b",
"mov z4.b, p0/m, z1.b",
"mov z16.d, p7/m, z4.d"
"mov z2.b, p0/m, z1.b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq ymm0, ymm1, 16": {
@@ -745,8 +745,8 @@
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
]
},
"vldmxcsr [rax]": {
unittests/InstructionCountCI/x87.json
+4186 -3562
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