diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
index 4cdc2725c..25e89b8fe 100644
--- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
@@ -66,11 +66,11 @@ namespace x64 {
   };
 
   //  v8..v15 = (lower 64bits) Callee saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 12> RAFPR = {
-    // v0 ~ v3 are used as temps.
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> RAFPR = {
+    // v0 ~ v1 are used as temps.
     // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
-    // FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
 
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
     FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
     FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
     FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
@@ -127,11 +127,11 @@ namespace x32 {
   };
 
   //  v8..v15 = (lower 64bits) Callee saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 20> RAFPR = {
-    // v0 ~ v3 are used as temps.
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 22> RAFPR = {
+    // v0 ~ v1 are used as temps.
     // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
-    // FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
 
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
     FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
     FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
     FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
@@ -545,8 +545,19 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
   // rsp capable move
   add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);
 
+  LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 2 == 0, "Needs to have multiple of 2 FPRs for RA");
+
   if (CanUseSVE) {
-    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+    size_t i = 0;
+
+    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      st2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B, TmpReg, 0);
+      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 2);
+    }
+
+    for (; i < GeneralFPRegisters.size(); i += 4) {
       const auto Reg1 = GeneralFPRegisters[i];
       const auto Reg2 = GeneralFPRegisters[i + 1];
       const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -555,8 +566,14 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
       add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
     }
   } else {
-    LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 4 == 0, "Needs to have multiple of 4 FPRs for RA");
-    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+    size_t i = 0;
+    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), TmpReg, 32);
+    }
+
+    for (; i < GeneralFPRegisters.size(); i += 4) {
       const auto Reg1 = GeneralFPRegisters[i];
       const auto Reg2 = GeneralFPRegisters[i + 1];
       const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -578,7 +595,15 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
 
   if (CanUseSVE) {
-    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+    size_t i = 0;
+    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      ld2b(Reg1.Z(), Reg2.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 2);
+    }
+
+    for (; i < GeneralFPRegisters.size(); i += 4) {
       const auto Reg1 = GeneralFPRegisters[i];
       const auto Reg2 = GeneralFPRegisters[i + 1];
       const auto Reg3 = GeneralFPRegisters[i + 2];
@@ -587,7 +612,14 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
       add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
     }
   } else {
-    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+    size_t i = 0;
+    for (; i < (GeneralFPRegisters.size() % 4); i += 2) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), ARMEmitter::Reg::rsp, 32);
+    }
+
+    for (; i < GeneralFPRegisters.size(); i += 4) {
       const auto Reg1 = GeneralFPRegisters[i];
       const auto Reg2 = GeneralFPRegisters[i + 1];
       const auto Reg3 = GeneralFPRegisters[i + 2];
diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
index 8a39b9be0..14357394e 100644
--- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
+++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
@@ -42,8 +42,6 @@ constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
 // Vector temporaries
 constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
 constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
-constexpr auto VTMP3 = FEXCore::ARMEmitter::VReg::v2;
-constexpr auto VTMP4 = FEXCore::ARMEmitter::VReg::v3;
 
 // Predicate register temporaries (used when AVX support is enabled)
 // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json
index 1b7d3af10..fe91498e6 100644
--- a/unittests/InstructionCountCI/DDD.json
+++ b/unittests/InstructionCountCI/DDD.json
@@ -23,11 +23,11 @@
         "0x0f 0x0f 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "mov v4.h[1], v4.h[2]",
-        "sxtl v4.4s, v4.4h",
-        "scvtf v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "mov v2.h[1], v2.h[2]",
+        "sxtl v2.4s, v2.4h",
+        "scvtf v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "pi2fd mm0, mm1": {
@@ -39,9 +39,9 @@
         "0x0f 0x0f 0x0d"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "scvtf v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "scvtf v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "pf2iw mm0, mm1": {
@@ -54,11 +54,11 @@
         "0x0f 0x0f 0x1c"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "fcvtzs v4.2s, v4.2s",
-        "mov v4.h[1], v4.h[2]",
-        "sxtl v4.4s, v4.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "fcvtzs v2.2s, v2.2s",
+        "mov v2.h[1], v2.h[2]",
+        "sxtl v2.4s, v2.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "pf2id mm0, mm1": {
@@ -70,9 +70,9 @@
         "0x0f 0x0f 0x1d"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcpv mm0, mm1": {
@@ -83,10 +83,10 @@
         "0x0f 0x0f 0x86"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
+        "ldr d2, [x28, #768]",
         "fmov v0.4s, #0x70 (1.0000)",
-        "fdiv v4.4s, v0.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "fdiv v2.4s, v0.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrsqrtv mm0, mm1": {
@@ -97,11 +97,11 @@
         "0x0f 0x0f 0x87"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
+        "ldr d2, [x28, #768]",
         "fmov v0.4s, #0x70 (1.0000)",
-        "fsqrt v1.4s, v4.4s",
-        "fdiv v4.4s, v0.4s, v1.4s",
-        "str d4, [x28, #752]"
+        "fsqrt v1.4s, v2.4s",
+        "fdiv v2.4s, v0.4s, v1.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfnacc mm0, mm1": {
@@ -109,12 +109,12 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x8a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uzp1 v6.2s, v4.2s, v5.2s",
-        "uzp2 v4.2s, v4.2s, v5.2s",
-        "fsub v4.4s, v6.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uzp1 v4.2s, v2.2s, v3.2s",
+        "uzp2 v2.2s, v2.2s, v3.2s",
+        "fsub v2.4s, v4.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfpnacc mm0, mm1": {
@@ -122,13 +122,13 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x8e",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "dup v6.4s, v4.s[1]",
-        "fsub s4, s4, s6",
-        "faddp v5.4s, v5.4s, v5.4s",
-        "mov v4.s[1], v5.s[0]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "dup v4.4s, v2.s[1]",
+        "fsub s2, s2, s4",
+        "faddp v3.4s, v3.4s, v3.4s",
+        "mov v2.s[1], v3.s[0]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfcmpge mm0, mm1": {
@@ -136,10 +136,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x90",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fcmge v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fcmge v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfmin mm0, mm1": {
@@ -147,11 +147,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x94",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fcmgt v0.4s, v5.4s, v4.4s",
-        "bif v4.16b, v5.16b, v0.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fcmgt v0.4s, v3.4s, v2.4s",
+        "bif v2.16b, v3.16b, v0.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcp mm0, mm1": {
@@ -162,11 +162,11 @@
         "0x0f 0x0f 0x96"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
+        "ldr d2, [x28, #768]",
         "fmov s0, #0x70 (1.0000)",
-        "fdiv s4, s0, s4",
-        "dup v4.4s, v4.s[0]",
-        "str d4, [x28, #752]"
+        "fdiv s2, s0, s2",
+        "dup v2.4s, v2.s[0]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrsqrt mm0, mm1": {
@@ -177,12 +177,12 @@
         "0x0f 0x0f 0x97"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
+        "ldr d2, [x28, #768]",
         "fmov s0, #0x70 (1.0000)",
-        "fsqrt s1, s4",
-        "fdiv s4, s0, s1",
-        "dup v4.4s, v4.s[0]",
-        "str d4, [x28, #752]"
+        "fsqrt s1, s2",
+        "fdiv s2, s0, s1",
+        "dup v2.4s, v2.s[0]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfsub mm0, mm1": {
@@ -190,10 +190,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x9a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fsub v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fsub v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfadd mm0, mm1": {
@@ -201,10 +201,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0x9e",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fadd v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fadd v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfcmpgt mm0, mm1": {
@@ -212,10 +212,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xa0",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fcmgt v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fcmgt v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfmax mm0, mm1": {
@@ -223,11 +223,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xa4",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fcmgt v0.4s, v5.4s, v4.4s",
-        "bit v4.16b, v5.16b, v0.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fcmgt v0.4s, v3.4s, v2.4s",
+        "bit v2.16b, v3.16b, v0.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcpit1 mm0, mm1": {
@@ -235,8 +235,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xa6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcpit1 mm0, mm0": {
@@ -244,8 +244,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0x0f 0xa6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrsqit1 mm0, mm1": {
@@ -253,8 +253,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xa7",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrsqit1 mm0, mm0": {
@@ -262,8 +262,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0x0f 0xa7",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfsubr mm0, mm1": {
@@ -271,10 +271,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xaa",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fsub v4.4s, v4.4s, v5.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fsub v2.4s, v2.4s, v3.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfcmpeq mm0, mm1": {
@@ -282,10 +282,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xb0",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fcmeq v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fcmeq v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfmul mm0, mm1": {
@@ -293,10 +293,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xb4",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "fmul v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "fmul v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcpit2 mm0, mm1": {
@@ -304,8 +304,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xb6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "str d2, [x28, #752]"
       ]
     },
     "pfrcpit2 mm0, mm0": {
@@ -313,8 +313,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0x0f 0xb6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x28, #752]"
       ]
     },
     "db 0x0f, 0x0f, 0xc1, 0xb7": {
@@ -327,14 +327,14 @@
         "0x0f 0x0f 0xb7"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "smull v4.4s, v4.4h, v5.4h",
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "smull v2.4s, v2.4h, v3.4h",
         "mov x20, #0x800000008000",
-        "dup v5.2d, x20",
-        "add v4.4s, v4.4s, v5.4s",
-        "shrn v4.4h, v4.4s, #16",
-        "str d4, [x28, #752]"
+        "dup v3.2d, x20",
+        "add v2.4s, v2.4s, v3.4s",
+        "shrn v2.4h, v2.4s, #16",
+        "str d2, [x28, #752]"
       ]
     },
     "pswapd mm0, mm1": {
@@ -342,9 +342,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xbb",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "rev64 v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "rev64 v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "pavgusb mm0, mm1": {
@@ -352,10 +352,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x0f 0xbf",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "urhadd v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "urhadd v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 9fa7adbe0..30769c8f1 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -15,12 +15,12 @@
         "NP 0x0f 0x38 0x00"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "movi v6.16b, #0x87",
-        "and v5.16b, v5.16b, v6.16b",
-        "tbl v4.8b, {v4.16b}, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "movi v4.16b, #0x87",
+        "and v3.16b, v3.16b, v4.16b",
+        "tbl v2.8b, {v2.16b}, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufb xmm0, xmm1": {
@@ -30,9 +30,9 @@
         "0x66 0x0f 0x38 0x00"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.16b, #0x8f",
-        "and v4.16b, v17.16b, v4.16b",
-        "tbl v16.16b, {v16.16b}, v4.16b"
+        "movi v2.16b, #0x8f",
+        "and v2.16b, v17.16b, v2.16b",
+        "tbl v16.16b, {v16.16b}, v2.16b"
       ]
     },
     "phaddw mm0, mm1": {
@@ -42,10 +42,10 @@
         "NP 0x0f 0x38 0x01"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "addp v4.4h, v5.4h, v4.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "addp v2.4h, v3.4h, v2.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "phaddw xmm0, xmm1": {
@@ -65,10 +65,10 @@
         "NP 0x0f 0x38 0x02"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "addp v4.2s, v5.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "addp v2.2s, v3.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "phaddd xmm0, xmm1": {
@@ -88,12 +88,12 @@
         "NP 0x0f 0x38 0x03"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uzp1 v6.4h, v4.4h, v5.4h",
-        "uzp2 v4.4h, v4.4h, v5.4h",
-        "sqadd v4.8h, v6.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uzp1 v4.4h, v2.4h, v3.4h",
+        "uzp2 v2.4h, v2.4h, v3.4h",
+        "sqadd v2.8h, v4.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "phaddsw xmm0, xmm1": {
@@ -103,9 +103,9 @@
         "0x66 0x0f 0x38 0x03"
       ],
       "ExpectedArm64ASM": [
-        "uzp1 v4.8h, v16.8h, v17.8h",
-        "uzp2 v5.8h, v16.8h, v17.8h",
-        "sqadd v16.8h, v4.8h, v5.8h"
+        "uzp1 v2.8h, v16.8h, v17.8h",
+        "uzp2 v3.8h, v16.8h, v17.8h",
+        "sqadd v16.8h, v2.8h, v3.8h"
       ]
     },
     "pmaddubsw mm0, mm1": {
@@ -115,15 +115,15 @@
         "NP 0x0f 0x38 0x04"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uxtl v4.8h, v4.8b",
-        "sxtl v5.8h, v5.8b",
-        "smull v6.4s, v4.4h, v5.4h",
-        "smull2 v4.4s, v4.8h, v5.8h",
-        "addp v4.4s, v6.4s, v4.4s",
-        "sqxtn v4.4h, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uxtl v2.8h, v2.8b",
+        "sxtl v3.8h, v3.8b",
+        "smull v4.4s, v2.4h, v3.4h",
+        "smull2 v2.4s, v2.8h, v3.8h",
+        "addp v2.4s, v4.4s, v2.4s",
+        "sqxtn v2.4h, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pmaddubsw xmm0, xmm1": {
@@ -137,15 +137,15 @@
         "0x66 0x0f 0x38 0x04"
       ],
       "ExpectedArm64ASM": [
-        "uxtl v4.8h, v16.8b",
-        "sxtl v5.8h, v17.8b",
-        "mul v4.8h, v4.8h, v5.8h",
-        "uxtl2 v5.8h, v16.16b",
-        "sxtl2 v6.8h, v17.16b",
-        "mul v5.8h, v5.8h, v6.8h",
-        "uzp1 v6.8h, v4.8h, v5.8h",
-        "uzp2 v4.8h, v4.8h, v5.8h",
-        "sqadd v16.8h, v6.8h, v4.8h"
+        "uxtl v2.8h, v16.8b",
+        "sxtl v3.8h, v17.8b",
+        "mul v2.8h, v2.8h, v3.8h",
+        "uxtl2 v3.8h, v16.16b",
+        "sxtl2 v4.8h, v17.16b",
+        "mul v3.8h, v3.8h, v4.8h",
+        "uzp1 v4.8h, v2.8h, v3.8h",
+        "uzp2 v2.8h, v2.8h, v3.8h",
+        "sqadd v16.8h, v4.8h, v2.8h"
       ]
     },
     "phsubw mm0, mm1": {
@@ -155,12 +155,12 @@
         "NP 0x0f 0x38 0x05"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uzp1 v6.4h, v4.4h, v5.4h",
-        "uzp2 v4.4h, v4.4h, v5.4h",
-        "sub v4.8h, v6.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uzp1 v4.4h, v2.4h, v3.4h",
+        "uzp2 v2.4h, v2.4h, v3.4h",
+        "sub v2.8h, v4.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "phsubw xmm0, xmm1": {
@@ -170,9 +170,9 @@
         "0x66 0x0f 0x38 0x05"
       ],
       "ExpectedArm64ASM": [
-        "uzp1 v4.8h, v16.8h, v17.8h",
-        "uzp2 v5.8h, v16.8h, v17.8h",
-        "sub v16.8h, v4.8h, v5.8h"
+        "uzp1 v2.8h, v16.8h, v17.8h",
+        "uzp2 v3.8h, v16.8h, v17.8h",
+        "sub v16.8h, v2.8h, v3.8h"
       ]
     },
     "phsubd mm0, mm1": {
@@ -182,12 +182,12 @@
         "NP 0x0f 0x38 0x06"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uzp1 v6.2s, v4.2s, v5.2s",
-        "uzp2 v4.2s, v4.2s, v5.2s",
-        "sub v4.4s, v6.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uzp1 v4.2s, v2.2s, v3.2s",
+        "uzp2 v2.2s, v2.2s, v3.2s",
+        "sub v2.4s, v4.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "phsubd xmm0, xmm1": {
@@ -197,9 +197,9 @@
         "0x66 0x0f 0x38 0x06"
       ],
       "ExpectedArm64ASM": [
-        "uzp1 v4.4s, v16.4s, v17.4s",
-        "uzp2 v5.4s, v16.4s, v17.4s",
-        "sub v16.4s, v4.4s, v5.4s"
+        "uzp1 v2.4s, v16.4s, v17.4s",
+        "uzp2 v3.4s, v16.4s, v17.4s",
+        "sub v16.4s, v2.4s, v3.4s"
       ]
     },
     "phsubsw mm0, mm1": {
@@ -209,12 +209,12 @@
         "NP 0x0f 0x38 0x07"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uzp1 v6.4h, v4.4h, v5.4h",
-        "uzp2 v4.4h, v4.4h, v5.4h",
-        "sqsub v4.8h, v6.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uzp1 v4.4h, v2.4h, v3.4h",
+        "uzp2 v2.4h, v2.4h, v3.4h",
+        "sqsub v2.8h, v4.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "phsubsw xmm0, xmm1": {
@@ -224,9 +224,9 @@
         "0x66 0x0f 0x38 0x07"
       ],
       "ExpectedArm64ASM": [
-        "uzp1 v4.8h, v16.8h, v17.8h",
-        "uzp2 v5.8h, v16.8h, v17.8h",
-        "sqsub v16.8h, v4.8h, v5.8h"
+        "uzp1 v2.8h, v16.8h, v17.8h",
+        "uzp2 v3.8h, v16.8h, v17.8h",
+        "sqsub v16.8h, v2.8h, v3.8h"
       ]
     },
     "psignb mm0, mm1": {
@@ -236,12 +236,12 @@
         "NP 0x0f 0x38 0x08"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqshl v4.8b, v4.8b, #7",
-        "srshr v4.8b, v4.8b, #7",
-        "mul v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqshl v2.8b, v2.8b, #7",
+        "srshr v2.8b, v2.8b, #7",
+        "mul v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psignb xmm0, xmm1": {
@@ -251,9 +251,9 @@
         "0x66 0x0f 0x38 0x08"
       ],
       "ExpectedArm64ASM": [
-        "sqshl v4.16b, v17.16b, #7",
-        "srshr v4.16b, v4.16b, #7",
-        "mul v16.16b, v16.16b, v4.16b"
+        "sqshl v2.16b, v17.16b, #7",
+        "srshr v2.16b, v2.16b, #7",
+        "mul v16.16b, v16.16b, v2.16b"
       ]
     },
     "psignw mm0, mm1": {
@@ -263,12 +263,12 @@
         "NP 0x0f 0x38 0x09"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqshl v4.4h, v4.4h, #15",
-        "srshr v4.4h, v4.4h, #15",
-        "mul v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqshl v2.4h, v2.4h, #15",
+        "srshr v2.4h, v2.4h, #15",
+        "mul v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "psignw xmm0, xmm1": {
@@ -278,9 +278,9 @@
         "0x66 0x0f 0x38 0x09"
       ],
       "ExpectedArm64ASM": [
-        "sqshl v4.8h, v17.8h, #15",
-        "srshr v4.8h, v4.8h, #15",
-        "mul v16.8h, v16.8h, v4.8h"
+        "sqshl v2.8h, v17.8h, #15",
+        "srshr v2.8h, v2.8h, #15",
+        "mul v16.8h, v16.8h, v2.8h"
       ]
     },
     "psignd mm0, mm1": {
@@ -290,12 +290,12 @@
         "NP 0x0f 0x38 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqshl v4.2s, v4.2s, #31",
-        "srshr v4.2s, v4.2s, #31",
-        "mul v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqshl v2.2s, v2.2s, #31",
+        "srshr v2.2s, v2.2s, #31",
+        "mul v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "psignd xmm0, xmm1": {
@@ -305,9 +305,9 @@
         "0x66 0x0f 0x38 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "sqshl v4.4s, v17.4s, #31",
-        "srshr v4.4s, v4.4s, #31",
-        "mul v16.4s, v16.4s, v4.4s"
+        "sqshl v2.4s, v17.4s, #31",
+        "srshr v2.4s, v2.4s, #31",
+        "mul v16.4s, v16.4s, v2.4s"
       ]
     },
     "pmulhrsw mm0, mm1": {
@@ -318,14 +318,14 @@
         "NP 0x0f 0x38 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "smull v4.4s, v4.4h, v5.4h",
-        "sshr v4.4s, v4.4s, #14",
-        "movi v5.4s, #0x1, lsl #0",
-        "add v4.4s, v4.4s, v5.4s",
-        "shrn v4.4h, v4.4s, #1",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "smull v2.4s, v2.4h, v3.4h",
+        "sshr v2.4s, v2.4s, #14",
+        "movi v3.4s, #0x1, lsl #0",
+        "add v2.4s, v2.4s, v3.4s",
+        "shrn v2.4h, v2.4s, #1",
+        "str d2, [x28, #752]"
       ]
     },
     "pmulhrsw xmm0, xmm1": {
@@ -336,16 +336,16 @@
         "0x66 0x0f 0x38 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "smull v4.4s, v16.4h, v17.4h",
-        "smull2 v5.4s, v16.8h, v17.8h",
-        "sshr v4.4s, v4.4s, #14",
-        "sshr v5.4s, v5.4s, #14",
-        "movi v6.4s, #0x1, lsl #0",
-        "add v4.4s, v4.4s, v6.4s",
-        "add v5.4s, v5.4s, v6.4s",
-        "shrn v4.4h, v4.4s, #1",
-        "mov v0.16b, v4.16b",
-        "shrn2 v0.8h, v5.4s, #1",
+        "smull v2.4s, v16.4h, v17.4h",
+        "smull2 v3.4s, v16.8h, v17.8h",
+        "sshr v2.4s, v2.4s, #14",
+        "sshr v3.4s, v3.4s, #14",
+        "movi v4.4s, #0x1, lsl #0",
+        "add v2.4s, v2.4s, v4.4s",
+        "add v3.4s, v3.4s, v4.4s",
+        "shrn v2.4h, v2.4s, #1",
+        "mov v0.16b, v2.16b",
+        "shrn2 v0.8h, v3.4s, #1",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -356,8 +356,8 @@
         "0x66 0x0f 0x38 0x10"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.16b, v16.16b, #7",
-        "bit v16.16b, v17.16b, v4.16b"
+        "sshr v2.16b, v16.16b, #7",
+        "bit v16.16b, v17.16b, v2.16b"
       ]
     },
     "blendvps xmm0, xmm1": {
@@ -367,8 +367,8 @@
         "0x66 0x0f 0x38 0x14"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.4s, v16.4s, #31",
-        "bit v16.16b, v17.16b, v4.16b"
+        "sshr v2.4s, v16.4s, #31",
+        "bit v16.16b, v17.16b, v2.16b"
       ]
     },
     "blendvpd xmm0, xmm1": {
@@ -378,8 +378,8 @@
         "0x66 0x0f 0x38 0x15"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.2d, v16.2d, #63",
-        "bit v16.16b, v17.16b, v4.16b"
+        "sshr v2.2d, v16.2d, #63",
+        "bit v16.16b, v17.16b, v2.16b"
       ]
     },
     "pblendvb xmm1, xmm2": {
@@ -389,8 +389,8 @@
         "0x66 0x0f 0x38 0x10"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.16b, v16.16b, #7",
-        "bit v17.16b, v18.16b, v4.16b"
+        "sshr v2.16b, v16.16b, #7",
+        "bit v17.16b, v18.16b, v2.16b"
       ]
     },
     "blendvps xmm1, xmm2": {
@@ -400,8 +400,8 @@
         "0x66 0x0f 0x38 0x14"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.4s, v16.4s, #31",
-        "bit v17.16b, v18.16b, v4.16b"
+        "sshr v2.4s, v16.4s, #31",
+        "bit v17.16b, v18.16b, v2.16b"
       ]
     },
     "blendvpd xmm1, xmm2": {
@@ -411,8 +411,8 @@
         "0x66 0x0f 0x38 0x15"
       ],
       "ExpectedArm64ASM": [
-        "sshr v4.2d, v16.2d, #63",
-        "bit v17.16b, v18.16b, v4.16b"
+        "sshr v2.2d, v16.2d, #63",
+        "bit v17.16b, v18.16b, v2.16b"
       ]
     },
     "ptest xmm0, xmm1": {
@@ -422,14 +422,14 @@
         "0x66 0x0f 0x38 0x17"
       ],
       "ExpectedArm64ASM": [
-        "and v4.16b, v16.16b, v17.16b",
-        "bic v5.16b, v17.16b, v16.16b",
-        "cnt v4.16b, v4.16b",
-        "cnt v5.16b, v5.16b",
-        "addv h4, v4.8h",
-        "addv h5, v5.8h",
-        "umov w20, v4.h[0]",
-        "umov w21, v5.h[0]",
+        "and v2.16b, v16.16b, v17.16b",
+        "bic v3.16b, v17.16b, v16.16b",
+        "cnt v2.16b, v2.16b",
+        "cnt v3.16b, v3.16b",
+        "addv h2, v2.8h",
+        "addv h3, v3.8h",
+        "umov w20, v2.h[0]",
+        "umov w21, v3.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -452,9 +452,9 @@
         "NP 0x0f 0x38 0x1c"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "abs v4.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "abs v2.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pabsb xmm0, xmm1": {
@@ -474,9 +474,9 @@
         "NP 0x0f 0x38 0x1d"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "abs v4.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "abs v2.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pabsw xmm0, xmm1": {
@@ -496,9 +496,9 @@
         "NP 0x0f 0x38 0x1e"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "abs v4.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "abs v2.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pabsd xmm0, xmm1": {
@@ -528,8 +528,8 @@
         "0x66 0x0f 0x38 0x31"
       ],
       "ExpectedArm64ASM": [
-        "uxtl v4.8h, v17.8b",
-        "uxtl v16.4s, v4.4h"
+        "uxtl v2.8h, v17.8b",
+        "uxtl v16.4s, v2.4h"
       ]
     },
     "pmovzxbq xmm0, xmm1": {
@@ -539,9 +539,9 @@
         "0x66 0x0f 0x38 0x32"
       ],
       "ExpectedArm64ASM": [
-        "uxtl v4.8h, v17.8b",
-        "uxtl v4.4s, v4.4h",
-        "uxtl v16.2d, v4.2s"
+        "uxtl v2.8h, v17.8b",
+        "uxtl v2.4s, v2.4h",
+        "uxtl v16.2d, v2.2s"
       ]
     },
     "pmovzxwd xmm0, xmm1": {
@@ -561,8 +561,8 @@
         "0x66 0x0f 0x38 0x34"
       ],
       "ExpectedArm64ASM": [
-        "uxtl v4.4s, v17.4h",
-        "uxtl v16.2d, v4.2s"
+        "uxtl v2.4s, v17.4h",
+        "uxtl v16.2d, v2.2s"
       ]
     },
     "pmovzxdq xmm0, xmm1": {
@@ -683,12 +683,12 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1552]",
-        "ldr q4, [x0]",
-        "zip1 v5.8h, v4.8h, v17.8h",
-        "zip2 v4.8h, v4.8h, v17.8h",
-        "umin v4.4s, v5.4s, v4.4s",
-        "uminv s4, v4.4s",
-        "rev32 v16.8h, v4.8h"
+        "ldr q2, [x0]",
+        "zip1 v3.8h, v2.8h, v17.8h",
+        "zip2 v2.8h, v2.8h, v17.8h",
+        "umin v2.4s, v3.4s, v2.4s",
+        "uminv s2, v2.4s",
+        "rev32 v16.8h, v2.8h"
       ]
     },
     "sha1nexte xmm0, xmm1": {
@@ -713,8 +713,8 @@
         "0x66 0x0f 0x38 0xc9"
       ],
       "ExpectedArm64ASM": [
-        "ext v4.16b, v17.16b, v16.16b, #8",
-        "eor v16.16b, v16.16b, v4.16b"
+        "ext v2.16b, v17.16b, v16.16b, #8",
+        "eor v16.16b, v16.16b, v2.16b"
       ]
     },
     "sha1msg2 xmm0, xmm1": {
@@ -739,11 +739,11 @@
         "mov w23, v16.s[0]",
         "eor w23, w23, w20",
         "ror w23, w23, #31",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w20",
-        "mov v4.s[2], w21",
-        "mov v4.s[1], w22",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w20",
+        "mov v2.s[2], w21",
+        "mov v2.s[1], w22",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w23"
       ]
     },
@@ -853,11 +853,11 @@
         "add w21, w21, w23",
         "ldr w23, [sp, #128]",
         "add w21, w21, w23",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w20",
-        "mov v4.s[2], w24",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w20",
+        "mov v2.s[2], w24",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w22",
         "add sp, sp, #0x120 (288)"
       ]
@@ -898,11 +898,11 @@
         "lsr w23, w23, #3",
         "eor w23, w25, w23",
         "add w23, w24, w23",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w20",
-        "mov v4.s[2], w21",
-        "mov v4.s[1], w22",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w20",
+        "mov v2.s[2], w21",
+        "mov v2.s[1], w22",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w23"
       ]
     },
@@ -943,11 +943,11 @@
         "lsr w25, w21, #10",
         "eor w24, w24, w25",
         "add w23, w23, w24",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w23",
-        "mov v4.s[2], w22",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w23",
+        "mov v2.s[2], w22",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w20"
       ]
     },
@@ -968,7 +968,7 @@
         "0x66 0x0f 0x38 0xdc"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
+        "movi v2.2d, #0x0",
         "unimplemented (Unimplemented)",
         "unimplemented (Unimplemented)",
         "eor v16.16b, v16.16b, v17.16b"
@@ -981,7 +981,7 @@
         "0x66 0x0f 0x38 0xdd"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
+        "movi v2.2d, #0x0",
         "unimplemented (Unimplemented)",
         "eor v16.16b, v16.16b, v17.16b"
       ]
@@ -993,7 +993,7 @@
         "0x66 0x0f 0x38 0xde"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
+        "movi v2.2d, #0x0",
         "unimplemented (Unimplemented)",
         "unimplemented (Unimplemented)",
         "eor v16.16b, v16.16b, v17.16b"
@@ -1006,7 +1006,7 @@
         "0x66 0x0f 0x38 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
+        "movi v2.2d, #0x0",
         "unimplemented (Unimplemented)",
         "eor v16.16b, v16.16b, v17.16b"
       ]
diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
index 948d0f789..c97ae2551 100644
--- a/unittests/InstructionCountCI/H0F3A.json
+++ b/unittests/InstructionCountCI/H0F3A.json
@@ -19,10 +19,10 @@
         "NP 0x0f 0x3a 0x0f"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "ext v4.8b, v5.8b, v4.8b, #0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "ext v2.8b, v3.8b, v2.8b, #0",
+        "str d2, [x28, #752]"
       ]
     },
     "palignr mm0, mm1, 1": {
@@ -32,10 +32,10 @@
         "NP 0x0f 0x3a 0x0f"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "ext v4.8b, v5.8b, v4.8b, #1",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "ext v2.8b, v3.8b, v2.8b, #1",
+        "str d2, [x28, #752]"
       ]
     },
     "palignr mm0, mm1, 255": {
@@ -45,8 +45,8 @@
         "NP 0x0f 0x3a 0x0f"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "roundps xmm0, xmm1, 00000000b": {
@@ -167,8 +167,8 @@
         "0x66 0x0f 0x3a 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "frintn s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "frintn s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "roundss xmm0, xmm1, 00000001b": {
@@ -179,8 +179,8 @@
         "0x66 0x0f 0x3a 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "frintm s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "frintm s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "roundss xmm0, xmm1, 00000010b": {
@@ -191,8 +191,8 @@
         "0x66 0x0f 0x3a 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "frintp s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "frintp s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "roundss xmm0, xmm1, 00000011b": {
@@ -203,8 +203,8 @@
         "0x66 0x0f 0x3a 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "frintz s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "frintz s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "roundss xmm0, xmm1, 00000100b": {
@@ -215,8 +215,8 @@
         "0x66 0x0f 0x3a 0x0a"
       ],
       "ExpectedArm64ASM": [
-        "frinti s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "frinti s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "roundsd xmm0, xmm1, 00000000b": {
@@ -227,8 +227,8 @@
         "0x66 0x0f 0x3a 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "frintn d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "frintn d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "roundsd xmm0, xmm1, 00000001b": {
@@ -239,8 +239,8 @@
         "0x66 0x0f 0x3a 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "frintm d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "frintm d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "roundsd xmm0, xmm1, 00000010b": {
@@ -251,8 +251,8 @@
         "0x66 0x0f 0x3a 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "frintp d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "frintp d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "roundsd xmm0, xmm1, 00000011b": {
@@ -263,8 +263,8 @@
         "0x66 0x0f 0x3a 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "frintz d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "frintz d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "roundsd xmm0, xmm1, 00000100b": {
@@ -275,8 +275,8 @@
         "0x66 0x0f 0x3a 0x0b"
       ],
       "ExpectedArm64ASM": [
-        "frinti d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "frinti d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "blendps xmm0, xmm1, 0000b": {
@@ -286,8 +286,8 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "mov v4.16b, v16.16b",
-        "mov v16.16b, v4.16b"
+        "mov v2.16b, v16.16b",
+        "mov v16.16b, v2.16b"
       ]
     },
     "blendps xmm0, xmm1, 0001b": {
@@ -319,8 +319,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[1], v17.s[1]",
         "mov v16.16b, v0.16b"
       ]
@@ -344,8 +344,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[2], v17.s[2]",
         "mov v16.16b, v0.16b"
       ]
@@ -359,8 +359,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[1], v17.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[2], v17.s[2]",
         "mov v16.16b, v0.16b"
       ]
@@ -374,9 +374,9 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v17.s[1]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v17.s[1]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[2], v17.s[2]",
         "mov v16.16b, v0.16b"
       ]
@@ -400,8 +400,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -415,8 +415,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[1], v17.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -430,9 +430,9 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v17.s[1]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v17.s[1]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -446,8 +446,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[2], v17.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -461,9 +461,9 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[2], v17.s[2]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v17.s[2]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -477,9 +477,9 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[1], v17.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[2], v17.s[2]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v17.s[2]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -493,10 +493,10 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v17.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v17.s[1]",
-        "mov v4.s[2], v17.s[2]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v17.s[1]",
+        "mov v2.s[2], v17.s[2]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -508,8 +508,8 @@
         "0x66 0x0f 0x3a 0x0d"
       ],
       "ExpectedArm64ASM": [
-        "mov v4.16b, v16.16b",
-        "mov v16.16b, v4.16b"
+        "mov v2.16b, v16.16b",
+        "mov v16.16b, v2.16b"
       ]
     },
     "blendpd xmm0, xmm1, 01b": {
@@ -541,8 +541,8 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.d[0], v17.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v0.16b, v2.16b",
         "mov v0.d[1], v17.d[1]",
         "mov v16.16b, v0.16b"
       ]
@@ -554,8 +554,8 @@
         "0x66 0x0f 0x3a 0x0e"
       ],
       "ExpectedArm64ASM": [
-        "mov v4.16b, v16.16b",
-        "mov v16.16b, v4.16b"
+        "mov v2.16b, v16.16b",
+        "mov v16.16b, v2.16b"
       ]
     },
     "pblendw xmm0, xmm1, 00000001b": {
@@ -577,14 +577,14 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.h[0], v17.h[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.h[1], v17.h[1]",
-        "mov v4.h[2], v17.h[2]",
-        "mov v4.h[3], v17.h[3]",
-        "mov v4.h[4], v17.h[4]",
-        "mov v4.h[5], v17.h[5]",
-        "mov v4.h[6], v17.h[6]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.h[1], v17.h[1]",
+        "mov v2.h[2], v17.h[2]",
+        "mov v2.h[3], v17.h[3]",
+        "mov v2.h[4], v17.h[4]",
+        "mov v2.h[5], v17.h[5]",
+        "mov v2.h[6], v17.h[6]",
+        "mov v0.16b, v2.16b",
         "mov v0.h[7], v17.h[7]",
         "mov v16.16b, v0.16b"
       ]
@@ -856,19 +856,19 @@
         "0x66 0x0f 0x3a 0x40"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "fmul v5.4s, v16.4s, v17.4s",
-        "mov v5.s[0], v4.s[0]",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v5.s[3], v4.s[0]",
-        "faddp v5.4s, v5.4s, v4.4s",
-        "faddp v5.4s, v5.4s, v4.4s",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.s[1], v5.s[0]",
-        "mov v4.s[2], v5.s[0]",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[3], v5.s[0]",
+        "movi v2.2d, #0x0",
+        "fmul v3.4s, v16.4s, v17.4s",
+        "mov v3.s[0], v2.s[0]",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v3.s[3], v2.s[0]",
+        "faddp v3.4s, v3.4s, v2.4s",
+        "faddp v3.4s, v3.4s, v2.4s",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.s[1], v3.s[0]",
+        "mov v2.s[2], v3.s[0]",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[3], v3.s[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -889,15 +889,15 @@
         "0x66 0x0f 0x3a 0x40"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "fmul v5.4s, v16.4s, v17.4s",
-        "faddp v5.4s, v5.4s, v4.4s",
-        "faddp v5.4s, v5.4s, v4.4s",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.s[1], v5.s[0]",
-        "mov v4.s[2], v5.s[0]",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[3], v5.s[0]",
+        "movi v2.2d, #0x0",
+        "fmul v3.4s, v16.4s, v17.4s",
+        "faddp v3.4s, v3.4s, v2.4s",
+        "faddp v3.4s, v3.4s, v2.4s",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.s[1], v3.s[0]",
+        "mov v2.s[2], v3.s[0]",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[3], v3.s[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -918,14 +918,14 @@
         "0x66 0x0f 0x3a 0x41"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "fmul v5.2d, v16.2d, v17.2d",
-        "mov v5.d[0], v4.d[0]",
-        "mov v5.d[1], v4.d[0]",
-        "faddp v5.2d, v5.2d, v4.2d",
-        "mov v4.d[0], v5.d[0]",
-        "mov v0.16b, v4.16b",
-        "mov v0.d[1], v5.d[0]",
+        "movi v2.2d, #0x0",
+        "fmul v3.2d, v16.2d, v17.2d",
+        "mov v3.d[0], v2.d[0]",
+        "mov v3.d[1], v2.d[0]",
+        "faddp v3.2d, v3.2d, v2.2d",
+        "mov v2.d[0], v3.d[0]",
+        "mov v0.16b, v2.16b",
+        "mov v0.d[1], v3.d[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -946,12 +946,12 @@
         "0x66 0x0f 0x3a 0x41"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "fmul v5.2d, v16.2d, v17.2d",
-        "faddp v5.2d, v5.2d, v4.2d",
-        "mov v4.d[0], v5.d[0]",
-        "mov v0.16b, v4.16b",
-        "mov v0.d[1], v5.d[0]",
+        "movi v2.2d, #0x0",
+        "fmul v3.2d, v16.2d, v17.2d",
+        "faddp v3.2d, v3.2d, v2.2d",
+        "mov v2.d[0], v3.d[0]",
+        "mov v0.16b, v2.16b",
+        "mov v0.d[1], v3.d[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -962,20 +962,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[0]",
-        "ext v5.16b, v16.16b, v16.16b, #0",
-        "ext v6.16b, v16.16b, v16.16b, #1",
-        "ext v7.16b, v16.16b, v16.16b, #2",
-        "ext v8.16b, v16.16b, v16.16b, #3",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[0]",
+        "ext v3.16b, v16.16b, v16.16b, #0",
+        "ext v4.16b, v16.16b, v16.16b, #1",
+        "ext v5.16b, v16.16b, v16.16b, #2",
+        "ext v6.16b, v16.16b, v16.16b, #3",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 001b": {
@@ -985,20 +985,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[1]",
-        "ext v5.16b, v16.16b, v16.16b, #0",
-        "ext v6.16b, v16.16b, v16.16b, #1",
-        "ext v7.16b, v16.16b, v16.16b, #2",
-        "ext v8.16b, v16.16b, v16.16b, #3",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[1]",
+        "ext v3.16b, v16.16b, v16.16b, #0",
+        "ext v4.16b, v16.16b, v16.16b, #1",
+        "ext v5.16b, v16.16b, v16.16b, #2",
+        "ext v6.16b, v16.16b, v16.16b, #3",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 010b": {
@@ -1008,20 +1008,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[2]",
-        "ext v5.16b, v16.16b, v16.16b, #0",
-        "ext v6.16b, v16.16b, v16.16b, #1",
-        "ext v7.16b, v16.16b, v16.16b, #2",
-        "ext v8.16b, v16.16b, v16.16b, #3",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[2]",
+        "ext v3.16b, v16.16b, v16.16b, #0",
+        "ext v4.16b, v16.16b, v16.16b, #1",
+        "ext v5.16b, v16.16b, v16.16b, #2",
+        "ext v6.16b, v16.16b, v16.16b, #3",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 011b": {
@@ -1031,20 +1031,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[3]",
-        "ext v5.16b, v16.16b, v16.16b, #0",
-        "ext v6.16b, v16.16b, v16.16b, #1",
-        "ext v7.16b, v16.16b, v16.16b, #2",
-        "ext v8.16b, v16.16b, v16.16b, #3",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[3]",
+        "ext v3.16b, v16.16b, v16.16b, #0",
+        "ext v4.16b, v16.16b, v16.16b, #1",
+        "ext v5.16b, v16.16b, v16.16b, #2",
+        "ext v6.16b, v16.16b, v16.16b, #3",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 100b": {
@@ -1054,20 +1054,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[0]",
-        "ext v5.16b, v16.16b, v16.16b, #4",
-        "ext v6.16b, v16.16b, v16.16b, #5",
-        "ext v7.16b, v16.16b, v16.16b, #6",
-        "ext v8.16b, v16.16b, v16.16b, #7",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[0]",
+        "ext v3.16b, v16.16b, v16.16b, #4",
+        "ext v4.16b, v16.16b, v16.16b, #5",
+        "ext v5.16b, v16.16b, v16.16b, #6",
+        "ext v6.16b, v16.16b, v16.16b, #7",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 101b": {
@@ -1077,20 +1077,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[1]",
-        "ext v5.16b, v16.16b, v16.16b, #4",
-        "ext v6.16b, v16.16b, v16.16b, #5",
-        "ext v7.16b, v16.16b, v16.16b, #6",
-        "ext v8.16b, v16.16b, v16.16b, #7",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[1]",
+        "ext v3.16b, v16.16b, v16.16b, #4",
+        "ext v4.16b, v16.16b, v16.16b, #5",
+        "ext v5.16b, v16.16b, v16.16b, #6",
+        "ext v6.16b, v16.16b, v16.16b, #7",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 110b": {
@@ -1100,20 +1100,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[2]",
-        "ext v5.16b, v16.16b, v16.16b, #4",
-        "ext v6.16b, v16.16b, v16.16b, #5",
-        "ext v7.16b, v16.16b, v16.16b, #6",
-        "ext v8.16b, v16.16b, v16.16b, #7",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[2]",
+        "ext v3.16b, v16.16b, v16.16b, #4",
+        "ext v4.16b, v16.16b, v16.16b, #5",
+        "ext v5.16b, v16.16b, v16.16b, #6",
+        "ext v6.16b, v16.16b, v16.16b, #7",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "mpsadbw xmm0, xmm1, 111b": {
@@ -1123,20 +1123,20 @@
         "0x66 0x0f 0x3a 0x42"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.4s, v17.s[3]",
-        "ext v5.16b, v16.16b, v16.16b, #4",
-        "ext v6.16b, v16.16b, v16.16b, #5",
-        "ext v7.16b, v16.16b, v16.16b, #6",
-        "ext v8.16b, v16.16b, v16.16b, #7",
-        "uabdl v5.8h, v5.8b, v4.8b",
-        "uabdl v6.8h, v6.8b, v4.8b",
-        "uabdl v7.8h, v7.8b, v4.8b",
-        "uabdl v4.8h, v8.8b, v4.8b",
-        "addp v5.8h, v5.8h, v7.8h",
-        "addp v4.8h, v6.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v16.8h, v6.8h, v4.8h"
+        "dup v2.4s, v17.s[3]",
+        "ext v3.16b, v16.16b, v16.16b, #4",
+        "ext v4.16b, v16.16b, v16.16b, #5",
+        "ext v5.16b, v16.16b, v16.16b, #6",
+        "ext v6.16b, v16.16b, v16.16b, #7",
+        "uabdl v3.8h, v3.8b, v2.8b",
+        "uabdl v4.8h, v4.8b, v2.8b",
+        "uabdl v5.8h, v5.8b, v2.8b",
+        "uabdl v2.8h, v6.8b, v2.8b",
+        "addp v3.8h, v3.8h, v5.8h",
+        "addp v2.8h, v4.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v16.8h, v4.8h, v2.8h"
       ]
     },
     "pclmulqdq xmm0, xmm1, 00000b": {
@@ -1240,11 +1240,11 @@
         "add w23, w23, w24",
         "add w23, w23, w26",
         "ror w21, w21, #2",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w23",
-        "mov v4.s[2], w22",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w23",
+        "mov v2.s[2], w22",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w20",
         "add sp, sp, #0x20 (32)"
       ]
@@ -1304,11 +1304,11 @@
         "add w23, w23, w24",
         "add w23, w23, w26",
         "ror w21, w21, #2",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w23",
-        "mov v4.s[2], w22",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w23",
+        "mov v2.s[2], w22",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w20",
         "add sp, sp, #0x20 (32)"
       ]
@@ -1380,11 +1380,11 @@
         "add w23, w23, w24",
         "add w23, w23, w26",
         "ror w21, w21, #2",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w23",
-        "mov v4.s[2], w22",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w23",
+        "mov v2.s[2], w22",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w20",
         "add sp, sp, #0x20 (32)"
       ]
@@ -1444,11 +1444,11 @@
         "add w23, w23, w24",
         "add w23, w23, w26",
         "ror w21, w21, #2",
-        "mov v4.16b, v16.16b",
-        "mov v4.s[3], w23",
-        "mov v4.s[2], w22",
-        "mov v4.s[1], w21",
-        "mov v16.16b, v4.16b",
+        "mov v2.16b, v16.16b",
+        "mov v2.s[3], w23",
+        "mov v2.s[2], w22",
+        "mov v2.s[1], w21",
+        "mov v16.16b, v2.16b",
         "mov v16.s[0], w20",
         "add sp, sp, #0x20 (32)"
       ]
@@ -1461,11 +1461,11 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1608]",
-        "ldr q4, [x0]",
-        "movi v5.2d, #0x0",
+        "ldr q2, [x0]",
+        "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
-        "tbl v16.16b, {v16.16b}, v4.16b"
+        "tbl v16.16b, {v16.16b}, v2.16b"
       ]
     },
     "aeskeygenassist xmm0, xmm1, 0xFF": {
@@ -1476,11 +1476,11 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1608]",
-        "ldr q4, [x0]",
-        "movi v5.2d, #0x0",
+        "ldr q2, [x0]",
+        "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
-        "tbl v16.16b, {v16.16b}, v4.16b",
+        "tbl v16.16b, {v16.16b}, v2.16b",
         "mov x0, #0xff00000000",
         "dup v1.2d, x0",
         "eor v16.16b, v16.16b, v1.16b"
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index b51d16c5c..7fcc6a556 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -3109,9 +3109,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
@@ -3160,9 +3160,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
@@ -3284,9 +3284,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index de1b913dd..62faf7608 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -133,9 +133,9 @@
         "0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "scvtf v4.4s, v4.4s",
-        "mov v16.d[0], v4.d[0]"
+        "ldr d2, [x4]",
+        "scvtf v2.4s, v2.4s",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtpi2ps xmm0, mm0": {
@@ -146,9 +146,9 @@
         "0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "scvtf v4.4s, v4.4s",
-        "mov v16.d[0], v4.d[0]"
+        "ldr d2, [x28, #752]",
+        "scvtf v2.4s, v2.4s",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "movntps [rax], xmm0": {
@@ -164,9 +164,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x4]",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "cvttps2pi mm0, xmm0": {
@@ -174,8 +174,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "fcvtzs v4.2s, v16.2s",
-        "str d4, [x28, #752]"
+        "fcvtzs v2.2s, v16.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "cvtps2pi mm0, [rax]": {
@@ -183,10 +183,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "frinti v4.2s, v4.2s",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x4]",
+        "frinti v2.2s, v2.2s",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "cvtps2pi mm0, xmm0": {
@@ -194,9 +194,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "frinti v4.2s, v16.2s",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "frinti v2.2s, v16.2s",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "ucomiss xmm0, xmm1": {
@@ -696,9 +696,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "cmp x22, #0x0 (0)",
         "csel w20, w20, w21, ne",
@@ -715,9 +715,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "cmp x22, #0x0 (0)",
         "csel w4, w20, w21, ne"
@@ -731,9 +731,9 @@
         "ldrb w20, [x28, #706]",
         "mov w21, #0x1",
         "eor w20, w20, #0x1",
-        "fmov s4, w20",
-        "cnt v4.16b, v4.16b",
-        "umov w20, v4.b[0]",
+        "fmov s2, w20",
+        "cnt v2.16b, v2.16b",
+        "umov w20, v2.b[0]",
         "and x20, x21, x20",
         "cmp x20, #0x0 (0)",
         "csel x4, x7, x4, ne"
@@ -749,9 +749,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "cmp x22, #0x0 (0)",
         "csel w20, w20, w21, eq",
@@ -768,9 +768,9 @@
         "ldrb w22, [x28, #706]",
         "mov w23, #0x1",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x22, x23, x22",
         "cmp x22, #0x0 (0)",
         "csel w4, w20, w21, eq"
@@ -784,9 +784,9 @@
         "ldrb w20, [x28, #706]",
         "mov w21, #0x1",
         "eor w20, w20, #0x1",
-        "fmov s4, w20",
-        "cnt v4.16b, v4.16b",
-        "umov w20, v4.b[0]",
+        "fmov s2, w20",
+        "cnt v2.16b, v2.16b",
+        "umov w20, v2.b[0]",
         "and x20, x21, x20",
         "cmp x20, #0x0 (0)",
         "csel x4, x7, x4, eq"
@@ -1009,12 +1009,12 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
-        "ushr v4.4s, v16.4s, #31",
+        "ushr v2.4s, v16.4s, #31",
         "ldr x0, [x28, #1600]",
-        "ldr q5, [x0]",
-        "ushl v4.4s, v4.4s, v5.4s",
-        "addv s4, v4.4s",
-        "mov w4, v4.s[0]"
+        "ldr q3, [x0]",
+        "ushl v2.4s, v2.4s, v3.4s",
+        "addv s2, v2.4s",
+        "mov w4, v2.s[0]"
       ]
     },
     "movmskps rax, xmm0": {
@@ -1022,12 +1022,12 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
-        "ushr v4.4s, v16.4s, #31",
+        "ushr v2.4s, v16.4s, #31",
         "ldr x0, [x28, #1600]",
-        "ldr q5, [x0]",
-        "ushl v4.4s, v4.4s, v5.4s",
-        "addv s4, v4.4s",
-        "mov w4, v4.s[0]"
+        "ldr q3, [x0]",
+        "ushl v2.4s, v2.4s, v3.4s",
+        "addv s2, v2.4s",
+        "mov w4, v2.s[0]"
       ]
     },
     "sqrtps xmm0, xmm1": {
@@ -1124,8 +1124,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x5a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "fcvtl v16.2d, v4.2s"
+        "ldr d2, [x4]",
+        "fcvtl v16.2d, v2.2s"
       ]
     },
     "cvtdq2ps xmm0, xmm1": {
@@ -1175,10 +1175,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x60",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip1 v4.8b, v4.8b, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip1 v2.8b, v2.8b, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "punpcklbw mm0, [rax]": {
@@ -1186,10 +1186,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x60",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip1 v4.8b, v4.8b, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip1 v2.8b, v2.8b, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "punpcklwd mm0, mm1": {
@@ -1197,10 +1197,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x61",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip1 v4.4h, v4.4h, v5.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip1 v2.4h, v2.4h, v3.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "punpcklwd mm0, [rax]": {
@@ -1208,10 +1208,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x61",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip1 v4.4h, v4.4h, v5.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip1 v2.4h, v2.4h, v3.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckldq mm0, mm1": {
@@ -1219,10 +1219,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x62",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip1 v4.2s, v4.2s, v5.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip1 v2.2s, v2.2s, v3.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckldq mm0, [rax]": {
@@ -1230,10 +1230,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x62",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip1 v4.2s, v4.2s, v5.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip1 v2.2s, v2.2s, v3.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "packsswb mm0, mm1": {
@@ -1241,11 +1241,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x63",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip1 v4.2d, v4.2d, v5.2d",
-        "sqxtn v4.8b, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip1 v2.2d, v2.2d, v3.2d",
+        "sqxtn v2.8b, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "packsswb mm0, [rax]": {
@@ -1253,11 +1253,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x63",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip1 v4.2d, v4.2d, v5.2d",
-        "sqxtn v4.8b, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip1 v2.2d, v2.2d, v3.2d",
+        "sqxtn v2.8b, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "packsswb mm0, mm0": {
@@ -1265,10 +1265,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x63",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "zip1 v4.2d, v4.2d, v4.2d",
-        "sqxtn v4.8b, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "zip1 v2.2d, v2.2d, v2.2d",
+        "sqxtn v2.8b, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpgtb mm0, mm1": {
@@ -1276,10 +1276,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x64",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmgt v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmgt v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpgtw mm0, mm1": {
@@ -1287,10 +1287,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x65",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmgt v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmgt v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpgtd mm0, mm1": {
@@ -1298,10 +1298,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x66",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmgt v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmgt v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhbw mm0, mm1": {
@@ -1309,10 +1309,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x68",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip2 v4.8b, v4.8b, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip2 v2.8b, v2.8b, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhbw mm0, [rax]": {
@@ -1320,10 +1320,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x68",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip2 v4.8b, v4.8b, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip2 v2.8b, v2.8b, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhwd mm0, mm1": {
@@ -1331,10 +1331,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x69",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip2 v4.4h, v4.4h, v5.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip2 v2.4h, v2.4h, v3.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhwd mm0, [rax]": {
@@ -1342,10 +1342,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x69",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip2 v4.4h, v4.4h, v5.4h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip2 v2.4h, v2.4h, v3.4h",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhdq mm0, mm1": {
@@ -1353,10 +1353,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip2 v4.2s, v4.2s, v5.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip2 v2.2s, v2.2s, v3.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "punpckhdq mm0, [rax]": {
@@ -1364,10 +1364,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x4]",
-        "zip2 v4.2s, v4.2s, v5.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x4]",
+        "zip2 v2.2s, v2.2s, v3.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "packssdw mm0, mm1": {
@@ -1375,11 +1375,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6b",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "zip1 v4.2d, v4.2d, v5.2d",
-        "sqxtn v4.4h, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "zip1 v2.2d, v2.2d, v3.2d",
+        "sqxtn v2.4h, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "movd mm0, eax": {
@@ -1387,8 +1387,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6e",
       "ExpectedArm64ASM": [
-        "fmov s4, w4",
-        "str d4, [x28, #752]"
+        "fmov s2, w4",
+        "str d2, [x28, #752]"
       ]
     },
     "movd mm0, [rax]": {
@@ -1396,8 +1396,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6e",
       "ExpectedArm64ASM": [
-        "ldr s4, [x4]",
-        "str d4, [x28, #752]"
+        "ldr s2, [x4]",
+        "str d2, [x28, #752]"
       ]
     },
     "movq mm0, mm0": {
@@ -1405,8 +1405,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0x6f",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x28, #752]"
       ]
     },
     "movq mm0, mm1": {
@@ -1414,8 +1414,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6f",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "str d2, [x28, #752]"
       ]
     },
     "movq mm0, [rax]": {
@@ -1423,8 +1423,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x6f",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x4]",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, mm1, 0": {
@@ -1432,9 +1432,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "dup v4.8h, v4.h[0]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "dup v2.8h, v2.h[0]",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, [rax], 0": {
@@ -1442,9 +1442,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "dup v4.8h, v4.h[0]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x4]",
+        "dup v2.8h, v2.h[0]",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, mm1, 1": {
@@ -1452,11 +1452,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
+        "ldr d2, [x28, #768]",
         "ldr x0, [x28, #1616]",
-        "ldr d5, [x0, #16]",
-        "tbl v4.8b, {v4.16b}, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d3, [x0, #16]",
+        "tbl v2.8b, {v2.16b}, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, [rax], 1": {
@@ -1464,11 +1464,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "ldr x0, [x28, #1616]",
-        "ldr d5, [x0, #16]",
-        "tbl v4.8b, {v4.16b}, v5.8b",
-        "str d4, [x28, #752]"
+        "ldr d3, [x0, #16]",
+        "tbl v2.8b, {v2.16b}, v3.8b",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, mm1, 0xff": {
@@ -1476,9 +1476,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "dup v4.8h, v4.h[3]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "dup v2.8h, v2.h[3]",
+        "str d2, [x28, #752]"
       ]
     },
     "pshufw mm0, [rax], 0xff": {
@@ -1486,9 +1486,9 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "dup v4.8h, v4.h[3]",
-        "str d4, [x28, #752]"
+        "ldr d2, [x4]",
+        "dup v2.8h, v2.h[3]",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpeqb mm0, mm1": {
@@ -1496,10 +1496,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x74",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmeq v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmeq v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpeqw mm0, mm1": {
@@ -1507,10 +1507,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x75",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmeq v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmeq v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pcmpeqd mm0, mm1": {
@@ -1518,10 +1518,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x76",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "cmeq v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "cmeq v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "emms": {
@@ -1538,8 +1538,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0x7e",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "mov w4, v4.s[0]"
+        "ldr d2, [x28, #752]",
+        "mov w4, v2.s[0]"
       ]
     },
     "movd [rax], mm0": {
@@ -1547,8 +1547,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x7e",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str s4, [x4]"
+        "ldr d2, [x28, #752]",
+        "str s2, [x4]"
       ]
     },
     "db 0x0f, 0x7f, 0xc1": {
@@ -1560,8 +1560,8 @@
         "0x0f 0x7f"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x28, #768]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x28, #768]"
       ]
     },
     "movq [rax], mm0": {
@@ -1569,8 +1569,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x7f",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x4]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x4]"
       ]
     },
     "seto al": {
@@ -1715,9 +1715,9 @@
         "mov w20, #0x1",
         "ldrb w21, [x28, #706]",
         "eor w21, w21, #0x1",
-        "fmov s4, w21",
-        "cnt v4.16b, v4.16b",
-        "umov w21, v4.b[0]",
+        "fmov s2, w21",
+        "cnt v2.16b, v2.16b",
+        "umov w21, v2.b[0]",
         "and x20, x20, x21",
         "cmp x20, #0x0 (0)",
         "cset x20, ne",
@@ -1732,9 +1732,9 @@
         "mov w20, #0x1",
         "ldrb w21, [x28, #706]",
         "eor w21, w21, #0x1",
-        "fmov s4, w21",
-        "cnt v4.16b, v4.16b",
-        "umov w21, v4.b[0]",
+        "fmov s2, w21",
+        "cnt v2.16b, v2.16b",
+        "umov w21, v2.b[0]",
         "and x20, x20, x21",
         "cmp x20, #0x0 (0)",
         "cset x20, eq",
@@ -3411,8 +3411,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xc2",
       "ExpectedArm64ASM": [
-        "fcmgt v4.4s, v17.4s, v16.4s",
-        "mvn v16.16b, v4.16b"
+        "fcmgt v2.4s, v17.4s, v16.4s",
+        "mvn v16.16b, v2.16b"
       ]
     },
     "cmpps xmm0, xmm1, 6": {
@@ -3420,8 +3420,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xc2",
       "ExpectedArm64ASM": [
-        "fcmge v4.4s, v17.4s, v16.4s",
-        "mvn v16.16b, v4.16b"
+        "fcmge v2.4s, v17.4s, v16.4s",
+        "mvn v16.16b, v2.16b"
       ]
     },
     "cmpps xmm0, xmm1, 7": {
@@ -3457,9 +3457,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[0], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[0], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, eax, 1": {
@@ -3468,9 +3468,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[1], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[1], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, eax, 2": {
@@ -3479,9 +3479,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[2], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[2], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, eax, 3": {
@@ -3490,9 +3490,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[3], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[3], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, eax, 4": {
@@ -3501,9 +3501,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[0], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[0], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, [rax], 0": {
@@ -3512,9 +3512,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[0], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[0], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, [rax], 1": {
@@ -3523,9 +3523,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[1], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[1], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, [rax], 2": {
@@ -3534,9 +3534,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[2], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[2], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, [rax], 3": {
@@ -3545,9 +3545,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[3], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[3], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pinsrw mm0, [rax], 4": {
@@ -3556,9 +3556,9 @@
       "Comment": "0x0f 0xc4",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "ldr d4, [x28, #752]",
-        "mov v4.h[0], w20",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "mov v2.h[0], w20",
+        "str d2, [x28, #752]"
       ]
     },
     "pextrw eax, mm0, 0": {
@@ -3566,8 +3566,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "umov w20, v4.h[0]",
+        "ldr d2, [x28, #752]",
+        "umov w20, v2.h[0]",
         "uxth x4, w20"
       ]
     },
@@ -3576,8 +3576,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "umov w20, v4.h[1]",
+        "ldr d2, [x28, #752]",
+        "umov w20, v2.h[1]",
         "uxth x4, w20"
       ]
     },
@@ -3586,8 +3586,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "umov w20, v4.h[2]",
+        "ldr d2, [x28, #752]",
+        "umov w20, v2.h[2]",
         "uxth x4, w20"
       ]
     },
@@ -3596,8 +3596,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "umov w20, v4.h[3]",
+        "ldr d2, [x28, #752]",
+        "umov w20, v2.h[3]",
         "uxth x4, w20"
       ]
     },
@@ -3606,8 +3606,8 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "umov w20, v4.h[0]",
+        "ldr d2, [x28, #752]",
+        "umov w20, v2.h[0]",
         "uxth x4, w20"
       ]
     },
@@ -3618,10 +3618,10 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v16.s[0]",
-        "mov v4.s[2], v17.s[0]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v16.s[0]",
+        "mov v2.s[2], v17.s[0]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[0]",
         "mov v16.16b, v0.16b"
       ]
@@ -3631,14 +3631,14 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v16.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v16.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -3649,10 +3649,10 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v16.s[0]",
-        "mov v4.s[2], v17.s[0]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v16.s[0]",
+        "mov v2.s[2], v17.s[0]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[0]",
         "mov v16.16b, v0.16b"
       ]
@@ -3662,14 +3662,14 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[1]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v16.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v16.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -3680,10 +3680,10 @@
       "ExpectedArm64ASM": [
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v16.s[3]",
-        "mov v4.s[2], v17.s[3]",
-        "mov v0.16b, v4.16b",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v16.s[3]",
+        "mov v2.s[2], v17.s[3]",
+        "mov v0.16b, v2.16b",
         "mov v0.s[3], v17.s[3]",
         "mov v16.16b, v0.16b"
       ]
@@ -3693,14 +3693,14 @@
       "Optimal": "No",
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "mov v0.16b, v16.16b",
         "mov v0.s[0], v16.s[3]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v16.s[3]",
-        "mov v5.s[2], v4.s[3]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v16.s[3]",
+        "mov v3.s[2], v2.s[3]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
         "mov v16.16b, v0.16b"
       ]
     },
@@ -3726,14 +3726,14 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.8h, v0.h[0]",
         "neg v0.8h, v0.8h",
-        "ushl v4.8h, v5.8h, v0.8h",
-        "str d4, [x28, #752]"
+        "ushl v2.8h, v3.8h, v0.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "psrld mm0, mm1": {
@@ -3741,14 +3741,14 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.4s, v0.s[0]",
         "neg v0.4s, v0.4s",
-        "ushl v4.4s, v5.4s, v0.4s",
-        "str d4, [x28, #752]"
+        "ushl v2.4s, v3.4s, v0.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlq mm0, mm1": {
@@ -3756,14 +3756,14 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.2d, v0.d[0]",
         "neg v0.2d, v0.2d",
-        "ushl v4.2d, v5.2d, v0.2d",
-        "str d4, [x28, #752]"
+        "ushl v2.2d, v3.2d, v0.2d",
+        "str d2, [x28, #752]"
       ]
     },
     "paddq mm0, mm1": {
@@ -3771,10 +3771,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd4",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "add v4.2d, v5.2d, v4.2d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "add v2.2d, v3.2d, v2.2d",
+        "str d2, [x28, #752]"
       ]
     },
     "pmullw mm0, mm1": {
@@ -3782,10 +3782,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mul v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mul v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pmovmskb eax, mm0": {
@@ -3793,18 +3793,18 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
+        "ldr d2, [x28, #752]",
         "mov x20, #0x201",
         "movk x20, #0x804, lsl #16",
         "movk x20, #0x2010, lsl #32",
         "movk x20, #0x8040, lsl #48",
-        "dup v5.2d, x20",
-        "cmlt v4.16b, v4.16b, #0",
-        "and v4.16b, v4.16b, v5.16b",
-        "addp v4.16b, v4.16b, v4.16b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "umov w4, v4.h[0]"
+        "dup v3.2d, x20",
+        "cmlt v2.16b, v2.16b, #0",
+        "and v2.16b, v2.16b, v3.16b",
+        "addp v2.16b, v2.16b, v2.16b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "umov w4, v2.h[0]"
       ]
     },
     "psubusb mm0, mm1": {
@@ -3812,10 +3812,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd8",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqsub v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqsub v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psubusw mm0, mm1": {
@@ -3823,10 +3823,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xd9",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqsub v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqsub v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pminub mm0, mm1": {
@@ -3834,10 +3834,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xda",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "umin v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "umin v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pand mm0, mm1": {
@@ -3845,10 +3845,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xdb",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "and v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "and v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "paddusb mm0, mm1": {
@@ -3856,10 +3856,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xdc",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqadd v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqadd v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "paddusw mm0, mm1": {
@@ -3867,10 +3867,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xdd",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqadd v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqadd v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pmaxub mm0, mm1": {
@@ -3878,10 +3878,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xde",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "umax v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "umax v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pandn mm0, mm1": {
@@ -3889,10 +3889,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xdf",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "bic v4.16b, v4.16b, v5.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "bic v2.16b, v2.16b, v3.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "pavgb mm0, mm1": {
@@ -3900,10 +3900,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe0",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "urhadd v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "urhadd v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psraw mm0, mm1": {
@@ -3911,14 +3911,14 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.8h, v0.h[0]",
         "neg v0.8h, v0.8h",
-        "sshl v4.8h, v5.8h, v0.8h",
-        "str d4, [x28, #752]"
+        "sshl v2.8h, v3.8h, v0.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "psrad mm0, mm1": {
@@ -3926,14 +3926,14 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.4s, v0.s[0]",
         "neg v0.4s, v0.4s",
-        "sshl v4.4s, v5.4s, v0.4s",
-        "str d4, [x28, #752]"
+        "sshl v2.4s, v3.4s, v0.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "pavgw mm0, mm1": {
@@ -3941,10 +3941,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "urhadd v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "urhadd v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pmulhuw mm0, mm1": {
@@ -3952,11 +3952,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe4",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "umull v4.4s, v4.4h, v5.4h",
-        "shrn v4.4h, v4.4s, #16",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "umull v2.4s, v2.4h, v3.4h",
+        "shrn v2.4h, v2.4s, #16",
+        "str d2, [x28, #752]"
       ]
     },
     "pmulhw mm0, mm1": {
@@ -3964,11 +3964,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "smull v4.4s, v4.4h, v5.4h",
-        "shrn v4.4h, v4.4s, #16",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "smull v2.4s, v2.4h, v3.4h",
+        "shrn v2.4h, v2.4s, #16",
+        "str d2, [x28, #752]"
       ]
     },
     "movntq [rax], mm0": {
@@ -3976,8 +3976,8 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe7",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "str d4, [x4]"
+        "ldr d2, [x28, #752]",
+        "str d2, [x4]"
       ]
     },
     "psubsb mm0, mm1": {
@@ -3985,10 +3985,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe8",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqsub v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqsub v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psubsw mm0, mm1": {
@@ -3996,10 +3996,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xe9",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqsub v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqsub v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pminsw mm0, mm1": {
@@ -4007,10 +4007,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xea",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "smin v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "smin v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "por mm0, mm1": {
@@ -4018,10 +4018,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xeb",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "orr v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "orr v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "paddsb mm0, mm1": {
@@ -4029,10 +4029,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xec",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqadd v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqadd v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "paddsw mm0, mm1": {
@@ -4040,10 +4040,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xed",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sqadd v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sqadd v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pmaxsw mm0, mm1": {
@@ -4051,10 +4051,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xee",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "smax v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "smax v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pxor mm0, mm1": {
@@ -4062,10 +4062,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xef",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "eor v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "eor v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psllw mm0, mm1": {
@@ -4073,13 +4073,13 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.8h, v0.h[0]",
-        "ushl v4.8h, v5.8h, v0.8h",
-        "str d4, [x28, #752]"
+        "ushl v2.8h, v3.8h, v0.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "pslld mm0, mm1": {
@@ -4087,13 +4087,13 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.4s, v0.s[0]",
-        "ushl v4.4s, v5.4s, v0.4s",
-        "str d4, [x28, #752]"
+        "ushl v2.4s, v3.4s, v0.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "psllq mm0, mm1": {
@@ -4101,13 +4101,13 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "uqshl d0, d4, #57",
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "uqshl d0, d2, #57",
         "ushr d0, d0, #57",
         "dup v0.2d, v0.d[0]",
-        "ushl v4.2d, v5.2d, v0.2d",
-        "str d4, [x28, #752]"
+        "ushl v2.2d, v3.2d, v0.2d",
+        "str d2, [x28, #752]"
       ]
     },
     "pmuludq mm0, mm1": {
@@ -4115,10 +4115,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf4",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "umull v4.2d, v4.2s, v5.2s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "umull v2.2d, v2.2s, v3.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "pmaddwd mm0, mm1": {
@@ -4126,11 +4126,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf5",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "smull v4.4s, v4.4h, v5.4h",
-        "addp v4.4s, v4.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "smull v2.4s, v2.4h, v3.4h",
+        "addp v2.4s, v2.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "psadbw mm0, mm1": {
@@ -4138,11 +4138,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ldr d5, [x28, #768]",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addv h4, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ldr d3, [x28, #768]",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addv h2, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "maskmovq mm0, mm1": {
@@ -4150,12 +4150,12 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf7",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "cmlt v4.16b, v4.16b, #0",
-        "ldr d5, [x28, #752]",
-        "ldr d6, [x11]",
-        "bsl v4.8b, v5.8b, v6.8b",
-        "str d4, [x11]"
+        "ldr d2, [x28, #768]",
+        "cmlt v2.16b, v2.16b, #0",
+        "ldr d3, [x28, #752]",
+        "ldr d4, [x11]",
+        "bsl v2.8b, v3.8b, v4.8b",
+        "str d2, [x11]"
       ]
     },
     "psubb mm0, mm1": {
@@ -4163,10 +4163,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf8",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sub v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sub v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "psubw mm0, mm1": {
@@ -4174,10 +4174,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xf9",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sub v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sub v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "psubd mm0, mm1": {
@@ -4185,10 +4185,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xfa",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sub v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sub v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     },
     "psubq mm0, mm1": {
@@ -4196,10 +4196,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xfb",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "sub v4.2d, v5.2d, v4.2d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "sub v2.2d, v3.2d, v2.2d",
+        "str d2, [x28, #752]"
       ]
     },
     "paddb mm0, mm1": {
@@ -4207,10 +4207,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xfc",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "add v4.16b, v5.16b, v4.16b",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "add v2.16b, v3.16b, v2.16b",
+        "str d2, [x28, #752]"
       ]
     },
     "paddw mm0, mm1": {
@@ -4218,10 +4218,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xfd",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "add v4.8h, v5.8h, v4.8h",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "add v2.8h, v3.8h, v2.8h",
+        "str d2, [x28, #752]"
       ]
     },
     "paddd mm0, mm1": {
@@ -4229,10 +4229,10 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0xfe",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "add v4.4s, v5.4s, v4.4s",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "add v2.4s, v3.4s, v2.4s",
+        "str d2, [x28, #752]"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json
index c8e9a086a..4c13b5dc3 100644
--- a/unittests/InstructionCountCI/SecondaryGroup.json
+++ b/unittests/InstructionCountCI/SecondaryGroup.json
@@ -85,13 +85,15 @@
       ]
     },
     "bts ax, 0": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 8,
       "Optimal": "No",
       "Comment": "GROUP8 0x0F 0xBA /5",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "orr x21, x20, #0x1",
-        "bfxil x4, x21, #0, #16",
+        "mov x0, x20",
+        "bfxil x0, x21, #0, #16",
+        "mov x4, x0",
         "ubfx x20, x20, #0, #1",
         "lsl x20, x20, #29",
         "str w20, [x28, #728]"
@@ -161,13 +163,15 @@
       ]
     },
     "btr ax, 0": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 8,
       "Optimal": "No",
       "Comment": "GROUP8 0x0F 0xBA /6",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "and x21, x20, #0xfffffffffffffffe",
-        "bfxil x4, x21, #0, #16",
+        "mov x0, x20",
+        "bfxil x0, x21, #0, #16",
+        "mov x4, x0",
         "ubfx x20, x20, #0, #1",
         "lsl x20, x20, #29",
         "str w20, [x28, #728]"
@@ -237,13 +241,15 @@
       ]
     },
     "btc ax, 0": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 8,
       "Optimal": "No",
       "Comment": "GROUP8 0x0F 0xBA /7",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "eor x21, x20, #0x1",
-        "bfxil x4, x21, #0, #16",
+        "mov x0, x20",
+        "bfxil x0, x21, #0, #16",
+        "mov x4, x0",
         "ubfx x20, x20, #0, #1",
         "lsl x20, x20, #29",
         "str w20, [x28, #728]"
@@ -491,9 +497,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP12 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ushr v4.8h, v4.8h, #15",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ushr v2.8h, v2.8h, #15",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlw mm0, 16": {
@@ -502,9 +508,9 @@
       "Optimal": "No",
       "Comment": "GROUP12 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlw xmm0, 0": {
@@ -545,9 +551,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP12 0x0F 0xC7 /3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "sshr v4.8h, v4.8h, #15",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "sshr v2.8h, v2.8h, #15",
+        "str d2, [x28, #752]"
       ]
     },
     "psraw mm0, 16": {
@@ -556,9 +562,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP12 0x0F 0xC7 /3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "sshr v4.8h, v4.8h, #15",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "sshr v2.8h, v2.8h, #15",
+        "str d2, [x28, #752]"
       ]
     },
     "psraw xmm0, 0": {
@@ -599,9 +605,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP12 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "shl v4.8h, v4.8h, #15",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "shl v2.8h, v2.8h, #15",
+        "str d2, [x28, #752]"
       ]
     },
     "psllw mm0, 16": {
@@ -610,9 +616,9 @@
       "Optimal": "No",
       "Comment": "GROUP12 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "psllw xmm0, 0": {
@@ -653,9 +659,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP13 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ushr v4.4s, v4.4s, #31",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ushr v2.4s, v2.4s, #31",
+        "str d2, [x28, #752]"
       ]
     },
     "psrld mm0, 32": {
@@ -664,9 +670,9 @@
       "Optimal": "No",
       "Comment": "GROUP13 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "psrld xmm0, 0": {
@@ -707,9 +713,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP13 0x0F 0xC7 /3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "sshr v4.4s, v4.4s, #31",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "sshr v2.4s, v2.4s, #31",
+        "str d2, [x28, #752]"
       ]
     },
     "psrad mm0, 32": {
@@ -718,9 +724,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP13 0x0F 0xC7 /3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "sshr v4.4s, v4.4s, #31",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "sshr v2.4s, v2.4s, #31",
+        "str d2, [x28, #752]"
       ]
     },
     "psrad xmm0, 0": {
@@ -761,9 +767,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP13 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "shl v4.4s, v4.4s, #31",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "shl v2.4s, v2.4s, #31",
+        "str d2, [x28, #752]"
       ]
     },
     "pslld mm0, 32": {
@@ -772,9 +778,9 @@
       "Optimal": "No",
       "Comment": "GROUP13 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "pslld xmm0, 0": {
@@ -815,9 +821,9 @@
       "Optimal": "No",
       "Comment": "GROUP14 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "ushr v4.2d, v4.2d, #63",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "ushr v2.2d, v2.2d, #63",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlq mm0, 64": {
@@ -826,9 +832,9 @@
       "Optimal": "No",
       "Comment": "GROUP14 0x0F 0xC7 /2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlq xmm0, 0": {
@@ -869,8 +875,8 @@
       "Optimal": "No",
       "Comment": "GROUP14 0x0F 0xC7 /3",
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "ext v16.16b, v16.16b, v4.16b, #15"
+        "movi v2.2d, #0x0",
+        "ext v16.16b, v16.16b, v2.16b, #15"
       ]
     },
     "psrldq xmm0, 16": {
@@ -895,9 +901,9 @@
       "Optimal": "Yes",
       "Comment": "GROUP14 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "shl v4.2d, v4.2d, #63",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "shl v2.2d, v2.2d, #63",
+        "str d2, [x28, #752]"
       ]
     },
     "psllq mm0, 64": {
@@ -906,9 +912,9 @@
       "Optimal": "No",
       "Comment": "GROUP14 0x0F 0xC7 /6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "movi v4.2d, #0x0",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #752]",
+        "movi v2.2d, #0x0",
+        "str d2, [x28, #752]"
       ]
     },
     "psllq xmm0, 0": {
@@ -962,22 +968,22 @@
         "strh w20, [x4, #2]",
         "ldrb w20, [x28, #1010]",
         "strb w20, [x4, #4]",
-        "ldr q4, [x28, #752]",
-        "str q4, [x4, #32]",
-        "ldr q4, [x28, #768]",
-        "str q4, [x4, #48]",
-        "ldr q4, [x28, #784]",
-        "str q4, [x4, #64]",
-        "ldr q4, [x28, #800]",
-        "str q4, [x4, #80]",
-        "ldr q4, [x28, #816]",
-        "str q4, [x4, #96]",
-        "ldr q4, [x28, #832]",
-        "str q4, [x4, #112]",
-        "ldr q4, [x28, #848]",
-        "str q4, [x4, #128]",
-        "ldr q4, [x28, #864]",
-        "str q4, [x4, #144]",
+        "ldr q2, [x28, #752]",
+        "str q2, [x4, #32]",
+        "ldr q2, [x28, #768]",
+        "str q2, [x4, #48]",
+        "ldr q2, [x28, #784]",
+        "str q2, [x4, #64]",
+        "ldr q2, [x28, #800]",
+        "str q2, [x4, #80]",
+        "ldr q2, [x28, #816]",
+        "str q2, [x4, #96]",
+        "ldr q2, [x28, #832]",
+        "str q2, [x4, #112]",
+        "ldr q2, [x28, #848]",
+        "str q2, [x4, #128]",
+        "ldr q2, [x28, #864]",
+        "str q2, [x4, #144]",
         "str q16, [x4, #160]",
         "str q17, [x4, #176]",
         "str q18, [x4, #192]",
@@ -1033,7 +1039,7 @@
       ]
     },
     "fxrstor [rax]": {
-      "ExpectedInstructionCount": 103,
+      "ExpectedInstructionCount": 105,
       "Optimal": "No",
       "Comment": "GROUP15 0x0F 0xAE /1",
       "ExpectedArm64ASM": [
@@ -1051,8 +1057,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1060,6 +1067,7 @@
         "uxth w0, w20",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1091,22 +1099,22 @@
         "strb w20, [x28, #750]",
         "ldrb w20, [x4, #4]",
         "strb w20, [x28, #1010]",
-        "ldr q4, [x4, #32]",
-        "str q4, [x28, #752]",
-        "ldr q4, [x4, #48]",
-        "str q4, [x28, #768]",
-        "ldr q4, [x4, #64]",
-        "str q4, [x28, #784]",
-        "ldr q4, [x4, #80]",
-        "str q4, [x28, #800]",
-        "ldr q4, [x4, #96]",
-        "str q4, [x28, #816]",
-        "ldr q4, [x4, #112]",
-        "str q4, [x28, #832]",
-        "ldr q4, [x4, #128]",
-        "str q4, [x28, #848]",
-        "ldr q4, [x4, #144]",
-        "str q4, [x28, #864]",
+        "ldr q2, [x4, #32]",
+        "str q2, [x28, #752]",
+        "ldr q2, [x4, #48]",
+        "str q2, [x28, #768]",
+        "ldr q2, [x4, #64]",
+        "str q2, [x28, #784]",
+        "ldr q2, [x4, #80]",
+        "str q2, [x28, #800]",
+        "ldr q2, [x4, #96]",
+        "str q2, [x28, #816]",
+        "ldr q2, [x4, #112]",
+        "str q2, [x28, #832]",
+        "ldr q2, [x4, #128]",
+        "str q2, [x28, #848]",
+        "ldr q2, [x4, #144]",
+        "str q2, [x28, #864]",
         "ldr q16, [x4, #160]",
         "ldr q17, [x4, #176]",
         "ldr q18, [x4, #192]",
@@ -1271,22 +1279,22 @@
         "strh w22, [x21, #2]",
         "ldrb w22, [x28, #1010]",
         "strb w22, [x21, #4]",
-        "ldr q4, [x28, #752]",
-        "str q4, [x21, #32]",
-        "ldr q4, [x28, #768]",
-        "str q4, [x21, #48]",
-        "ldr q4, [x28, #784]",
-        "str q4, [x21, #64]",
-        "ldr q4, [x28, #800]",
-        "str q4, [x21, #80]",
-        "ldr q4, [x28, #816]",
-        "str q4, [x21, #96]",
-        "ldr q4, [x28, #832]",
-        "str q4, [x21, #112]",
-        "ldr q4, [x28, #848]",
-        "str q4, [x21, #128]",
-        "ldr q4, [x28, #864]",
-        "str q4, [x21, #144]",
+        "ldr q2, [x28, #752]",
+        "str q2, [x21, #32]",
+        "ldr q2, [x28, #768]",
+        "str q2, [x21, #48]",
+        "ldr q2, [x28, #784]",
+        "str q2, [x21, #64]",
+        "ldr q2, [x28, #800]",
+        "str q2, [x21, #80]",
+        "ldr q2, [x28, #816]",
+        "str q2, [x21, #96]",
+        "ldr q2, [x28, #832]",
+        "str q2, [x21, #112]",
+        "ldr q2, [x28, #848]",
+        "str q2, [x21, #128]",
+        "ldr q2, [x28, #864]",
+        "str q2, [x21, #144]",
         "ubfx x22, x20, #1, #1",
         "cbnz x22, #+0x8",
         "b #+0x44",
@@ -1342,7 +1350,7 @@
       ]
     },
     "xrstor [rax]": {
-      "ExpectedInstructionCount": 190,
+      "ExpectedInstructionCount": 194,
       "Optimal": "No",
       "Comment": "GROUP15 0x0F 0xAE /5",
       "ExpectedArm64ASM": [
@@ -1350,7 +1358,7 @@
         "ldr x21, [x20, #512]",
         "ubfx x22, x21, #0, #1",
         "cbnz x22, #+0x8",
-        "b #+0x120",
+        "b #+0x128",
         "ldrh w22, [x20]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
@@ -1365,8 +1373,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1374,6 +1383,7 @@
         "uxth w0, w22",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1405,23 +1415,23 @@
         "strb w22, [x28, #750]",
         "ldrb w22, [x20, #4]",
         "strb w22, [x28, #1010]",
-        "ldr q4, [x20, #32]",
-        "str q4, [x28, #752]",
-        "ldr q4, [x20, #48]",
-        "str q4, [x28, #768]",
-        "ldr q4, [x20, #64]",
-        "str q4, [x28, #784]",
-        "ldr q4, [x20, #80]",
-        "str q4, [x28, #800]",
-        "ldr q4, [x20, #96]",
-        "str q4, [x28, #816]",
-        "ldr q4, [x20, #112]",
-        "str q4, [x28, #832]",
-        "ldr q4, [x20, #128]",
-        "str q4, [x28, #848]",
-        "ldr q4, [x20, #144]",
-        "str q4, [x28, #864]",
-        "b #+0xe8",
+        "ldr q2, [x20, #32]",
+        "str q2, [x28, #752]",
+        "ldr q2, [x20, #48]",
+        "str q2, [x28, #768]",
+        "ldr q2, [x20, #64]",
+        "str q2, [x28, #784]",
+        "ldr q2, [x20, #80]",
+        "str q2, [x28, #800]",
+        "ldr q2, [x20, #96]",
+        "str q2, [x28, #816]",
+        "ldr q2, [x20, #112]",
+        "str q2, [x28, #832]",
+        "ldr q2, [x20, #128]",
+        "str q2, [x28, #848]",
+        "ldr q2, [x20, #144]",
+        "str q2, [x28, #864]",
+        "b #+0xf0",
         "mov w22, #0x0",
         "mov w23, #0x37f",
         "stp x4, x5, [x28, #8]",
@@ -1437,8 +1447,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -1446,6 +1457,7 @@
         "uxth w0, w23",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1470,15 +1482,15 @@
         "strb w22, [x28, #746]",
         "strb w22, [x28, #750]",
         "strb w22, [x28, #1010]",
-        "movi v4.2d, #0x0",
-        "str q4, [x28, #752]",
-        "str q4, [x28, #768]",
-        "str q4, [x28, #784]",
-        "str q4, [x28, #800]",
-        "str q4, [x28, #816]",
-        "str q4, [x28, #832]",
-        "str q4, [x28, #848]",
-        "str q4, [x28, #864]",
+        "movi v2.2d, #0x0",
+        "str q2, [x28, #752]",
+        "str q2, [x28, #768]",
+        "str q2, [x28, #784]",
+        "str q2, [x28, #800]",
+        "str q2, [x28, #816]",
+        "str q2, [x28, #832]",
+        "str q2, [x28, #848]",
+        "str q2, [x28, #864]",
         "ubfx x22, x21, #1, #1",
         "cbnz x22, #+0x8",
         "b #+0x48",
diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json
index 2b5319997..51835e29a 100644
--- a/unittests/InstructionCountCI/SecondaryModRM.json
+++ b/unittests/InstructionCountCI/SecondaryModRM.json
@@ -11,12 +11,13 @@
   },
   "Instructions": {
     "xgetbv": {
-      "ExpectedInstructionCount": 44,
+      "ExpectedInstructionCount": 46,
       "Optimal": "No",
       "Comment": "0xF 0x01 /2 RM-0",
       "ExpectedArm64ASM": [
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -51,6 +52,7 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index 4f0c2eb27..2cb6cbc65 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -110,9 +110,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x2a",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #752]",
-        "sxtl v4.2d, v4.2s",
-        "scvtf v16.2d, v4.2d"
+        "ldr d2, [x28, #752]",
+        "sxtl v2.2d, v2.2s",
+        "scvtf v16.2d, v2.2d"
       ]
     },
     "movntpd [rax], xmm0": {
@@ -128,9 +128,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "fcvtn v4.2s, v16.2d",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "fcvtn v2.2s, v16.2d",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "cvtpd2pi mm0, xmm0": {
@@ -138,10 +138,10 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "fcvtn v4.2s, v16.2d",
-        "frinti v4.2s, v4.2s",
-        "fcvtzs v4.2s, v4.2s",
-        "str d4, [x28, #752]"
+        "fcvtn v2.2s, v16.2d",
+        "frinti v2.2s, v2.2s",
+        "fcvtzs v2.2s, v2.2s",
+        "str d2, [x28, #752]"
       ]
     },
     "ucomisd xmm0, xmm1": {
@@ -204,8 +204,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x50",
       "ExpectedArm64ASM": [
-        "uzp2 v4.4s, v16.4s, v16.4s",
-        "mov x20, v4.d[0]",
+        "uzp2 v2.4s, v16.4s, v16.4s",
+        "mov x20, v2.d[0]",
         "bfi x20, x20, #31, #32",
         "lsr x4, x20, #62"
       ]
@@ -247,8 +247,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x5a",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "fcvtn v16.2s, v4.2d"
+        "ldr q2, [x4]",
+        "fcvtn v16.2s, v2.2d"
       ]
     },
     "cvtps2dq xmm0, xmm1": {
@@ -265,8 +265,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x5b",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "frinti v16.4s, v4.4s",
+        "ldr q2, [x4]",
+        "frinti v16.4s, v2.4s",
         "fcvtzs v16.4s, v16.4s"
       ]
     },
@@ -317,8 +317,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x60",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip1 v16.16b, v16.16b, v4.16b"
+        "ldr q2, [x4]",
+        "zip1 v16.16b, v16.16b, v2.16b"
       ]
     },
     "punpcklwd xmm0, xmm1": {
@@ -334,8 +334,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x61",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip1 v16.8h, v16.8h, v4.8h"
+        "ldr q2, [x4]",
+        "zip1 v16.8h, v16.8h, v2.8h"
       ]
     },
     "punpckldq xmm0, xmm1": {
@@ -351,8 +351,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x62",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip1 v16.4s, v16.4s, v4.4s"
+        "ldr q2, [x4]",
+        "zip1 v16.4s, v16.4s, v2.4s"
       ]
     },
     "packsswb xmm0, xmm1": {
@@ -369,9 +369,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x63",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "sqxtn v16.8b, v16.8h",
-        "sqxtn2 v16.16b, v4.8h"
+        "sqxtn2 v16.16b, v2.8h"
       ]
     },
     "packsswb xmm0, xmm0": {
@@ -421,8 +421,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x68",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip2 v16.16b, v16.16b, v4.16b"
+        "ldr q2, [x4]",
+        "zip2 v16.16b, v16.16b, v2.16b"
       ]
     },
     "punpckhwd xmm0, xmm1": {
@@ -438,8 +438,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x69",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip2 v16.8h, v16.8h, v4.8h"
+        "ldr q2, [x4]",
+        "zip2 v16.8h, v16.8h, v2.8h"
       ]
     },
     "punpckhdq xmm0, xmm1": {
@@ -455,8 +455,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x6a",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "zip2 v16.4s, v16.4s, v4.4s"
+        "ldr q2, [x4]",
+        "zip2 v16.4s, v16.4s, v2.4s"
       ]
     },
     "packssdw xmm0, xmm1": {
@@ -573,8 +573,8 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "dup v16.4s, v4.s[0]"
+        "ldr q2, [x4]",
+        "dup v16.4s, v2.s[0]"
       ]
     },
     "pshufd xmm0, xmm1, 1": {
@@ -587,8 +587,8 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1632]",
-        "ldr q4, [x0, #16]",
-        "tbl v16.16b, {v17.16b}, v4.16b"
+        "ldr q2, [x0, #16]",
+        "tbl v16.16b, {v17.16b}, v2.16b"
       ]
     },
     "pshufd xmm0, [rax], 1": {
@@ -600,10 +600,10 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "ldr x0, [x28, #1632]",
-        "ldr q5, [x0, #16]",
-        "tbl v16.16b, {v4.16b}, v5.16b"
+        "ldr q3, [x0, #16]",
+        "tbl v16.16b, {v2.16b}, v3.16b"
       ]
     },
     "pshufd xmm0, xmm1, 0xff": {
@@ -625,8 +625,8 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "dup v16.4s, v4.s[3]"
+        "ldr q2, [x4]",
+        "dup v16.4s, v2.s[3]"
       ]
     },
     "pcmpeqb xmm0, xmm1": {
@@ -702,9 +702,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0x7c",
       "ExpectedArm64ASM": [
-        "uzp1 v4.2d, v16.2d, v17.2d",
-        "uzp2 v5.2d, v16.2d, v17.2d",
-        "fsub v16.2d, v4.2d, v5.2d"
+        "uzp1 v2.2d, v16.2d, v17.2d",
+        "uzp2 v3.2d, v16.2d, v17.2d",
+        "fsub v16.2d, v2.2d, v3.2d"
       ]
     },
     "movd dword [rax], xmm0": {
@@ -737,9 +737,9 @@
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1584]",
-        "ldr q4, [x0]",
-        "eor v4.16b, v17.16b, v4.16b",
-        "fadd v16.2d, v16.2d, v4.2d"
+        "ldr q2, [x0]",
+        "eor v2.16b, v17.16b, v2.16b",
+        "fadd v16.2d, v16.2d, v2.2d"
       ]
     },
     "psrlw xmm0, xmm1": {
@@ -803,13 +803,13 @@
         "movk x20, #0x804, lsl #16",
         "movk x20, #0x2010, lsl #32",
         "movk x20, #0x8040, lsl #48",
-        "dup v4.2d, x20",
-        "cmlt v5.16b, v16.16b, #0",
-        "and v4.16b, v5.16b, v4.16b",
-        "addp v4.16b, v4.16b, v4.16b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "umov w4, v4.h[0]"
+        "dup v2.2d, x20",
+        "cmlt v3.16b, v16.16b, #0",
+        "and v2.16b, v3.16b, v2.16b",
+        "addp v2.16b, v2.16b, v2.16b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "umov w4, v2.h[0]"
       ]
     },
     "psubusb xmm0, xmm1": {
@@ -941,8 +941,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xe6",
       "ExpectedArm64ASM": [
-        "fcvtn v4.2s, v17.2d",
-        "fcvtzs v16.4s, v4.4s"
+        "fcvtn v2.2s, v17.2d",
+        "fcvtzs v16.4s, v2.4s"
       ]
     },
     "movntdq [rax], xmm0": {
@@ -1055,9 +1055,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xf4",
       "ExpectedArm64ASM": [
-        "uzp1 v4.4s, v16.4s, v16.4s",
-        "uzp1 v5.4s, v17.4s, v17.4s",
-        "umull v16.2d, v4.2s, v5.2s"
+        "uzp1 v2.4s, v16.4s, v16.4s",
+        "uzp1 v3.4s, v17.4s, v17.4s",
+        "umull v16.2d, v2.2s, v3.2s"
       ]
     },
     "pmaddwd xmm0, xmm1": {
@@ -1065,9 +1065,9 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xf5",
       "ExpectedArm64ASM": [
-        "smull v4.4s, v16.4h, v17.4h",
-        "smull2 v5.4s, v16.8h, v17.8h",
-        "addp v16.4s, v4.4s, v5.4s"
+        "smull v2.4s, v16.4h, v17.4h",
+        "smull2 v3.4s, v16.8h, v17.8h",
+        "addp v16.4s, v2.4s, v3.4s"
       ]
     },
     "psadbw xmm0, xmm1": {
@@ -1075,11 +1075,11 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xf6",
       "ExpectedArm64ASM": [
-        "uabdl v4.8h, v16.8b, v17.8b",
-        "uabdl2 v5.8h, v16.16b, v17.16b",
-        "addv h4, v4.8h",
-        "addv h5, v5.8h",
-        "zip1 v16.2d, v4.2d, v5.2d"
+        "uabdl v2.8h, v16.8b, v17.8b",
+        "uabdl2 v3.8h, v16.16b, v17.16b",
+        "addv h2, v2.8h",
+        "addv h3, v3.8h",
+        "zip1 v16.2d, v2.2d, v3.2d"
       ]
     },
     "maskmovdqu xmm0, xmm1": {
@@ -1087,10 +1087,10 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xf7",
       "ExpectedArm64ASM": [
-        "cmlt v4.16b, v17.16b, #0",
-        "ldr q5, [x11]",
-        "bsl v4.16b, v16.16b, v5.16b",
-        "str q4, [x11]"
+        "cmlt v2.16b, v17.16b, #0",
+        "ldr q3, [x11]",
+        "bsl v2.16b, v16.16b, v3.16b",
+        "str q2, [x11]"
       ]
     },
     "psubb xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
index daa99152b..3f32c724c 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
@@ -15,8 +15,8 @@
       "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ext v4.16b, v17.16b, v17.16b, #8",
-        "fcadd v16.2d, v16.2d, v4.2d, #90"
+        "ext v2.16b, v17.16b, v17.16b, #8",
+        "fcadd v16.2d, v16.2d, v2.2d, #90"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
index 98e45aa3a..9d5f14786 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
@@ -16,11 +16,11 @@
         "0x66 0x0f 0xe4"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "umulh z4.h, p6/m, z4.h, z5.h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "umulh z2.h, p6/m, z2.h, z3.h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "pmulhw xmm0, xmm1": {
@@ -31,11 +31,11 @@
         "0x66 0x0f 0xe5"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "smulh z4.h, p6/m, z4.h, z5.h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "smulh z2.h, p6/m, z2.h, z3.h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index 5acdd81ef..9f8333ea7 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -45,8 +45,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x12",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "trn1 v16.4s, v4.4s, v4.4s"
+        "ldr q2, [x4]",
+        "trn1 v16.4s, v2.4s, v2.4s"
       ]
     },
     "movshdup xmm0, xmm1": {
@@ -62,8 +62,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x16",
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "trn2 v16.4s, v4.4s, v4.4s"
+        "ldr q2, [x4]",
+        "trn2 v16.4s, v2.4s, v2.4s"
       ]
     },
     "cvtsi2ss xmm0, eax": {
@@ -74,8 +74,8 @@
         "0xf3 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "scvtf s4, w4",
-        "mov v16.s[0], v4.s[0]"
+        "scvtf s2, w4",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cvtsi2ss xmm0, dword [rax]": {
@@ -86,9 +86,9 @@
         "0xf3 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr s4, [x4]",
-        "scvtf s4, s4",
-        "mov v16.s[0], v4.s[0]"
+        "ldr s2, [x4]",
+        "scvtf s2, s2",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cvtsi2ss xmm0, rax": {
@@ -96,8 +96,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x2a",
       "ExpectedArm64ASM": [
-        "scvtf s4, x4",
-        "mov v16.s[0], v4.s[0]"
+        "scvtf s2, x4",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cvtsi2ss xmm0, qword [rax]": {
@@ -109,8 +109,8 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x20, [x4]",
-        "scvtf s4, x20",
-        "mov v16.s[0], v4.s[0]"
+        "scvtf s2, x20",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "movntss [rax], xmm0": {
@@ -134,8 +134,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "ldr s4, [x7]",
-        "fcvtzs w4, s4"
+        "ldr s2, [x7]",
+        "fcvtzs w4, s2"
       ]
     },
     "cvttss2si rax, xmm0": {
@@ -151,8 +151,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "fcvtzs x4, s4"
+        "ldr d2, [x7]",
+        "fcvtzs x4, s2"
       ]
     },
     "cvtss2si eax, xmm0": {
@@ -169,8 +169,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "ldr s4, [x7]",
-        "frinti s0, s4",
+        "ldr s2, [x7]",
+        "frinti s0, s2",
         "fcvtzs w4, s0"
       ]
     },
@@ -188,8 +188,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "frinti s0, s4",
+        "ldr d2, [x7]",
+        "frinti s0, s2",
         "fcvtzs x4, s0"
       ]
     },
@@ -198,8 +198,8 @@
       "Optimal": "No",
       "Comment": "0xf3 0x0f 0x51",
       "ExpectedArm64ASM": [
-        "fsqrt s4, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fsqrt s2, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "rsqrtss xmm0, xmm1": {
@@ -212,8 +212,8 @@
       "ExpectedArm64ASM": [
         "fmov s0, #0x70 (1.0000)",
         "fsqrt s1, s17",
-        "fdiv s4, s0, s1",
-        "mov v16.s[0], v4.s[0]"
+        "fdiv s2, s0, s1",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "rcpss xmm0, xmm1": {
@@ -225,8 +225,8 @@
       ],
       "ExpectedArm64ASM": [
         "fmov s0, #0x70 (1.0000)",
-        "fdiv s4, s0, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fdiv s2, s0, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "addss xmm0, xmm1": {
@@ -237,8 +237,8 @@
         "0xf3 0x0f 0x58"
       ],
       "ExpectedArm64ASM": [
-        "fadd s4, s16, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fadd s2, s16, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "mulss xmm0, xmm1": {
@@ -249,8 +249,8 @@
         "0xf3 0x0f 0x59"
       ],
       "ExpectedArm64ASM": [
-        "fmul s4, s16, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fmul s2, s16, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cvtss2sd xmm0, xmm1": {
@@ -258,8 +258,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x5a",
       "ExpectedArm64ASM": [
-        "fcvt d4, s17",
-        "mov v16.d[0], v4.d[0]"
+        "fcvt d2, s17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtss2sd xmm0, [rax]": {
@@ -267,9 +267,9 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0x5a",
       "ExpectedArm64ASM": [
-        "ldr s4, [x4]",
-        "fcvt d4, s4",
-        "mov v16.d[0], v4.d[0]"
+        "ldr s2, [x4]",
+        "fcvt d2, s2",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvttps2dq xmm0, xmm1": {
@@ -288,8 +288,8 @@
         "0xf3 0x0f 0x5c"
       ],
       "ExpectedArm64ASM": [
-        "fsub s4, s16, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fsub s2, s16, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "minss xmm0, xmm1": {
@@ -301,8 +301,8 @@
       ],
       "ExpectedArm64ASM": [
         "fcmp s16, s17",
-        "fcsel s4, s16, s17, mi",
-        "mov v16.s[0], v4.s[0]"
+        "fcsel s2, s16, s17, mi",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "divss xmm0, xmm1": {
@@ -313,8 +313,8 @@
         "0xf3 0x0f 0x5e"
       ],
       "ExpectedArm64ASM": [
-        "fdiv s4, s16, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fdiv s2, s16, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "maxss xmm0, xmm1": {
@@ -326,8 +326,8 @@
       ],
       "ExpectedArm64ASM": [
         "fcmp s16, s17",
-        "fcsel s4, s17, s16, mi",
-        "mov v16.s[0], v4.s[0]"
+        "fcsel s2, s17, s16, mi",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "movdqu xmm0, xmm1": {
@@ -354,8 +354,8 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.8h, v17.h[4]",
-        "trn1 v16.2d, v17.2d, v4.2d"
+        "dup v2.8h, v17.h[4]",
+        "trn1 v16.2d, v17.2d, v2.2d"
       ]
     },
     "pshufhw xmm0, xmm1, 11100100b": {
@@ -377,8 +377,8 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "zip1 v4.8h, v17.8h, v17.8h",
-        "zip1 v16.2d, v17.2d, v4.2d"
+        "zip1 v2.8h, v17.8h, v17.8h",
+        "zip1 v16.2d, v17.2d, v2.2d"
       ]
     },
     "pshufhw xmm0, xmm1, 1": {
@@ -391,8 +391,8 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1624]",
-        "ldr q4, [x0, #16]",
-        "tbl v16.16b, {v17.16b}, v4.16b"
+        "ldr q2, [x0, #16]",
+        "tbl v16.16b, {v17.16b}, v2.16b"
       ]
     },
     "pshufhw xmm0, xmm1, 0xff": {
@@ -403,8 +403,8 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.8h, v17.h[7]",
-        "trn1 v16.2d, v17.2d, v4.2d"
+        "dup v2.8h, v17.h[7]",
+        "trn1 v16.2d, v17.2d, v2.2d"
       ]
     },
     "movq xmm0, xmm1": {
@@ -595,8 +595,8 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmeq s4, s16, s17",
-        "mov v16.s[0], v4.s[0]"
+        "fcmeq s2, s16, s17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 1": {
@@ -607,8 +607,8 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmgt s4, s17, s16",
-        "mov v16.s[0], v4.s[0]"
+        "fcmgt s2, s17, s16",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 2": {
@@ -619,8 +619,8 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmge s4, s17, s16",
-        "mov v16.s[0], v4.s[0]"
+        "fcmge s2, s17, s16",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 3": {
@@ -633,9 +633,9 @@
       "ExpectedArm64ASM": [
         "fcmge s0, s16, s17",
         "fcmgt s1, s17, s16",
-        "orr v4.8b, v0.8b, v1.8b",
-        "mvn v4.8b, v4.8b",
-        "mov v16.s[0], v4.s[0]"
+        "orr v2.8b, v0.8b, v1.8b",
+        "mvn v2.8b, v2.8b",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 4": {
@@ -646,9 +646,9 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmeq s4, s16, s17",
-        "mvn v4.8b, v4.8b",
-        "mov v16.s[0], v4.s[0]"
+        "fcmeq s2, s16, s17",
+        "mvn v2.8b, v2.8b",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 5": {
@@ -659,9 +659,9 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmgt s4, s17, s16",
-        "mvn v4.16b, v4.16b",
-        "mov v16.s[0], v4.s[0]"
+        "fcmgt s2, s17, s16",
+        "mvn v2.16b, v2.16b",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 6": {
@@ -672,9 +672,9 @@
         "0xf3 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmge s4, s17, s16",
-        "mvn v4.16b, v4.16b",
-        "mov v16.s[0], v4.s[0]"
+        "fcmge s2, s17, s16",
+        "mvn v2.16b, v2.16b",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cmpss xmm0, xmm1, 7": {
@@ -687,8 +687,8 @@
       "ExpectedArm64ASM": [
         "fcmge s0, s16, s17",
         "fcmgt s1, s17, s16",
-        "orr v4.8b, v0.8b, v1.8b",
-        "mov v16.s[0], v4.s[0]"
+        "orr v2.8b, v0.8b, v1.8b",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "movq2dq xmm0, mm0": {
@@ -704,8 +704,8 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0xe6",
       "ExpectedArm64ASM": [
-        "sxtl v4.2d, v17.2s",
-        "scvtf v16.2d, v4.2d"
+        "sxtl v2.2d, v17.2s",
+        "scvtf v16.2d, v2.2d"
       ]
     },
     "cvtdq2pd xmm0, [rax]": {
@@ -713,9 +713,9 @@
       "Optimal": "Yes",
       "Comment": "0xf3 0x0f 0xe6",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "sxtl v4.2d, v4.2s",
-        "scvtf v16.2d, v4.2d"
+        "ldr d2, [x4]",
+        "sxtl v2.2d, v2.2s",
+        "scvtf v16.2d, v2.2d"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index 81211c02c..412eea8bd 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -46,8 +46,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x12",
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "dup v16.2d, v4.d[0]"
+        "ldr d2, [x4]",
+        "dup v16.2d, v2.d[0]"
       ]
     },
     "cvtsi2sd xmm0, eax": {
@@ -58,8 +58,8 @@
         "0xf2 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "scvtf d4, w4",
-        "mov v16.d[0], v4.d[0]"
+        "scvtf d2, w4",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtsi2sd xmm0, dword [rax]": {
@@ -71,8 +71,8 @@
       ],
       "ExpectedArm64ASM": [
         "ldr w20, [x4]",
-        "scvtf d4, w20",
-        "mov v16.d[0], v4.d[0]"
+        "scvtf d2, w20",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtsi2sd xmm0, rax": {
@@ -83,8 +83,8 @@
         "0xf2 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "scvtf d4, x4",
-        "mov v16.d[0], v4.d[0]"
+        "scvtf d2, x4",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtsi2sd xmm0, qword [rax]": {
@@ -95,9 +95,9 @@
         "0xf2 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "scvtf d4, d4",
-        "mov v16.d[0], v4.d[0]"
+        "ldr d2, [x4]",
+        "scvtf d2, d2",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "movntsd [rax], xmm0": {
@@ -121,8 +121,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "fcvtzs w4, d4"
+        "ldr d2, [x7]",
+        "fcvtzs w4, d2"
       ]
     },
     "cvttsd2si rax, xmm0": {
@@ -138,8 +138,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x2c",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "fcvtzs x4, d4"
+        "ldr d2, [x7]",
+        "fcvtzs x4, d2"
       ]
     },
     "cvtsd2si eax, xmm0": {
@@ -156,8 +156,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "frinti d0, d4",
+        "ldr d2, [x7]",
+        "frinti d0, d2",
         "fcvtzs x4, d0"
       ]
     },
@@ -175,8 +175,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x2d",
       "ExpectedArm64ASM": [
-        "ldr d4, [x7]",
-        "frinti d0, d4",
+        "ldr d2, [x7]",
+        "frinti d0, d2",
         "fcvtzs x4, d0"
       ]
     },
@@ -188,8 +188,8 @@
         "0xf2 0x0f 0x51"
       ],
       "ExpectedArm64ASM": [
-        "fsqrt d4, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fsqrt d2, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "addsd xmm0, xmm1": {
@@ -200,8 +200,8 @@
         "0xf2 0x0f 0x58"
       ],
       "ExpectedArm64ASM": [
-        "fadd d4, d16, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fadd d2, d16, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "mulsd xmm0, xmm1": {
@@ -212,8 +212,8 @@
         "0xf2 0x0f 0x59"
       ],
       "ExpectedArm64ASM": [
-        "fmul d4, d16, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fmul d2, d16, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cvtsd2ss xmm0, xmm1": {
@@ -224,8 +224,8 @@
         "0xf2 0x0f 0x5a"
       ],
       "ExpectedArm64ASM": [
-        "fcvt s4, d17",
-        "mov v16.s[0], v4.s[0]"
+        "fcvt s2, d17",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "cvtsd2ss xmm0, [rax]": {
@@ -236,9 +236,9 @@
         "0xf2 0x0f 0x5a"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "fcvt s4, d4",
-        "mov v16.s[0], v4.s[0]"
+        "ldr d2, [x4]",
+        "fcvt s2, d2",
+        "mov v16.s[0], v2.s[0]"
       ]
     },
     "subsd xmm0, xmm1": {
@@ -249,8 +249,8 @@
         "0xf2 0x0f 0x5c"
       ],
       "ExpectedArm64ASM": [
-        "fsub d4, d16, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fsub d2, d16, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "minsd xmm0, xmm1": {
@@ -262,8 +262,8 @@
       ],
       "ExpectedArm64ASM": [
         "fcmp d16, d17",
-        "fcsel d4, d16, d17, mi",
-        "mov v16.d[0], v4.d[0]"
+        "fcsel d2, d16, d17, mi",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "divsd xmm0, xmm1": {
@@ -274,8 +274,8 @@
         "0xf2 0x0f 0x5e"
       ],
       "ExpectedArm64ASM": [
-        "fdiv d4, d16, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fdiv d2, d16, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "maxsd xmm0, xmm1": {
@@ -287,8 +287,8 @@
       ],
       "ExpectedArm64ASM": [
         "fcmp d16, d17",
-        "fcsel d4, d17, d16, mi",
-        "mov v16.d[0], v4.d[0]"
+        "fcsel d2, d17, d16, mi",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "pshuflw xmm0, xmm1, 0": {
@@ -299,8 +299,8 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.8h, v17.h[0]",
-        "trn2 v16.2d, v4.2d, v17.2d"
+        "dup v2.8h, v17.h[0]",
+        "trn2 v16.2d, v2.2d, v17.2d"
       ]
     },
     "pshuflw xmm0, xmm1, 11100100b": {
@@ -322,8 +322,8 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "zip1 v4.8h, v17.8h, v17.8h",
-        "zip1 v16.2d, v4.2d, v17.2d"
+        "zip1 v2.8h, v17.8h, v17.8h",
+        "zip1 v16.2d, v2.2d, v17.2d"
       ]
     },
     "pshuflw xmm0, xmm1, 1": {
@@ -336,8 +336,8 @@
       ],
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1616]",
-        "ldr q4, [x0, #16]",
-        "tbl v16.16b, {v17.16b}, v4.16b"
+        "ldr q2, [x0, #16]",
+        "tbl v16.16b, {v17.16b}, v2.16b"
       ]
     },
     "pshuflw xmm0, xmm1, 0xff": {
@@ -348,8 +348,8 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "dup v4.8h, v17.h[3]",
-        "trn2 v16.2d, v4.2d, v17.2d"
+        "dup v2.8h, v17.h[3]",
+        "trn2 v16.2d, v2.2d, v17.2d"
       ]
     },
     "insertq xmm0, xmm1, 0, 0": {
@@ -401,9 +401,9 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0x7d",
       "ExpectedArm64ASM": [
-        "uzp1 v4.4s, v16.4s, v17.4s",
-        "uzp2 v5.4s, v16.4s, v17.4s",
-        "fsub v16.4s, v4.4s, v5.4s"
+        "uzp1 v2.4s, v16.4s, v17.4s",
+        "uzp2 v3.4s, v16.4s, v17.4s",
+        "fsub v16.4s, v2.4s, v3.4s"
       ]
     },
     "cmpsd xmm0, xmm1, 0": {
@@ -414,8 +414,8 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmeq d4, d16, d17",
-        "mov v16.d[0], v4.d[0]"
+        "fcmeq d2, d16, d17",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 1": {
@@ -426,8 +426,8 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmgt d4, d17, d16",
-        "mov v16.d[0], v4.d[0]"
+        "fcmgt d2, d17, d16",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 2": {
@@ -438,8 +438,8 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmge d4, d17, d16",
-        "mov v16.d[0], v4.d[0]"
+        "fcmge d2, d17, d16",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 3": {
@@ -452,9 +452,9 @@
       "ExpectedArm64ASM": [
         "fcmge d0, d16, d17",
         "fcmgt d1, d17, d16",
-        "orr v4.8b, v0.8b, v1.8b",
-        "mvn v4.8b, v4.8b",
-        "mov v16.d[0], v4.d[0]"
+        "orr v2.8b, v0.8b, v1.8b",
+        "mvn v2.8b, v2.8b",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 4": {
@@ -465,9 +465,9 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmeq d4, d16, d17",
-        "mvn v4.8b, v4.8b",
-        "mov v16.d[0], v4.d[0]"
+        "fcmeq d2, d16, d17",
+        "mvn v2.8b, v2.8b",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 5": {
@@ -478,9 +478,9 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmgt d4, d17, d16",
-        "mvn v4.16b, v4.16b",
-        "mov v16.d[0], v4.d[0]"
+        "fcmgt d2, d17, d16",
+        "mvn v2.16b, v2.16b",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 6": {
@@ -491,9 +491,9 @@
         "0xf2 0x0f 0xc2"
       ],
       "ExpectedArm64ASM": [
-        "fcmge d4, d17, d16",
-        "mvn v4.16b, v4.16b",
-        "mov v16.d[0], v4.d[0]"
+        "fcmge d2, d17, d16",
+        "mvn v2.16b, v2.16b",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "cmpsd xmm0, xmm1, 7": {
@@ -506,8 +506,8 @@
       "ExpectedArm64ASM": [
         "fcmge d0, d16, d17",
         "fcmgt d1, d17, d16",
-        "orr v4.8b, v0.8b, v1.8b",
-        "mov v16.d[0], v4.d[0]"
+        "orr v2.8b, v0.8b, v1.8b",
+        "mov v16.d[0], v2.d[0]"
       ]
     },
     "addsubps xmm0, xmm1": {
@@ -516,9 +516,9 @@
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
         "ldr x0, [x28, #1568]",
-        "ldr q4, [x0]",
-        "eor v4.16b, v17.16b, v4.16b",
-        "fadd v16.4s, v16.4s, v4.4s"
+        "ldr q2, [x0]",
+        "eor v2.16b, v17.16b, v2.16b",
+        "fadd v16.4s, v16.4s, v2.4s"
       ]
     },
     "movdq2q mm0, xmm0": {
@@ -534,8 +534,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0xe6",
       "ExpectedArm64ASM": [
-        "fcvtn v4.2s, v17.2d",
-        "frinti v16.4s, v4.4s",
+        "fcvtn v2.2s, v17.2d",
+        "frinti v16.4s, v2.4s",
         "fcvtzs v16.4s, v16.4s"
       ]
     },
diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
index 8913dbbfa..bccaa001f 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
@@ -15,8 +15,8 @@
       "Optimal": "Yes",
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "rev64 v4.4s, v17.4s",
-        "fcadd v16.4s, v16.4s, v4.4s, #90"
+        "rev64 v2.4s, v17.4s",
+        "fcadd v16.4s, v16.4s, v2.4s, #90"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json
index ae4cf5c44..01caeb897 100644
--- a/unittests/InstructionCountCI/Secondary_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_SVE128.json
@@ -14,11 +14,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
-        "ushr v4.4s, v16.4s, #31",
-        "index z5.s, #0, #1",
-        "ushl v4.4s, v4.4s, v5.4s",
-        "addv s4, v4.4s",
-        "mov w4, v4.s[0]"
+        "ushr v2.4s, v16.4s, #31",
+        "index z3.s, #0, #1",
+        "ushl v2.4s, v2.4s, v3.4s",
+        "addv s2, v2.4s",
+        "mov w4, v2.s[0]"
       ]
     },
     "movmskps rax, xmm0": {
@@ -26,11 +26,11 @@
       "Optimal": "Yes",
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
-        "ushr v4.4s, v16.4s, #31",
-        "index z5.s, #0, #1",
-        "ushl v4.4s, v4.4s, v5.4s",
-        "addv s4, v4.4s",
-        "mov w4, v4.s[0]"
+        "ushr v2.4s, v16.4s, #31",
+        "index z3.s, #0, #1",
+        "ushl v2.4s, v2.4s, v3.4s",
+        "addv s2, v2.4s",
+        "mov w4, v2.s[0]"
       ]
     },
     "psrlw mm0, mm1": {
@@ -38,12 +38,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xd1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsr z4.h, p6/m, z4.h, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsr z2.h, p6/m, z2.h, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psrld mm0, mm1": {
@@ -51,12 +51,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xd2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsr z4.s, p6/m, z4.s, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsr z2.s, p6/m, z2.s, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psrlq mm0, mm1": {
@@ -64,12 +64,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xd3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsr z4.d, p6/m, z4.d, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsr z2.d, p6/m, z2.d, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psraw mm0, mm1": {
@@ -77,12 +77,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xe1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "asr z4.h, p6/m, z4.h, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "asr z2.h, p6/m, z2.h, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psrad mm0, mm1": {
@@ -90,12 +90,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xe2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "asr z4.s, p6/m, z4.s, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "asr z2.s, p6/m, z2.s, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psllw mm0, mm1": {
@@ -103,12 +103,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xf1",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsl z4.h, p6/m, z4.h, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsl z2.h, p6/m, z2.h, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "pslld mm0, mm1": {
@@ -116,12 +116,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xf2",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsl z4.s, p6/m, z4.s, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsl z2.s, p6/m, z2.s, z0.d",
+        "str d2, [x28, #752]"
       ]
     },
     "psllq mm0, mm1": {
@@ -129,12 +129,12 @@
       "Optimal": "No",
       "Comment": "0x0f 0xf3",
       "ExpectedArm64ASM": [
-        "ldr d4, [x28, #768]",
-        "ldr d5, [x28, #752]",
-        "mov z0.d, d4",
-        "movprfx z4, z5",
-        "lsl z4.d, p6/m, z4.d, z0.d",
-        "str d4, [x28, #752]"
+        "ldr d2, [x28, #768]",
+        "ldr d3, [x28, #752]",
+        "mov z0.d, d2",
+        "movprfx z2, z3",
+        "lsl z2.d, p6/m, z2.d, z0.d",
+        "str d2, [x28, #752]"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index c1983b9e9..ff4a963a7 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -19,8 +19,8 @@
         "Map 1 0b00 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovups ymm0, [rax]": {
@@ -31,8 +31,8 @@
         "Map 1 0b00 0x10 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovupd xmm0, [rax]": {
@@ -44,8 +44,8 @@
         "Map 1 0b01 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovupd ymm0, [rax]": {
@@ -56,8 +56,8 @@
         "Map 1 0b01 0x10 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovss xmm0, [rax]": {
@@ -69,8 +69,8 @@
         "Map 1 0b10 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr s4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr s2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovss xmm0, xmm1, xmm2": {
@@ -81,11 +81,11 @@
         "Map 1 0b10 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovsd xmm0, [rax]": {
@@ -97,8 +97,8 @@
         "Map 1 0b11 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr d2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovsd xmm0, xmm1, xmm2": {
@@ -109,11 +109,11 @@
         "Map 1 0b11 0x10 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovups [rax], xmm0": {
@@ -123,8 +123,8 @@
         "Map 1 0b00 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovups [rax], ymm0": {
@@ -134,8 +134,8 @@
         "Map 1 0b00 0x11 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vmovupd [rax], xmm0": {
@@ -145,8 +145,8 @@
         "Map 1 0b01 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovupd [rax], ymm0": {
@@ -156,8 +156,8 @@
         "Map 1 0b01 0x11 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vmovss [rax], xmm0": {
@@ -167,8 +167,8 @@
         "Map 1 0b10 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str s4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str s2, [x4]"
       ]
     },
     "db 0xc5, 0xf2, 0x11, 0xc2": {
@@ -181,11 +181,11 @@
         "Map 1 0b10 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z16.d",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z18.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z16.d",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z18.d, p7/m, z2.d"
       ]
     },
     "vmovsd [rax], xmm0": {
@@ -195,8 +195,8 @@
         "Map 1 0b11 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str d2, [x4]"
       ]
     },
     "db 0xc5, 0xf3, 0x11, 0xc2": {
@@ -209,11 +209,11 @@
         "Map 1 0b11 0x11 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z16.d",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z18.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z16.d",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z18.d, p7/m, z2.d"
       ]
     },
     "vmovlps xmm0, xmm1, [rax]": {
@@ -224,11 +224,11 @@
         "Map 1 0b00 0x12 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovlpd xmm0, xmm1, [rax]": {
@@ -239,11 +239,11 @@
         "Map 1 0b01 0x12 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovsldup xmm0, [rax]": {
@@ -253,10 +253,10 @@
         "Map 1 0b10 0x12 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "trn1 v4.4s, v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "trn1 v2.4s, v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovsldup ymm0, [rax]": {
@@ -266,9 +266,9 @@
         "Map 1 0b10 0x12 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "trn1 z4.s, z4.s, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "trn1 z2.s, z2.s, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovddup xmm0, [rax]": {
@@ -278,10 +278,10 @@
         "Map 1 0b11 0x12 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "dup v4.2d, v4.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr d2, [x4]",
+        "dup v2.2d, v2.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovddup ymm0, [rax]": {
@@ -291,9 +291,9 @@
         "Map 1 0b11 0x12 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "trn1 z4.d, z4.d, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "trn1 z2.d, z2.d, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovlps [rax], xmm0": {
@@ -303,8 +303,8 @@
         "Map 1 0b00 0x13 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str d2, [x4]"
       ]
     },
     "vmovlpd [rax], xmm0": {
@@ -314,8 +314,8 @@
         "Map 1 0b01 0x13 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str d2, [x4]"
       ]
     },
     "vunpcklps xmm0, xmm1, [rax]": {
@@ -325,11 +325,11 @@
         "Map 1 0b00 0x14 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "zip1 v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "zip1 v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpcklps ymm0, ymm1, [rax]": {
@@ -339,15 +339,15 @@
         "Map 1 0b00 0x14 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ld1b {z5.b}, p7/z, [x4]",
-        "zip1 z6.s, z4.s, z5.s",
-        "zip2 z4.s, z4.s, z5.s",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "ld1b {z3.b}, p7/z, [x4]",
+        "zip1 z4.s, z2.s, z3.s",
+        "zip2 z2.s, z2.s, z3.s",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpcklpd xmm0, xmm1, [rax]": {
@@ -357,11 +357,11 @@
         "Map 1 0b01 0x14 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "zip1 v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "zip1 v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpcklpd ymm0, ymm1, [rax]": {
@@ -371,15 +371,15 @@
         "Map 1 0b01 0x14 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ld1b {z5.b}, p7/z, [x4]",
-        "zip1 z6.d, z4.d, z5.d",
-        "zip2 z4.d, z4.d, z5.d",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "ld1b {z3.b}, p7/z, [x4]",
+        "zip1 z4.d, z2.d, z3.d",
+        "zip2 z2.d, z2.d, z3.d",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpckhps xmm0, xmm1, [rax]": {
@@ -389,11 +389,11 @@
         "Map 1 0b00 0x15 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "zip2 v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "zip2 v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpckhps ymm0, ymm1, [rax]": {
@@ -403,13 +403,13 @@
         "Map 1 0b00 0x15 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ld1b {z5.b}, p7/z, [x4]",
-        "zip1 z6.s, z4.s, z5.s",
-        "zip2 z4.s, z4.s, z5.s",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ld1b {z3.b}, p7/z, [x4]",
+        "zip1 z4.s, z2.s, z3.s",
+        "zip2 z2.s, z2.s, z3.s",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpckhpd xmm0, xmm1, [rax]": {
@@ -419,11 +419,11 @@
         "Map 1 0b01 0x15 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ldr q5, [x4]",
-        "zip2 v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ldr q3, [x4]",
+        "zip2 v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vunpckhpd ymm0, ymm1, [rax]": {
@@ -433,13 +433,13 @@
         "Map 1 0b01 0x15 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ld1b {z5.b}, p7/z, [x4]",
-        "zip1 z6.d, z4.d, z5.d",
-        "zip2 z4.d, z4.d, z5.d",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ld1b {z3.b}, p7/z, [x4]",
+        "zip1 z4.d, z2.d, z3.d",
+        "zip2 z2.d, z2.d, z3.d",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovhps xmm0, xmm1, [rax]": {
@@ -449,12 +449,12 @@
         "Map 1 0b00 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.8b, v4.8b",
-        "ldr d5, [x4]",
-        "mov v4.d[1], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.8b, v2.8b",
+        "ldr d3, [x4]",
+        "mov v2.d[1], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovhpd xmm0, xmm1, [rax]": {
@@ -464,12 +464,12 @@
         "Map 1 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.8b, v4.8b",
-        "ldr d5, [x4]",
-        "mov v4.d[1], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.8b, v2.8b",
+        "ldr d3, [x4]",
+        "mov v2.d[1], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovshdup xmm0, [rax]": {
@@ -479,10 +479,10 @@
         "Map 1 0b10 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "trn2 v4.4s, v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "trn2 v2.4s, v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovshdup ymm0, [rax]": {
@@ -492,9 +492,9 @@
         "Map 1 0b10 0x16 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "trn2 z4.s, z4.s, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "trn2 z2.s, z2.s, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovhps [rax], xmm0": {
@@ -504,9 +504,9 @@
         "Map 1 0b00 0x17 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov v4.d[0], v4.d[1]",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov v2.d[0], v2.d[1]",
+        "str d2, [x4]"
       ]
     },
     "vmovhpd [rax], xmm0": {
@@ -516,9 +516,9 @@
         "Map 1 0b01 0x17 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov v4.d[0], v4.d[1]",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov v2.d[0], v2.d[1]",
+        "str d2, [x4]"
       ]
     },
     "vmovmskps rax, xmm0": {
@@ -528,12 +528,12 @@
         "Map 1 0b00 0x50 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "ushr v4.4s, v4.4s, #31",
-        "index z5.s, #0, #1",
-        "ushl v4.4s, v4.4s, v5.4s",
-        "addv s4, v4.4s",
-        "mov w4, v4.s[0]"
+        "mov z2.d, p7/m, z16.d",
+        "ushr v2.4s, v2.4s, #31",
+        "index z3.s, #0, #1",
+        "ushl v2.4s, v2.4s, v3.4s",
+        "addv s2, v2.4s",
+        "mov w4, v2.s[0]"
       ]
     },
     "vmovmskps rax, ymm0": {
@@ -543,44 +543,44 @@
         "Map 1 0b00 0x50 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
+        "mov z2.d, p7/m, z16.d",
         "mov w20, #0x0",
-        "mov w21, v4.s[0]",
+        "mov w21, v2.s[0]",
         "lsr w21, w21, #31",
         "orr x20, x20, x21",
-        "mov w21, v4.s[1]",
+        "mov w21, v2.s[1]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #1",
         "orr x20, x20, x21",
-        "mov w21, v4.s[2]",
+        "mov w21, v2.s[2]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #2",
         "orr x20, x20, x21",
-        "mov w21, v4.s[3]",
+        "mov w21, v2.s[3]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #3",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov w21, v4.s[0]",
+        "compact z0.d, p0, z2.d",
+        "mov w21, v2.s[0]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #4",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov w21, v4.s[1]",
+        "compact z0.d, p0, z2.d",
+        "mov w21, v2.s[1]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #5",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov w21, v4.s[2]",
+        "compact z0.d, p0, z2.d",
+        "mov w21, v2.s[2]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #6",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov w21, v4.s[3]",
+        "compact z0.d, p0, z2.d",
+        "mov w21, v2.s[3]",
         "lsr w21, w21, #31",
         "lsl w21, w21, #7",
         "orr x20, x20, x21",
@@ -594,9 +594,9 @@
         "Map 1 0b01 0x50 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "uzp2 v4.4s, v4.4s, v4.4s",
-        "mov x20, v4.d[0]",
+        "mov z2.d, p7/m, z16.d",
+        "uzp2 v2.4s, v2.4s, v2.4s",
+        "mov x20, v2.d[0]",
         "bfi x20, x20, #31, #32",
         "lsr x4, x20, #62"
       ]
@@ -608,24 +608,24 @@
         "Map 1 0b01 0x50 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
+        "mov z2.d, p7/m, z16.d",
         "mov w20, #0x0",
-        "mov x21, v4.d[0]",
+        "mov x21, v2.d[0]",
         "lsr x21, x21, #63",
         "orr x20, x20, x21",
-        "mov x21, v4.d[1]",
+        "mov x21, v2.d[1]",
         "lsr x21, x21, #63",
         "lsl x21, x21, #1",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov x21, v4.d[0]",
+        "compact z0.d, p0, z2.d",
+        "mov x21, v2.d[0]",
         "lsr x21, x21, #63",
         "lsl x21, x21, #2",
         "orr x20, x20, x21",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "mov x21, v4.d[1]",
+        "compact z0.d, p0, z2.d",
+        "mov x21, v2.d[1]",
         "lsr x21, x21, #63",
         "lsl x21, x21, #3",
         "orr x20, x20, x21",
@@ -639,10 +639,10 @@
         "Map 1 0b00 0x51 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fsqrt v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fsqrt v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsqrtps ymm0, ymm1": {
@@ -652,9 +652,9 @@
         "Map 1 0b00 0x51 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fsqrt z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fsqrt z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsqrtpd xmm0, xmm1": {
@@ -664,10 +664,10 @@
         "Map 1 0b01 0x51 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fsqrt v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fsqrt v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsqrtpd ymm0, ymm1": {
@@ -677,9 +677,9 @@
         "Map 1 0b01 0x51 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fsqrt z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fsqrt z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsqrtss xmm0, xmm1, xmm2": {
@@ -690,14 +690,14 @@
         "Map 1 0b10 0x51 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z5.d, p7/m, z17.d",
-        "fsqrt s4, s4",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov z3.d, p7/m, z17.d",
+        "fsqrt s2, s2",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsqrtsd xmm0, xmm1, xmm2": {
@@ -708,14 +708,14 @@
         "Map 1 0b11 0x51 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z5.d, p7/m, z17.d",
-        "fsqrt d4, d4",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov z3.d, p7/m, z17.d",
+        "fsqrt d2, d2",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrsqrtps xmm0, xmm1": {
@@ -726,12 +726,12 @@
         "Map 1 0b00 0x52 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "fmov v0.4s, #0x70 (1.0000)",
-        "fsqrt v1.4s, v4.4s",
-        "fdiv v4.4s, v0.4s, v1.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "fsqrt v1.4s, v2.4s",
+        "fdiv v2.4s, v0.4s, v1.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrsqrtps ymm0, ymm1": {
@@ -742,11 +742,11 @@
         "Map 1 0b00 0x52 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fsqrt z0.s, p7/m, z4.s",
-        "fmov z4.s, #0x70 (1.0000)",
-        "fdiv z4.s, p7/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fsqrt z0.s, p7/m, z2.s",
+        "fmov z2.s, #0x70 (1.0000)",
+        "fdiv z2.s, p7/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrsqrtss xmm0, xmm1, xmm2": {
@@ -757,16 +757,16 @@
         "Map 1 0b10 0x52 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z18.d",
+        "mov z3.d, p7/m, z17.d",
         "fmov s0, #0x70 (1.0000)",
-        "fsqrt s1, s4",
-        "fdiv s4, s0, s1",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "fsqrt s1, s2",
+        "fdiv s2, s0, s1",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrcpps xmm0, xmm1": {
@@ -777,11 +777,11 @@
         "Map 1 0b00 0x53 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "fmov v0.4s, #0x70 (1.0000)",
-        "fdiv v4.4s, v0.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "fdiv v2.4s, v0.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrcpps ymm0, ymm1": {
@@ -792,11 +792,11 @@
         "Map 1 0b00 0x53 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "fmov z0.s, #0x70 (1.0000)",
-        "fdiv z0.s, p7/m, z0.s, z4.s",
-        "mov z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "fdiv z0.s, p7/m, z0.s, z2.s",
+        "mov z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vrcpss xmm0, xmm1, xmm2": {
@@ -807,15 +807,15 @@
         "Map 1 0b10 0x53 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z18.d",
+        "mov z3.d, p7/m, z17.d",
         "fmov s0, #0x70 (1.0000)",
-        "fdiv s4, s0, s4",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "fdiv s2, s0, s2",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandps xmm0, xmm1": {
@@ -825,11 +825,11 @@
         "Map 1 0b00 0x54 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandps ymm0, ymm1": {
@@ -839,10 +839,10 @@
         "Map 1 0b00 0x54 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandpd xmm0, xmm1": {
@@ -852,11 +852,11 @@
         "Map 1 0b01 0x54 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandpd ymm0, ymm1": {
@@ -866,10 +866,10 @@
         "Map 1 0b01 0x54 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandnps xmm0, xmm1": {
@@ -879,11 +879,11 @@
         "Map 1 0b00 0x55 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "bic v4.16b, v5.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "bic v2.16b, v3.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandnps ymm0, ymm1": {
@@ -893,10 +893,10 @@
         "Map 1 0b00 0x55 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "bic z4.d, z5.d, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "bic z2.d, z3.d, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandnpd xmm0, xmm1": {
@@ -906,11 +906,11 @@
         "Map 1 0b01 0x55 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "bic v4.16b, v5.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "bic v2.16b, v3.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vandnpd ymm0, ymm1": {
@@ -920,10 +920,10 @@
         "Map 1 0b01 0x55 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "bic z4.d, z5.d, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "bic z2.d, z3.d, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vorps xmm0, xmm1": {
@@ -933,11 +933,11 @@
         "Map 1 0b00 0x56 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "orr v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "orr v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vorps ymm0, ymm1": {
@@ -947,10 +947,10 @@
         "Map 1 0b00 0x56 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "orr z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "orr z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vorpd xmm0, xmm1": {
@@ -960,11 +960,11 @@
         "Map 1 0b01 0x56 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "orr v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "orr v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vorpd ymm0, ymm1": {
@@ -974,10 +974,10 @@
         "Map 1 0b01 0x56 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "orr z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "orr z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vxorps xmm0, xmm1": {
@@ -987,11 +987,11 @@
         "Map 1 0b00 0x57 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vxorps ymm0, ymm1": {
@@ -1001,10 +1001,10 @@
         "Map 1 0b00 0x57 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "eor z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "eor z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vxorpd xmm0, xmm1": {
@@ -1014,11 +1014,11 @@
         "Map 1 0b01 0x57 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vxorpd ymm0, ymm1": {
@@ -1028,10 +1028,10 @@
         "Map 1 0b01 0x57 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "eor z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "eor z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklbw xmm0, xmm1, xmm2": {
@@ -1041,11 +1041,11 @@
         "Map 1 0b01 0x60 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklbw ymm0, ymm1, ymm2": {
@@ -1055,15 +1055,15 @@
         "Map 1 0b01 0x60 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.b, z4.b, z5.b",
-        "zip2 z4.b, z4.b, z5.b",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.b, z2.b, z3.b",
+        "zip2 z2.b, z2.b, z3.b",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklwd xmm0, xmm1, xmm2": {
@@ -1073,11 +1073,11 @@
         "Map 1 0b01 0x61 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklwd ymm0, ymm1, ymm2": {
@@ -1087,15 +1087,15 @@
         "Map 1 0b01 0x61 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.h, z4.h, z5.h",
-        "zip2 z4.h, z4.h, z5.h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.h, z2.h, z3.h",
+        "zip2 z2.h, z2.h, z3.h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckldq xmm0, xmm1, xmm2": {
@@ -1105,11 +1105,11 @@
         "Map 1 0b01 0x62 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckldq ymm0, ymm1, ymm2": {
@@ -1119,15 +1119,15 @@
         "Map 1 0b01 0x62 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.s, z4.s, z5.s",
-        "zip2 z4.s, z4.s, z5.s",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.s, z2.s, z3.s",
+        "zip2 z2.s, z2.s, z3.s",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpacksswb xmm0, xmm1, xmm2": {
@@ -1137,12 +1137,12 @@
         "Map 1 0b01 0x63 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtn v4.8b, v4.8h",
-        "sqxtn2 v4.16b, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtn v2.8b, v2.8h",
+        "sqxtn2 v2.16b, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpacksswb ymm0, ymm1, ymm2": {
@@ -1152,24 +1152,24 @@
         "Map 1 0b01 0x63 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtnb z1.b, z5.h",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtnb z1.b, z3.h",
         "uzp1 z1.b, z1.b, z1.b",
-        "sqxtnb z4.b, z4.h",
-        "uzp1 z4.b, z4.b, z4.b",
-        "splice z4.b, p6, z4.b, z1.b",
-        "mov z1.d, z4.d[1]",
-        "mov z5.d, z4.d",
+        "sqxtnb z2.b, z2.h",
+        "uzp1 z2.b, z2.b, z2.b",
+        "splice z2.b, p6, z2.b, z1.b",
+        "mov z1.d, z2.d[1]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtb xmm0, xmm1, xmm2": {
@@ -1179,11 +1179,11 @@
         "Map 1 0b01 0x64 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmgt v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmgt v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtb ymm0, ymm1, ymm2": {
@@ -1193,13 +1193,13 @@
         "Map 1 0b01 0x64 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpgt p0.b, p7/z, z4.b, z5.b",
-        "not z0.b, p0/m, z4.b",
-        "movprfx z4.b, p0/z, z4.b",
-        "orr z4.b, p0/m, z4.b, z0.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpgt p0.b, p7/z, z2.b, z3.b",
+        "not z0.b, p0/m, z2.b",
+        "movprfx z2.b, p0/z, z2.b",
+        "orr z2.b, p0/m, z2.b, z0.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtw xmm0, xmm1, xmm2": {
@@ -1209,11 +1209,11 @@
         "Map 1 0b01 0x65 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmgt v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmgt v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtw ymm0, ymm1, ymm2": {
@@ -1223,13 +1223,13 @@
         "Map 1 0b01 0x65 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpgt p0.h, p7/z, z4.h, z5.h",
-        "not z0.h, p0/m, z4.h",
-        "movprfx z4.h, p0/z, z4.h",
-        "orr z4.h, p0/m, z4.h, z0.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpgt p0.h, p7/z, z2.h, z3.h",
+        "not z0.h, p0/m, z2.h",
+        "movprfx z2.h, p0/z, z2.h",
+        "orr z2.h, p0/m, z2.h, z0.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtd xmm0, xmm1, xmm2": {
@@ -1239,11 +1239,11 @@
         "Map 1 0b01 0x66 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmgt v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmgt v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtd ymm0, ymm1, ymm2": {
@@ -1253,13 +1253,13 @@
         "Map 1 0b01 0x66 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpgt p0.s, p7/z, z4.s, z5.s",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpgt p0.s, p7/z, z2.s, z3.s",
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackuswb xmm0, xmm1, xmm2": {
@@ -1269,12 +1269,12 @@
         "Map 1 0b01 0x67 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtun v4.8b, v4.8h",
-        "sqxtun2 v4.16b, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtun v2.8b, v2.8h",
+        "sqxtun2 v2.16b, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackuswb ymm0, ymm1, ymm2": {
@@ -1284,24 +1284,24 @@
         "Map 1 0b01 0x67 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtunb z1.b, z5.h",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtunb z1.b, z3.h",
         "uzp1 z1.b, z1.b, z1.b",
-        "sqxtunb z4.b, z4.h",
-        "uzp1 z4.b, z4.b, z4.b",
-        "splice z4.b, p6, z4.b, z1.b",
-        "mov z1.d, z4.d[1]",
-        "mov z5.d, z4.d",
+        "sqxtunb z2.b, z2.h",
+        "uzp1 z2.b, z2.b, z2.b",
+        "splice z2.b, p6, z2.b, z1.b",
+        "mov z1.d, z2.d[1]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd xmm0, xmm1, 00b": {
@@ -1311,17 +1311,17 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd xmm0, xmm1, 01b": {
@@ -1331,17 +1331,17 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[1]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[1]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd xmm0, xmm1, 10b": {
@@ -1351,17 +1351,17 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[2]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[2]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd xmm0, xmm1, 11b": {
@@ -1371,17 +1371,17 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[3]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[3]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd ymm0, ymm1, 00b": {
@@ -1391,42 +1391,42 @@
         "Map 1 0b01 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.s, s4",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.s, s2",
+        "mov z3.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd ymm0, ymm1, 01b": {
@@ -1436,42 +1436,42 @@
         "Map 1 0b01 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.s, z4.s[1]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.s, z2.s[1]",
+        "mov z3.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd ymm0, ymm1, 10b": {
@@ -1481,42 +1481,42 @@
         "Map 1 0b01 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.s, z4.s[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.s, z2.s[2]",
+        "mov z3.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufd ymm0, ymm1, 11b": {
@@ -1526,42 +1526,42 @@
         "Map 1 0b01 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.s, z4.s[3]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.s, z2.s[3]",
+        "mov z3.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw xmm0, xmm1, 00b": {
@@ -1571,17 +1571,17 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[4], v4.h[4]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[5], v4.h[4]",
-        "mov v5.h[6], v4.h[4]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[7], v4.h[4]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[4], v2.h[4]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[5], v2.h[4]",
+        "mov v3.h[6], v2.h[4]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[7], v2.h[4]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw xmm0, xmm1, 01b": {
@@ -1591,17 +1591,17 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[4], v4.h[5]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[5], v4.h[4]",
-        "mov v5.h[6], v4.h[4]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[7], v4.h[4]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[4], v2.h[5]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[5], v2.h[4]",
+        "mov v3.h[6], v2.h[4]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[7], v2.h[4]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw xmm0, xmm1, 10b": {
@@ -1611,17 +1611,17 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[4], v4.h[6]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[5], v4.h[4]",
-        "mov v5.h[6], v4.h[4]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[7], v4.h[4]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[4], v2.h[6]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[5], v2.h[4]",
+        "mov v3.h[6], v2.h[4]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[7], v2.h[4]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw xmm0, xmm1, 11b": {
@@ -1631,17 +1631,17 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[4], v4.h[7]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[5], v4.h[4]",
-        "mov v5.h[6], v4.h[4]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[7], v4.h[4]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[4], v2.h[7]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[5], v2.h[4]",
+        "mov v3.h[6], v2.h[4]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[7], v2.h[4]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw ymm0, ymm1, 00b": {
@@ -1651,42 +1651,42 @@
         "Map 1 0b10 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[4]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[4]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-3",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #7",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw ymm0, ymm1, 01b": {
@@ -1696,42 +1696,42 @@
         "Map 1 0b10 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[5]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[5]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[13]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[13]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-3",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #7",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw ymm0, ymm1, 10b": {
@@ -1741,42 +1741,42 @@
         "Map 1 0b10 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[6]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[6]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[14]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[14]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-3",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #7",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufhw ymm0, ymm1, 11b": {
@@ -1786,42 +1786,42 @@
         "Map 1 0b10 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[7]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[7]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[15]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[15]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-3",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #7",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw xmm0, xmm1, 00b": {
@@ -1831,17 +1831,17 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[0], v4.h[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[1], v4.h[0]",
-        "mov v5.h[2], v4.h[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[3], v4.h[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[0], v2.h[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[1], v2.h[0]",
+        "mov v3.h[2], v2.h[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[3], v2.h[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw xmm0, xmm1, 01b": {
@@ -1851,17 +1851,17 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[0], v4.h[1]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[1], v4.h[0]",
-        "mov v5.h[2], v4.h[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[3], v4.h[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[0], v2.h[1]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[1], v2.h[0]",
+        "mov v3.h[2], v2.h[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[3], v2.h[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw xmm0, xmm1, 10b": {
@@ -1871,17 +1871,17 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[0], v4.h[2]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[1], v4.h[0]",
-        "mov v5.h[2], v4.h[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[3], v4.h[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[0], v2.h[2]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[1], v2.h[0]",
+        "mov v3.h[2], v2.h[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[3], v2.h[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw xmm0, xmm1, 11b": {
@@ -1891,17 +1891,17 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.h[0], v4.h[3]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[1], v4.h[0]",
-        "mov v5.h[2], v4.h[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[3], v4.h[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.h[0], v2.h[3]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[1], v2.h[0]",
+        "mov v3.h[2], v2.h[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[3], v2.h[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw ymm0, ymm1, 00b": {
@@ -1911,42 +1911,42 @@
         "Map 1 0b11 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, h4",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, h2",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-8",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #0",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-7",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #3",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw ymm0, ymm1, 01b": {
@@ -1956,42 +1956,42 @@
         "Map 1 0b11 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[1]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[1]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-8",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[9]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[9]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #0",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-7",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #3",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw ymm0, ymm1, 10b": {
@@ -2001,42 +2001,42 @@
         "Map 1 0b11 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[2]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-8",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[10]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[10]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #0",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-7",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #3",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshuflw ymm0, ymm1, 11b": {
@@ -2046,42 +2046,42 @@
         "Map 1 0b11 0x70 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z1.h, z4.h[3]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z1.h, z2.h[3]",
+        "mov z3.d, z2.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-8",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[11]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[11]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #0",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-7",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, h4",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, h2",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[8]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[8]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #3",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqb xmm0, xmm1, xmm2": {
@@ -2091,11 +2091,11 @@
         "Map 1 0b01 0x74 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmeq v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmeq v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqb ymm0, ymm1, ymm2": {
@@ -2105,13 +2105,13 @@
         "Map 1 0b01 0x74 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpeq p0.b, p7/z, z4.b, z5.b",
-        "not z0.b, p0/m, z4.b",
-        "movprfx z4.b, p0/z, z4.b",
-        "orr z4.b, p0/m, z4.b, z0.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpeq p0.b, p7/z, z2.b, z3.b",
+        "not z0.b, p0/m, z2.b",
+        "movprfx z2.b, p0/z, z2.b",
+        "orr z2.b, p0/m, z2.b, z0.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqw xmm0, xmm1, xmm2": {
@@ -2121,11 +2121,11 @@
         "Map 1 0b01 0x75 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmeq v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmeq v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqw ymm0, ymm1, ymm2": {
@@ -2135,13 +2135,13 @@
         "Map 1 0b01 0x75 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpeq p0.h, p7/z, z4.h, z5.h",
-        "not z0.h, p0/m, z4.h",
-        "movprfx z4.h, p0/z, z4.h",
-        "orr z4.h, p0/m, z4.h, z0.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpeq p0.h, p7/z, z2.h, z3.h",
+        "not z0.h, p0/m, z2.h",
+        "movprfx z2.h, p0/z, z2.h",
+        "orr z2.h, p0/m, z2.h, z0.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqd xmm0, xmm1, xmm2": {
@@ -2151,11 +2151,11 @@
         "Map 1 0b01 0x76 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmeq v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmeq v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqd ymm0, ymm1, ymm2": {
@@ -2165,13 +2165,13 @@
         "Map 1 0b01 0x76 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpeq p0.s, p7/z, z4.s, z5.s",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpeq p0.s, p7/z, z2.s, z3.s",
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vzeroupper": {
@@ -2181,54 +2181,54 @@
         "Map 1 0b01 0x77 L=0"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z17.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z18.d",
-        "mov v4.16b, v4.16b",
-        "mov z18.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z19.d",
-        "mov v4.16b, v4.16b",
-        "mov z19.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z20.d",
-        "mov v4.16b, v4.16b",
-        "mov z20.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z21.d",
-        "mov v4.16b, v4.16b",
-        "mov z21.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z22.d",
-        "mov v4.16b, v4.16b",
-        "mov z22.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z23.d",
-        "mov v4.16b, v4.16b",
-        "mov z23.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z24.d",
-        "mov v4.16b, v4.16b",
-        "mov z24.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z25.d",
-        "mov v4.16b, v4.16b",
-        "mov z25.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z26.d",
-        "mov v4.16b, v4.16b",
-        "mov z26.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z27.d",
-        "mov v4.16b, v4.16b",
-        "mov z27.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z28.d",
-        "mov v4.16b, v4.16b",
-        "mov z28.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z29.d",
-        "mov v4.16b, v4.16b",
-        "mov z29.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z30.d",
-        "mov v4.16b, v4.16b",
-        "mov z30.d, p7/m, z4.d",
-        "mov z4.d, p7/m, z31.d",
-        "mov v4.16b, v4.16b",
-        "mov z31.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z17.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z18.d",
+        "mov v2.16b, v2.16b",
+        "mov z18.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z19.d",
+        "mov v2.16b, v2.16b",
+        "mov z19.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z20.d",
+        "mov v2.16b, v2.16b",
+        "mov z20.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z21.d",
+        "mov v2.16b, v2.16b",
+        "mov z21.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z22.d",
+        "mov v2.16b, v2.16b",
+        "mov z22.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z23.d",
+        "mov v2.16b, v2.16b",
+        "mov z23.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z24.d",
+        "mov v2.16b, v2.16b",
+        "mov z24.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z25.d",
+        "mov v2.16b, v2.16b",
+        "mov z25.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z26.d",
+        "mov v2.16b, v2.16b",
+        "mov z26.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z27.d",
+        "mov v2.16b, v2.16b",
+        "mov z27.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z28.d",
+        "mov v2.16b, v2.16b",
+        "mov z28.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z29.d",
+        "mov v2.16b, v2.16b",
+        "mov z29.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z30.d",
+        "mov v2.16b, v2.16b",
+        "mov z30.d, p7/m, z2.d",
+        "mov z2.d, p7/m, z31.d",
+        "mov v2.16b, v2.16b",
+        "mov z31.d, p7/m, z2.d"
       ]
     },
     "vzeroall": {
@@ -2239,23 +2239,23 @@
         "Map 1 0b01 0x77 L=1"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d",
-        "mov z17.d, p7/m, z4.d",
-        "mov z18.d, p7/m, z4.d",
-        "mov z19.d, p7/m, z4.d",
-        "mov z20.d, p7/m, z4.d",
-        "mov z21.d, p7/m, z4.d",
-        "mov z22.d, p7/m, z4.d",
-        "mov z23.d, p7/m, z4.d",
-        "mov z24.d, p7/m, z4.d",
-        "mov z25.d, p7/m, z4.d",
-        "mov z26.d, p7/m, z4.d",
-        "mov z27.d, p7/m, z4.d",
-        "mov z28.d, p7/m, z4.d",
-        "mov z29.d, p7/m, z4.d",
-        "mov z30.d, p7/m, z4.d",
-        "mov z31.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d",
+        "mov z17.d, p7/m, z2.d",
+        "mov z18.d, p7/m, z2.d",
+        "mov z19.d, p7/m, z2.d",
+        "mov z20.d, p7/m, z2.d",
+        "mov z21.d, p7/m, z2.d",
+        "mov z22.d, p7/m, z2.d",
+        "mov z23.d, p7/m, z2.d",
+        "mov z24.d, p7/m, z2.d",
+        "mov z25.d, p7/m, z2.d",
+        "mov z26.d, p7/m, z2.d",
+        "mov z27.d, p7/m, z2.d",
+        "mov z28.d, p7/m, z2.d",
+        "mov z29.d, p7/m, z2.d",
+        "mov z30.d, p7/m, z2.d",
+        "mov z31.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x00": {
@@ -2265,11 +2265,11 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x00": {
@@ -2279,13 +2279,13 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq p0.s, p7/z, z4.s, z5.s",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq p0.s, p7/z, z2.s, z3.s",
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x01": {
@@ -2295,11 +2295,11 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v4.4s, v5.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v2.4s, v3.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x01": {
@@ -2309,13 +2309,13 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.s, p7/z, z5.s, z4.s",
-        "not z0.s, p0/m, z5.s",
-        "movprfx z4.s, p0/z, z5.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.s, p7/z, z3.s, z2.s",
+        "not z0.s, p0/m, z3.s",
+        "movprfx z2.s, p0/z, z3.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x02": {
@@ -2325,11 +2325,11 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v4.4s, v5.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v2.4s, v3.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x02": {
@@ -2339,13 +2339,13 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge p0.s, p7/z, z5.s, z4.s",
-        "not z0.s, p0/m, z5.s",
-        "movprfx z4.s, p0/z, z5.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge p0.s, p7/z, z3.s, z2.s",
+        "not z0.s, p0/m, z3.s",
+        "movprfx z2.s, p0/z, z3.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x03": {
@@ -2355,14 +2355,14 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v0.4s, v4.4s, v5.4s",
-        "fcmgt v1.4s, v5.4s, v4.4s",
-        "orr v4.16b, v0.16b, v1.16b",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v0.4s, v2.4s, v3.4s",
+        "fcmgt v1.4s, v3.4s, v2.4s",
+        "orr v2.16b, v0.16b, v1.16b",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x03": {
@@ -2372,13 +2372,13 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmuo p0.s, p7/z, z4.s, z5.s",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmuo p0.s, p7/z, z2.s, z3.s",
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x04": {
@@ -2388,12 +2388,12 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq v4.4s, v4.4s, v5.4s",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq v2.4s, v2.4s, v3.4s",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x04": {
@@ -2403,13 +2403,13 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmne p0.s, p7/z, z4.s, z5.s",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmne p0.s, p7/z, z2.s, z3.s",
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x05": {
@@ -2419,12 +2419,12 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v4.4s, v5.4s, v4.4s",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v2.4s, v3.4s, v2.4s",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x05": {
@@ -2434,14 +2434,14 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.s, p7/z, z5.s, z4.s",
-        "not z0.s, p0/m, z5.s",
-        "movprfx z4.s, p0/z, z5.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "not z4.b, p7/m, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.s, p7/z, z3.s, z2.s",
+        "not z0.s, p0/m, z3.s",
+        "movprfx z2.s, p0/z, z3.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "not z2.b, p7/m, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x06": {
@@ -2451,12 +2451,12 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v4.4s, v5.4s, v4.4s",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v2.4s, v3.4s, v2.4s",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x06": {
@@ -2466,14 +2466,14 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge p0.s, p7/z, z5.s, z4.s",
-        "not z0.s, p0/m, z5.s",
-        "movprfx z4.s, p0/z, z5.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "not z4.b, p7/m, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge p0.s, p7/z, z3.s, z2.s",
+        "not z0.s, p0/m, z3.s",
+        "movprfx z2.s, p0/z, z3.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "not z2.b, p7/m, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps xmm0, xmm1, xmm2, 0x07": {
@@ -2483,13 +2483,13 @@
         "Map 1 0b00 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v0.4s, v4.4s, v5.4s",
-        "fcmgt v1.4s, v5.4s, v4.4s",
-        "orr v4.16b, v0.16b, v1.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v0.4s, v2.4s, v3.4s",
+        "fcmgt v1.4s, v3.4s, v2.4s",
+        "orr v2.16b, v0.16b, v1.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpps ymm0, ymm1, ymm2, 0x07": {
@@ -2499,14 +2499,14 @@
         "Map 1 0b00 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmuo p0.s, p7/z, z4.s, z5.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmuo p0.s, p7/z, z2.s, z3.s",
         "not p0.b, p7/z, p0.b",
-        "not z0.s, p0/m, z4.s",
-        "movprfx z4.s, p0/z, z4.s",
-        "orr z4.s, p0/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "not z0.s, p0/m, z2.s",
+        "movprfx z2.s, p0/z, z2.s",
+        "orr z2.s, p0/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x00": {
@@ -2516,11 +2516,11 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x00": {
@@ -2530,13 +2530,13 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq p0.d, p7/z, z4.d, z5.d",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq p0.d, p7/z, z2.d, z3.d",
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x01": {
@@ -2546,11 +2546,11 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v4.2d, v5.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v2.2d, v3.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x01": {
@@ -2560,13 +2560,13 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.d, p7/z, z5.d, z4.d",
-        "not z0.d, p0/m, z5.d",
-        "movprfx z4.d, p0/z, z5.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.d, p7/z, z3.d, z2.d",
+        "not z0.d, p0/m, z3.d",
+        "movprfx z2.d, p0/z, z3.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x02": {
@@ -2576,11 +2576,11 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v4.2d, v5.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v2.2d, v3.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x02": {
@@ -2590,13 +2590,13 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge p0.d, p7/z, z5.d, z4.d",
-        "not z0.d, p0/m, z5.d",
-        "movprfx z4.d, p0/z, z5.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge p0.d, p7/z, z3.d, z2.d",
+        "not z0.d, p0/m, z3.d",
+        "movprfx z2.d, p0/z, z3.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x03": {
@@ -2606,14 +2606,14 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v0.2d, v4.2d, v5.2d",
-        "fcmgt v1.2d, v5.2d, v4.2d",
-        "orr v4.16b, v0.16b, v1.16b",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v0.2d, v2.2d, v3.2d",
+        "fcmgt v1.2d, v3.2d, v2.2d",
+        "orr v2.16b, v0.16b, v1.16b",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x03": {
@@ -2623,13 +2623,13 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmuo p0.d, p7/z, z4.d, z5.d",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmuo p0.d, p7/z, z2.d, z3.d",
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x04": {
@@ -2639,12 +2639,12 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq v4.2d, v4.2d, v5.2d",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq v2.2d, v2.2d, v3.2d",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x04": {
@@ -2654,13 +2654,13 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmne p0.d, p7/z, z4.d, z5.d",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmne p0.d, p7/z, z2.d, z3.d",
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x05": {
@@ -2670,12 +2670,12 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v4.2d, v5.2d, v4.2d",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v2.2d, v3.2d, v2.2d",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x05": {
@@ -2685,14 +2685,14 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.d, p7/z, z5.d, z4.d",
-        "not z0.d, p0/m, z5.d",
-        "movprfx z4.d, p0/z, z5.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "not z4.b, p7/m, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.d, p7/z, z3.d, z2.d",
+        "not z0.d, p0/m, z3.d",
+        "movprfx z2.d, p0/z, z3.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "not z2.b, p7/m, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x06": {
@@ -2702,12 +2702,12 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v4.2d, v5.2d, v4.2d",
-        "mvn v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v2.2d, v3.2d, v2.2d",
+        "mvn v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x06": {
@@ -2717,14 +2717,14 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge p0.d, p7/z, z5.d, z4.d",
-        "not z0.d, p0/m, z5.d",
-        "movprfx z4.d, p0/z, z5.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "not z4.b, p7/m, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge p0.d, p7/z, z3.d, z2.d",
+        "not z0.d, p0/m, z3.d",
+        "movprfx z2.d, p0/z, z3.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "not z2.b, p7/m, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd xmm0, xmm1, xmm2, 0x07": {
@@ -2734,13 +2734,13 @@
         "Map 1 0b01 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge v0.2d, v4.2d, v5.2d",
-        "fcmgt v1.2d, v5.2d, v4.2d",
-        "orr v4.16b, v0.16b, v1.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge v0.2d, v2.2d, v3.2d",
+        "fcmgt v1.2d, v3.2d, v2.2d",
+        "orr v2.16b, v0.16b, v1.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmppd ymm0, ymm1, ymm2, 0x07": {
@@ -2750,14 +2750,14 @@
         "Map 1 0b01 0xC2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmuo p0.d, p7/z, z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmuo p0.d, p7/z, z2.d, z3.d",
         "not p0.b, p7/z, p0.b",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x00": {
@@ -2767,12 +2767,12 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq s5, s4, s5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq s3, s2, s3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x01": {
@@ -2782,12 +2782,12 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt s5, s5, s4",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt s3, s3, s2",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x02": {
@@ -2797,12 +2797,12 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge s5, s5, s4",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge s3, s3, s2",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x03": {
@@ -2812,15 +2812,15 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge s0, s4, s5",
-        "fcmgt s1, s5, s4",
-        "orr v5.8b, v0.8b, v1.8b",
-        "mvn v5.8b, v5.8b",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge s0, s2, s3",
+        "fcmgt s1, s3, s2",
+        "orr v3.8b, v0.8b, v1.8b",
+        "mvn v3.8b, v3.8b",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x04": {
@@ -2830,13 +2830,13 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq s5, s4, s5",
-        "mvn v5.8b, v5.8b",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq s3, s2, s3",
+        "mvn v3.8b, v3.8b",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x05": {
@@ -2846,13 +2846,13 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt s5, s5, s4",
-        "mvn v5.16b, v5.16b",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt s3, s3, s2",
+        "mvn v3.16b, v3.16b",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x06": {
@@ -2862,13 +2862,13 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge s5, s5, s4",
-        "mvn v5.16b, v5.16b",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge s3, s3, s2",
+        "mvn v3.16b, v3.16b",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpss xmm0, xmm1, xmm2, 0x07": {
@@ -2878,14 +2878,14 @@
         "Map 1 0b10 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge s0, s4, s5",
-        "fcmgt s1, s5, s4",
-        "orr v5.8b, v0.8b, v1.8b",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge s0, s2, s3",
+        "fcmgt s1, s3, s2",
+        "orr v3.8b, v0.8b, v1.8b",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x00": {
@@ -2895,12 +2895,12 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq d5, d4, d5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq d3, d2, d3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x01": {
@@ -2910,12 +2910,12 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt d5, d5, d4",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt d3, d3, d2",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x02": {
@@ -2925,12 +2925,12 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge d5, d5, d4",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge d3, d3, d2",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x03": {
@@ -2940,15 +2940,15 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge d0, d4, d5",
-        "fcmgt d1, d5, d4",
-        "orr v5.8b, v0.8b, v1.8b",
-        "mvn v5.8b, v5.8b",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge d0, d2, d3",
+        "fcmgt d1, d3, d2",
+        "orr v3.8b, v0.8b, v1.8b",
+        "mvn v3.8b, v3.8b",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x04": {
@@ -2958,13 +2958,13 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmeq d5, d4, d5",
-        "mvn v5.8b, v5.8b",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmeq d3, d2, d3",
+        "mvn v3.8b, v3.8b",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x05": {
@@ -2974,13 +2974,13 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt d5, d5, d4",
-        "mvn v5.16b, v5.16b",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt d3, d3, d2",
+        "mvn v3.16b, v3.16b",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x06": {
@@ -2990,13 +2990,13 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge d5, d5, d4",
-        "mvn v5.16b, v5.16b",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge d3, d3, d2",
+        "mvn v3.16b, v3.16b",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcmpsd xmm0, xmm1, xmm2, 0x07": {
@@ -3006,14 +3006,14 @@
         "Map 1 0b11 0xC2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmge d0, d4, d5",
-        "fcmgt d1, d5, d4",
-        "orr v5.8b, v0.8b, v1.8b",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmge d0, d2, d3",
+        "fcmgt d1, d3, d2",
+        "orr v3.8b, v0.8b, v1.8b",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrw xmm0, xmm1, eax, 000b": {
@@ -3024,10 +3024,10 @@
       ],
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.h[0], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.h[0], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrw xmm0, xmm1, eax, 001b": {
@@ -3038,10 +3038,10 @@
       ],
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.h[1], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.h[1], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrw xmm0, xmm1, eax, 111b": {
@@ -3052,10 +3052,10 @@
       ],
       "ExpectedArm64ASM": [
         "uxth w20, w4",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.h[7], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.h[7], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpextrw eax, xmm0, 000b": {
@@ -3065,8 +3065,8 @@
         "Map 1 0b01 0xC5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.h[0]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.h[0]",
         "uxth x4, w20"
       ]
     },
@@ -3077,8 +3077,8 @@
         "Map 1 0b01 0xC5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.h[1]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.h[1]",
         "uxth x4, w20"
       ]
     },
@@ -3089,8 +3089,8 @@
         "Map 1 0b01 0xC5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.h[7]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.h[7]",
         "uxth x4, w20"
       ]
     },
@@ -3101,18 +3101,18 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v6.16b, v0.16b",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[0]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[0]",
         "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[0]",
-        "mov v4.s[3], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[0]",
+        "mov v2.s[3], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps ymm0, ymm1, ymm2, 00b": {
@@ -3122,43 +3122,43 @@
         "Map 1 0b00 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.s, s4",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.s, s2",
+        "mov z4.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps xmm0, xmm1, xmm2, 01b": {
@@ -3168,18 +3168,18 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[1]",
-        "mov v6.16b, v0.16b",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[0]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[1]",
         "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[0]",
-        "mov v4.s[3], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[0]",
+        "mov v2.s[3], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps ymm0, ymm1, ymm2, 01b": {
@@ -3189,43 +3189,43 @@
         "Map 1 0b00 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.s, z4.s[1]",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.s, z2.s[1]",
+        "mov z4.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps xmm0, xmm1, xmm2, 10b": {
@@ -3235,18 +3235,18 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[2]",
-        "mov v6.16b, v0.16b",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[0]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[2]",
         "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[0]",
-        "mov v4.s[3], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[0]",
+        "mov v2.s[3], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps ymm0, ymm1, ymm2, 10b": {
@@ -3256,43 +3256,43 @@
         "Map 1 0b00 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.s, z4.s[2]",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.s, z2.s[2]",
+        "mov z4.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps xmm0, xmm1, xmm2, 11b": {
@@ -3302,18 +3302,18 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v0.16b, v4.16b",
-        "mov v0.s[0], v4.s[3]",
-        "mov v6.16b, v0.16b",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[0]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v0.16b, v2.16b",
+        "mov v0.s[0], v2.s[3]",
         "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[0]",
-        "mov v4.s[3], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[0]",
+        "mov v2.s[3], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufps ymm0, ymm1, ymm2, 11b": {
@@ -3323,43 +3323,43 @@
         "Map 1 0b00 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.s, z4.s[3]",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.s, z2.s[3]",
+        "mov z4.d, z2.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s5",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufpd xmm0, xmm1, xmm2, 0b": {
@@ -3369,12 +3369,12 @@
         "Map 1 0b01 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.d[0], v4.d[0]",
-        "mov v4.d[1], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.d[0], v2.d[0]",
+        "mov v2.d[1], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufpd ymm0, ymm1, ymm2, 0b": {
@@ -3384,27 +3384,27 @@
         "Map 1 0b01 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.d, d4",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.d, d2",
+        "mov z4.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, d5",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufpd xmm0, xmm1, xmm2, 1b": {
@@ -3414,12 +3414,12 @@
         "Map 1 0b01 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.d[0], v4.d[1]",
-        "mov v4.d[1], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.d[0], v2.d[1]",
+        "mov v2.d[1], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vshufpd ymm0, ymm1, ymm2, 1b": {
@@ -3429,27 +3429,27 @@
         "Map 1 0b01 0xC6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.d, z4.d[1]",
-        "mov z6.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.d, z2.d[1]",
+        "mov z4.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, d5",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovaps xmm0, [rax]": {
@@ -3459,8 +3459,8 @@
         "Map 1 0b00 0x28 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovaps ymm0, [rax]": {
@@ -3470,8 +3470,8 @@
         "Map 1 0b00 0x28 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovaps xmm0, xmm1": {
@@ -3481,9 +3481,9 @@
         "Map 1 0b00 0x29 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovaps ymm0, ymm1": {
@@ -3493,8 +3493,8 @@
         "Map 1 0b00 0x29 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovapd xmm0, [rax]": {
@@ -3504,8 +3504,8 @@
         "Map 1 0b01 0x28 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovapd ymm0, [rax]": {
@@ -3515,8 +3515,8 @@
         "Map 1 0b01 0x28 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovapd xmm0, xmm1": {
@@ -3526,9 +3526,9 @@
         "Map 1 0b01 0x29 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovapd ymm0, ymm1": {
@@ -3538,8 +3538,8 @@
         "Map 1 0b01 0x29 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovaps [rax], xmm0": {
@@ -3549,8 +3549,8 @@
         "Map 1 0b00 0x29 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovaps [rax], ymm0": {
@@ -3560,8 +3560,8 @@
         "Map 1 0b00 0x29 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vmovapd [rax], xmm0": {
@@ -3571,8 +3571,8 @@
         "Map 1 0b01 0x29 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovapd [rax], ymm0": {
@@ -3582,8 +3582,8 @@
         "Map 1 0b01 0x29 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vcvtsi2ss xmm0, xmm1, eax": {
@@ -3593,11 +3593,11 @@
         "Map 1 0b10 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf s5, w4",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf s3, w4",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtsi2ss xmm0, xmm1, rax": {
@@ -3607,11 +3607,11 @@
         "Map 1 0b10 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf s5, x4",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf s3, x4",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtsi2sd xmm0, xmm1, eax": {
@@ -3621,11 +3621,11 @@
         "Map 1 0b11 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf d5, w4",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf d3, w4",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtsi2sd xmm0, xmm1, rax": {
@@ -3635,11 +3635,11 @@
         "Map 1 0b11 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf d5, x4",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf d3, x4",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovntps [rax], xmm0": {
@@ -3649,8 +3649,8 @@
         "Map 1 0b00 0x2B 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovntps [rax], ymm0": {
@@ -3660,8 +3660,8 @@
         "Map 1 0b00 0x2B 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vmovntpd [rax], xmm0": {
@@ -3671,8 +3671,8 @@
         "Map 1 0b01 0x2B 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovntpd [rax], ymm0": {
@@ -3682,8 +3682,8 @@
         "Map 1 0b01 0x2B 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vcvttss2si eax, xmm0": {
@@ -3693,8 +3693,8 @@
         "Map 1 0b10 0x2c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "fcvtzs w4, s4"
+        "mov z2.d, p7/m, z16.d",
+        "fcvtzs w4, s2"
       ]
     },
     "vcvttss2si rax, xmm0": {
@@ -3704,8 +3704,8 @@
         "Map 1 0b10 0x2c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "fcvtzs x4, s4"
+        "mov z2.d, p7/m, z16.d",
+        "fcvtzs x4, s2"
       ]
     },
     "vcvttsd2si eax, xmm0": {
@@ -3715,8 +3715,8 @@
         "Map 1 0b11 0x2c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "fcvtzs w4, d4"
+        "mov z2.d, p7/m, z16.d",
+        "fcvtzs w4, d2"
       ]
     },
     "vcvttsd2si rax, xmm0": {
@@ -3726,8 +3726,8 @@
         "Map 1 0b11 0x2c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "fcvtzs x4, d4"
+        "mov z2.d, p7/m, z16.d",
+        "fcvtzs x4, d2"
       ]
     },
     "vcvtss2si eax, xmm0": {
@@ -3737,8 +3737,8 @@
         "Map 1 0b10 0x2d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "frinti s0, s4",
+        "mov z2.d, p7/m, z16.d",
+        "frinti s0, s2",
         "fcvtzs w4, s0"
       ]
     },
@@ -3749,8 +3749,8 @@
         "Map 1 0b10 0x2d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "frinti s0, s4",
+        "mov z2.d, p7/m, z16.d",
+        "frinti s0, s2",
         "fcvtzs x4, s0"
       ]
     },
@@ -3761,8 +3761,8 @@
         "Map 1 0b11 0x2d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "frinti d0, d4",
+        "mov z2.d, p7/m, z16.d",
+        "frinti d0, d2",
         "fcvtzs x4, d0"
       ]
     },
@@ -3773,8 +3773,8 @@
         "Map 1 0b11 0x2d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "frinti d0, d4",
+        "mov z2.d, p7/m, z16.d",
+        "frinti d0, d2",
         "fcvtzs x4, d0"
       ]
     },
@@ -3785,9 +3785,9 @@
         "Map 1 0b00 0x2e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "fcmp s4, s5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "fcmp s2, s3",
         "cset x20, eq",
         "csinc x20, x20, xzr, vc",
         "cset x1, lt",
@@ -3815,9 +3815,9 @@
         "Map 1 0b01 0x2e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "fcmp d4, d5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "fcmp d2, d3",
         "cset x20, eq",
         "csinc x20, x20, xzr, vc",
         "cset x1, lt",
@@ -3848,9 +3848,9 @@
         "Map 1 0b00 0x2f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "fcmp s4, s5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "fcmp s2, s3",
         "cset x20, eq",
         "csinc x20, x20, xzr, vc",
         "cset x1, lt",
@@ -3881,9 +3881,9 @@
         "Map 1 0b01 0x2f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "fcmp d4, d5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "fcmp d2, d3",
         "cset x20, eq",
         "csinc x20, x20, xzr, vc",
         "cset x1, lt",
@@ -3914,11 +3914,11 @@
         "Map 1 0b00 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddps ymm0, ymm1, ymm2": {
@@ -3928,10 +3928,10 @@
         "Map 1 0b00 0x58 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddpd xmm0, xmm1, xmm2": {
@@ -3941,11 +3941,11 @@
         "Map 1 0b01 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddpd ymm0, ymm1, ymm2": {
@@ -3955,10 +3955,10 @@
         "Map 1 0b01 0x58 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddss xmm0, xmm1, xmm2": {
@@ -3968,12 +3968,12 @@
         "Map 1 0b10 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd s5, s4, s5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd s3, s2, s3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsd xmm0, xmm1, xmm2": {
@@ -3983,12 +3983,12 @@
         "Map 1 0b11 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fadd d5, d4, d5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fadd d3, d2, d3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulps xmm0, xmm1, xmm2": {
@@ -3998,11 +3998,11 @@
         "Map 1 0b00 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulps ymm0, ymm1, ymm2": {
@@ -4012,10 +4012,10 @@
         "Map 1 0b00 0x59 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulpd xmm0, xmm1, xmm2": {
@@ -4025,11 +4025,11 @@
         "Map 1 0b01 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulpd ymm0, ymm1, ymm2": {
@@ -4039,10 +4039,10 @@
         "Map 1 0b01 0x59 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulss xmm0, xmm1, xmm2": {
@@ -4052,12 +4052,12 @@
         "Map 1 0b10 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul s5, s4, s5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul s3, s2, s3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmulsd xmm0, xmm1, xmm2": {
@@ -4067,12 +4067,12 @@
         "Map 1 0b11 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fmul d5, d4, d5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fmul d3, d2, d3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtps2pd xmm0, xmm1": {
@@ -4082,10 +4082,10 @@
         "Map 1 0b00 0x5a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtpd2ps xmm0, xmm1": {
@@ -4095,10 +4095,10 @@
         "Map 1 0b01 0x5a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtn v4.2s, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtn v2.2s, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtss2sd xmm0, xmm1, xmm2": {
@@ -4108,12 +4108,12 @@
         "Map 1 0b10 0x5a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcvt d5, s5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcvt d3, s3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtsd2ss xmm0, xmm1, xmm2": {
@@ -4123,12 +4123,12 @@
         "Map 1 0b11 0x5a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcvt s5, d5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcvt s3, d3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtdq2ps xmm0, xmm1": {
@@ -4138,10 +4138,10 @@
         "Map 1 0b00 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtdq2ps ymm0, ymm1": {
@@ -4151,9 +4151,9 @@
         "Map 1 0b00 0x5b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "scvtf z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "scvtf z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtps2dq xmm0, xmm1": {
@@ -4163,11 +4163,11 @@
         "Map 1 0b01 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti v4.4s, v4.4s",
-        "fcvtzs v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti v2.4s, v2.4s",
+        "fcvtzs v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtps2dq ymm0, ymm1": {
@@ -4177,10 +4177,10 @@
         "Map 1 0b01 0x5b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti z4.s, p7/m, z4.s",
-        "fcvtzs z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti z2.s, p7/m, z2.s",
+        "fcvtzs z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvttps2dq xmm0, xmm1": {
@@ -4190,10 +4190,10 @@
         "Map 1 0b10 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtzs v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtzs v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvttps2dq ymm0, ymm1": {
@@ -4203,9 +4203,9 @@
         "Map 1 0b10 0x5b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtzs z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtzs z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubps xmm0, xmm1, xmm2": {
@@ -4215,11 +4215,11 @@
         "Map 1 0b00 0x5c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubps ymm0, ymm1, ymm2": {
@@ -4229,10 +4229,10 @@
         "Map 1 0b00 0x5c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubpd xmm0, xmm1, xmm2": {
@@ -4242,11 +4242,11 @@
         "Map 1 0b01 0x5c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubpd ymm0, ymm1, ymm2": {
@@ -4256,10 +4256,10 @@
         "Map 1 0b01 0x5c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubss xmm0, xmm1, xmm2": {
@@ -4269,12 +4269,12 @@
         "Map 1 0b10 0x5c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub s5, s4, s5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub s3, s2, s3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vsubsd xmm0, xmm1, xmm2": {
@@ -4284,12 +4284,12 @@
         "Map 1 0b11 0x5c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fsub d5, d4, d5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fsub d3, d2, d3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminps xmm0, xmm1, xmm2": {
@@ -4299,12 +4299,12 @@
         "Map 1 0b00 0x5d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v0.4s, v5.4s, v4.4s",
-        "bif v4.16b, v5.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v0.4s, v3.4s, v2.4s",
+        "bif v2.16b, v3.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminps ymm0, ymm1, ymm2": {
@@ -4314,12 +4314,12 @@
         "Map 1 0b00 0x5d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.s, p7/z, z5.s, z4.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.s, p7/z, z3.s, z2.s",
         "not p0.b, p7/z, p0.b",
-        "mov z4.s, p0/m, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminpd xmm0, xmm1, xmm2": {
@@ -4329,12 +4329,12 @@
         "Map 1 0b01 0x5d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v0.2d, v5.2d, v4.2d",
-        "bif v4.16b, v5.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v0.2d, v3.2d, v2.2d",
+        "bif v2.16b, v3.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminpd ymm0, ymm1, ymm2": {
@@ -4344,12 +4344,12 @@
         "Map 1 0b01 0x5d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.d, p7/z, z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.d, p7/z, z3.d, z2.d",
         "not p0.b, p7/z, p0.b",
-        "mov z4.d, p0/m, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminss xmm0, xmm1, xmm2": {
@@ -4359,13 +4359,13 @@
         "Map 1 0b10 0x5d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmp s4, s5",
-        "fcsel s5, s4, s5, mi",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmp s2, s3",
+        "fcsel s3, s2, s3, mi",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vminsd xmm0, xmm1, xmm2": {
@@ -4375,13 +4375,13 @@
         "Map 1 0b11 0x5d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmp d4, d5",
-        "fcsel d5, d4, d5, mi",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmp d2, d3",
+        "fcsel d3, d2, d3, mi",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivps xmm0, xmm1, xmm2": {
@@ -4391,11 +4391,11 @@
         "Map 1 0b00 0x5e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivps ymm0, ymm1, ymm2": {
@@ -4405,10 +4405,10 @@
         "Map 1 0b00 0x5e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv z4.s, p7/m, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv z2.s, p7/m, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivpd xmm0, xmm1, xmm2": {
@@ -4418,11 +4418,11 @@
         "Map 1 0b01 0x5e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivpd ymm0, ymm1, ymm2": {
@@ -4432,10 +4432,10 @@
         "Map 1 0b01 0x5e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv z4.d, p7/m, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv z2.d, p7/m, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivss xmm0, xmm1, xmm2": {
@@ -4445,12 +4445,12 @@
         "Map 1 0b10 0x5e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv s5, s4, s5",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv s3, s2, s3",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdivsd xmm0, xmm1, xmm2": {
@@ -4460,12 +4460,12 @@
         "Map 1 0b11 0x5e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fdiv d5, d4, d5",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fdiv d3, d2, d3",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxps xmm0, xmm1, xmm2": {
@@ -4475,12 +4475,12 @@
         "Map 1 0b00 0x5f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v0.4s, v5.4s, v4.4s",
-        "bit v4.16b, v5.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v0.4s, v3.4s, v2.4s",
+        "bit v2.16b, v3.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxps ymm0, ymm1, ymm2": {
@@ -4490,11 +4490,11 @@
         "Map 1 0b00 0x5f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.s, p7/z, z5.s, z4.s",
-        "mov z4.s, p0/m, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.s, p7/z, z3.s, z2.s",
+        "mov z2.s, p0/m, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxpd xmm0, xmm1, xmm2": {
@@ -4504,12 +4504,12 @@
         "Map 1 0b01 0x5f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt v0.2d, v5.2d, v4.2d",
-        "bit v4.16b, v5.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt v0.2d, v3.2d, v2.2d",
+        "bit v2.16b, v3.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxpd ymm0, ymm1, ymm2": {
@@ -4519,11 +4519,11 @@
         "Map 1 0b01 0x5f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmgt p0.d, p7/z, z5.d, z4.d",
-        "mov z4.d, p0/m, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmgt p0.d, p7/z, z3.d, z2.d",
+        "mov z2.d, p0/m, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxss xmm0, xmm1, xmm2": {
@@ -4533,13 +4533,13 @@
         "Map 1 0b10 0x5f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmp s4, s5",
-        "fcsel s5, s5, s4, mi",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmp s2, s3",
+        "fcsel s3, s3, s2, mi",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaxsd xmm0, xmm1, xmm2": {
@@ -4549,13 +4549,13 @@
         "Map 1 0b11 0x5f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "fcmp d4, d5",
-        "fcsel d5, d5, d4, mi",
-        "mov v4.d[0], v5.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "fcmp d2, d3",
+        "fcsel d3, d3, d2, mi",
+        "mov v2.d[0], v3.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhbw xmm0, xmm1, xmm2": {
@@ -4565,11 +4565,11 @@
         "Map 1 0b01 0x68 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip2 v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip2 v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhbw ymm0, ymm1, ymm2": {
@@ -4579,13 +4579,13 @@
         "Map 1 0b01 0x68 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.b, z4.b, z5.b",
-        "zip2 z4.b, z4.b, z5.b",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.b, z2.b, z3.b",
+        "zip2 z2.b, z2.b, z3.b",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhwd xmm0, xmm1, xmm2": {
@@ -4595,11 +4595,11 @@
         "Map 1 0b01 0x69 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip2 v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip2 v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhwd ymm0, ymm1, ymm2": {
@@ -4609,13 +4609,13 @@
         "Map 1 0b01 0x69 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.h, z4.h, z5.h",
-        "zip2 z4.h, z4.h, z5.h",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.h, z2.h, z3.h",
+        "zip2 z2.h, z2.h, z3.h",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhdq xmm0, xmm1, xmm2": {
@@ -4625,11 +4625,11 @@
         "Map 1 0b01 0x6a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip2 v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip2 v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhdq ymm0, ymm1, ymm2": {
@@ -4639,13 +4639,13 @@
         "Map 1 0b01 0x6a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.s, z4.s, z5.s",
-        "zip2 z4.s, z4.s, z5.s",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.s, z2.s, z3.s",
+        "zip2 z2.s, z2.s, z3.s",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackssdw xmm0, xmm1, xmm2": {
@@ -4655,12 +4655,12 @@
         "Map 1 0b01 0x6b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtn v4.4h, v4.4s",
-        "sqxtn2 v4.8h, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtn v2.4h, v2.4s",
+        "sqxtn2 v2.8h, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackssdw ymm0, ymm1, ymm2": {
@@ -4670,24 +4670,24 @@
         "Map 1 0b01 0x6b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtnb z1.h, z5.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtnb z1.h, z3.s",
         "uzp1 z1.h, z1.h, z1.h",
-        "sqxtnb z4.h, z4.s",
-        "uzp1 z4.h, z4.h, z4.h",
-        "splice z4.h, p6, z4.h, z1.h",
-        "mov z1.d, z4.d[1]",
-        "mov z5.d, z4.d",
+        "sqxtnb z2.h, z2.s",
+        "uzp1 z2.h, z2.h, z2.h",
+        "splice z2.h, p6, z2.h, z1.h",
+        "mov z1.d, z2.d[1]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklqdq xmm0, xmm1, xmm2": {
@@ -4697,11 +4697,11 @@
         "Map 1 0b01 0x6c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpcklqdq ymm0, ymm1, ymm2": {
@@ -4711,15 +4711,15 @@
         "Map 1 0b01 0x6c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.d, z4.d, z5.d",
-        "zip2 z4.d, z4.d, z5.d",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.d, z2.d, z3.d",
+        "zip2 z2.d, z2.d, z3.d",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhqdq xmm0, xmm1, xmm2": {
@@ -4729,11 +4729,11 @@
         "Map 1 0b01 0x6d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip2 v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip2 v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpunpckhqdq ymm0, ymm1, ymm2": {
@@ -4743,13 +4743,13 @@
         "Map 1 0b01 0x6d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "zip1 z6.d, z4.d, z5.d",
-        "zip2 z4.d, z4.d, z5.d",
-        "mov z1.q, z6.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "zip1 z4.d, z2.d, z3.d",
+        "zip2 z2.d, z2.d, z3.d",
+        "mov z1.q, z4.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovd xmm0, dword [rax]": {
@@ -4759,8 +4759,8 @@
         "Map 1 0b01 0x6e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr s4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr s2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovq xmm0, qword [rax]": {
@@ -4770,8 +4770,8 @@
         "Map 1 0b01 0x6e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr d2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovdqa xmm0, [rax]": {
@@ -4781,8 +4781,8 @@
         "Map 1 0b01 0x6f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovdqa [rax], xmm0": {
@@ -4792,8 +4792,8 @@
         "Map 1 0b01 0x6f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovdqu xmm0, [rax]": {
@@ -4803,8 +4803,8 @@
         "Map 1 0b10 0x6f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovdqu [rax], xmm0": {
@@ -4814,8 +4814,8 @@
         "Map 1 0b10 0x6f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vhaddpd xmm0, xmm1, xmm2": {
@@ -4825,11 +4825,11 @@
         "Map 1 0b01 0x7c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "faddp v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "faddp v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhaddpd ymm0, ymm1, ymm2": {
@@ -4839,24 +4839,24 @@
         "Map 1 0b01 0x7c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "faddp z0.d, p7/m, z0.d, z5.d",
-        "uzp1 z4.d, z0.d, z0.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movprfx z0, z2",
+        "faddp z0.d, p7/m, z0.d, z3.d",
+        "uzp1 z2.d, z0.d, z0.d",
         "uzp2 z1.d, z0.d, z0.d",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhaddps xmm0, xmm1, xmm2": {
@@ -4866,11 +4866,11 @@
         "Map 1 0b11 0x7c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "faddp v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "faddp v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhaddps ymm0, ymm1, ymm2": {
@@ -4880,24 +4880,24 @@
         "Map 1 0b11 0x7c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "faddp z0.s, p7/m, z0.s, z5.s",
-        "uzp1 z4.s, z0.s, z0.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movprfx z0, z2",
+        "faddp z0.s, p7/m, z0.s, z3.s",
+        "uzp1 z2.s, z0.s, z0.s",
         "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhsubpd xmm0, xmm1, xmm2": {
@@ -4907,13 +4907,13 @@
         "Map 1 0b01 0x7d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.2d, v4.2d, v5.2d",
-        "uzp2 v4.2d, v4.2d, v5.2d",
-        "fsub v4.2d, v6.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.2d, v2.2d, v3.2d",
+        "uzp2 v2.2d, v2.2d, v3.2d",
+        "fsub v2.2d, v4.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhsubpd ymm0, ymm1, ymm2": {
@@ -4923,22 +4923,22 @@
         "Map 1 0b01 0x7d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.d, z4.d, z5.d",
-        "uzp2 z4.d, z4.d, z5.d",
-        "fsub z4.d, z6.d, z4.d",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.d, z2.d, z3.d",
+        "uzp2 z2.d, z2.d, z3.d",
+        "fsub z2.d, z4.d, z2.d",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhsubps xmm0, xmm1, xmm2": {
@@ -4948,13 +4948,13 @@
         "Map 1 0b11 0x7d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.4s, v4.4s, v5.4s",
-        "uzp2 v4.4s, v4.4s, v5.4s",
-        "fsub v4.4s, v6.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.4s, v2.4s, v3.4s",
+        "uzp2 v2.4s, v2.4s, v3.4s",
+        "fsub v2.4s, v4.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vhsubps ymm0, ymm1, ymm2": {
@@ -4964,22 +4964,22 @@
         "Map 1 0b11 0x7d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.s, z4.s, z5.s",
-        "uzp2 z4.s, z4.s, z5.s",
-        "fsub z4.s, z6.s, z4.s",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.s, z2.s, z3.s",
+        "uzp2 z2.s, z2.s, z3.s",
+        "fsub z2.s, z4.s, z2.s",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovd dword [rax], xmm0": {
@@ -4989,11 +4989,11 @@
         "Map 1 0b01 0x7e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
+        "mov z2.d, p7/m, z16.d",
         "movi v0.2d, #0x0",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "str s4, [x4]"
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "str s2, [x4]"
       ]
     },
     "vmovq qword [rax], xmm0": {
@@ -5003,8 +5003,8 @@
         "Map 1 0b01 0x7e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str d2, [x4]"
       ]
     },
     "vmovdqa ymm0, [rax]": {
@@ -5014,8 +5014,8 @@
         "Map 1 0b01 0x7f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovdqa [rax], ymm0": {
@@ -5025,8 +5025,8 @@
         "Map 1 0b01 0x7f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vmovdqu ymm0, [rax]": {
@@ -5036,8 +5036,8 @@
         "Map 1 0b10 0x7f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovdqu [rax], ymm0": {
@@ -5047,8 +5047,8 @@
         "Map 1 0b10 0x7f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vaddsubpd xmm0, xmm1, xmm2": {
@@ -5058,14 +5058,14 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "ldr x0, [x28, #1584]",
-        "ldr q6, [x0]",
-        "eor v5.16b, v5.16b, v6.16b",
-        "fadd v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q4, [x0]",
+        "eor v3.16b, v3.16b, v4.16b",
+        "fadd v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubpd ymm0, ymm1, ymm2": {
@@ -5075,13 +5075,13 @@
         "Map 1 0b01 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "ldr x0, [x28, #1584]",
-        "ld1b {z6.b}, p7/z, [x0]",
-        "eor z5.d, z5.d, z6.d",
-        "fadd z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z4.b}, p7/z, [x0]",
+        "eor z3.d, z3.d, z4.d",
+        "fadd z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubps xmm0, xmm1, xmm2": {
@@ -5091,14 +5091,14 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "ldr x0, [x28, #1568]",
-        "ldr q6, [x0]",
-        "eor v5.16b, v5.16b, v6.16b",
-        "fadd v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q4, [x0]",
+        "eor v3.16b, v3.16b, v4.16b",
+        "fadd v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubps ymm0, ymm1, ymm2": {
@@ -5108,13 +5108,13 @@
         "Map 1 0b11 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "ldr x0, [x28, #1568]",
-        "ld1b {z6.b}, p7/z, [x0]",
-        "eor z5.d, z5.d, z6.d",
-        "fadd z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z4.b}, p7/z, [x0]",
+        "eor z3.d, z3.d, z4.d",
+        "fadd z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw xmm0, xmm1, xmm2": {
@@ -5124,12 +5124,12 @@
         "Map 1 0b01 0xd1 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.h, p6/m, z4.h, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.h, p6/m, z2.h, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw ymm0, ymm1, xmm2": {
@@ -5139,11 +5139,11 @@
         "Map 1 0b01 0xd1 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.h, p7/m, z4.h, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.h, p7/m, z2.h, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld xmm0, xmm1, xmm2": {
@@ -5153,12 +5153,12 @@
         "Map 1 0b01 0xd2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.s, p6/m, z4.s, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.s, p6/m, z2.s, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld ymm0, ymm1, xmm2": {
@@ -5168,11 +5168,11 @@
         "Map 1 0b01 0xd2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.s, p7/m, z4.s, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.s, p7/m, z2.s, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq xmm0, xmm1, xmm2": {
@@ -5182,12 +5182,12 @@
         "Map 1 0b01 0xd3 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.d, p6/m, z4.d, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.d, p6/m, z2.d, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq ymm0, ymm1, xmm2": {
@@ -5197,11 +5197,11 @@
         "Map 1 0b01 0xd3 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsr z4.d, p7/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsr z2.d, p7/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddq xmm0, xmm1, xmm2": {
@@ -5211,11 +5211,11 @@
         "Map 1 0b01 0xd4 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddq ymm0, ymm1, ymm2": {
@@ -5225,10 +5225,10 @@
         "Map 1 0b01 0xd4 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmullw xmm0, xmm1, xmm2": {
@@ -5238,11 +5238,11 @@
         "Map 1 0b01 0xd5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mul v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mul v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmullw ymm0, ymm1, ymm2": {
@@ -5252,10 +5252,10 @@
         "Map 1 0b01 0xd4 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mul z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mul z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovq [rax], xmm0": {
@@ -5265,8 +5265,8 @@
         "Map 1 0b01 0xd6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str d4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str d2, [x4]"
       ]
     },
     "vpmovmskb rax, xmm0": {
@@ -5276,18 +5276,18 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
+        "mov z2.d, p7/m, z16.d",
         "mov x20, #0x201",
         "movk x20, #0x804, lsl #16",
         "movk x20, #0x2010, lsl #32",
         "movk x20, #0x8040, lsl #48",
-        "dup v5.2d, x20",
-        "cmlt v4.16b, v4.16b, #0",
-        "and v4.16b, v4.16b, v5.16b",
-        "addp v4.16b, v4.16b, v4.16b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "umov w4, v4.h[0]"
+        "dup v3.2d, x20",
+        "cmlt v2.16b, v2.16b, #0",
+        "and v2.16b, v2.16b, v3.16b",
+        "addp v2.16b, v2.16b, v2.16b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "umov w4, v2.h[0]"
       ]
     },
     "vpmovmskb rax, ymm0": {
@@ -5297,26 +5297,26 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
+        "mov z2.d, p7/m, z16.d",
         "mov x20, #0x201",
         "movk x20, #0x804, lsl #16",
         "movk x20, #0x2010, lsl #32",
         "movk x20, #0x8040, lsl #48",
-        "mov z5.d, x20",
+        "mov z3.d, x20",
         "mov z0.d, #0",
-        "cmplt p0.b, p7/z, z4.b, #0",
-        "not z0.b, p0/m, z4.b",
-        "orr z0.b, p0/m, z0.b, z4.b",
-        "mov z4.d, z0.d",
-        "and z4.d, z4.d, z5.d",
-        "movprfx z0, z4",
-        "addp z0.b, p7/m, z0.b, z4.b",
-        "uzp1 z4.b, z0.b, z0.b",
+        "cmplt p0.b, p7/z, z2.b, #0",
+        "not z0.b, p0/m, z2.b",
+        "orr z0.b, p0/m, z0.b, z2.b",
+        "mov z2.d, z0.d",
+        "and z2.d, z2.d, z3.d",
+        "movprfx z0, z2",
+        "addp z0.b, p7/m, z0.b, z2.b",
+        "uzp1 z2.b, z0.b, z0.b",
         "uzp2 z1.b, z0.b, z0.b",
-        "splice z4.d, p6, z4.d, z1.d",
-        "addp v4.16b, v4.16b, v4.16b",
-        "addp v4.8b, v4.8b, v4.8b",
-        "mov w4, v4.s[0]"
+        "splice z2.d, p6, z2.d, z1.d",
+        "addp v2.16b, v2.16b, v2.16b",
+        "addp v2.8b, v2.8b, v2.8b",
+        "mov w4, v2.s[0]"
       ]
     },
     "vpsubusb xmm0, xmm1, xmm2": {
@@ -5326,11 +5326,11 @@
         "Map 1 0b01 0xd8 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqsub v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqsub v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubusb ymm0, ymm1, ymm2": {
@@ -5340,10 +5340,10 @@
         "Map 1 0b01 0xd8 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqsub z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqsub z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubusw xmm0, xmm1, xmm2": {
@@ -5353,11 +5353,11 @@
         "Map 1 0b01 0xd9 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqsub v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqsub v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubusw ymm0, ymm1, ymm2": {
@@ -5367,10 +5367,10 @@
         "Map 1 0b01 0xd9 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqsub z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqsub z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminub xmm0, xmm1, xmm2": {
@@ -5380,11 +5380,11 @@
         "Map 1 0b01 0xda 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminub ymm0, ymm1, ymm2": {
@@ -5394,10 +5394,10 @@
         "Map 1 0b01 0xda 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin z4.b, p7/m, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin z2.b, p7/m, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpand xmm0, xmm1, xmm2": {
@@ -5407,11 +5407,11 @@
         "Map 1 0b01 0xdb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "and v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "and v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpand ymm0, ymm1, ymm2": {
@@ -5421,10 +5421,10 @@
         "Map 1 0b01 0xdb 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "and z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "and z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddusb xmm0, xmm1, xmm2": {
@@ -5434,11 +5434,11 @@
         "Map 1 0b01 0xdc 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqadd v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqadd v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddusb ymm0, ymm1, ymm2": {
@@ -5448,10 +5448,10 @@
         "Map 1 0b01 0xdc 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqadd z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqadd z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddusw xmm0, xmm1, xmm2": {
@@ -5461,11 +5461,11 @@
         "Map 1 0b01 0xdd 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqadd v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqadd v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddusw ymm0, ymm1, ymm2": {
@@ -5475,10 +5475,10 @@
         "Map 1 0b01 0xdd 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uqadd z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uqadd z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxub xmm0, xmm1, xmm2": {
@@ -5488,11 +5488,11 @@
         "Map 1 0b01 0xdd 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxub ymm0, ymm1, ymm2": {
@@ -5502,10 +5502,10 @@
         "Map 1 0b01 0xde 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax z4.b, p7/m, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax z2.b, p7/m, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpandn xmm0, xmm1, xmm2": {
@@ -5515,11 +5515,11 @@
         "Map 1 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "bic v4.16b, v5.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "bic v2.16b, v3.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpandn ymm0, ymm1, ymm2": {
@@ -5529,10 +5529,10 @@
         "Map 1 0b01 0xdf 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "bic z4.d, z5.d, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "bic z2.d, z3.d, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpavgb xmm0, xmm1, xmm2": {
@@ -5542,11 +5542,11 @@
         "Map 1 0b01 0xe0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "urhadd v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "urhadd v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpavgb ymm0, ymm1, ymm2": {
@@ -5556,10 +5556,10 @@
         "Map 1 0b01 0xe0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "urhadd z4.b, p7/m, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "urhadd z2.b, p7/m, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw xmm0, xmm1, xmm2": {
@@ -5569,12 +5569,12 @@
         "Map 1 0b01 0xe1 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "asr z4.h, p6/m, z4.h, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "asr z2.h, p6/m, z2.h, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw ymm0, ymm1, xmm2": {
@@ -5584,11 +5584,11 @@
         "Map 1 0b01 0xe1 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "asr z4.h, p7/m, z4.h, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "asr z2.h, p7/m, z2.h, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad xmm0, xmm1, xmm2": {
@@ -5598,12 +5598,12 @@
         "Map 1 0b01 0xe2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "asr z4.s, p6/m, z4.s, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "asr z2.s, p6/m, z2.s, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad ymm0, ymm1, xmm2": {
@@ -5613,11 +5613,11 @@
         "Map 1 0b01 0xe2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "asr z4.s, p7/m, z4.s, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "asr z2.s, p7/m, z2.s, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpavgw xmm0, xmm1, xmm2": {
@@ -5627,11 +5627,11 @@
         "Map 1 0b01 0xe3 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "urhadd v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "urhadd v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpavgw ymm0, ymm1, ymm2": {
@@ -5641,10 +5641,10 @@
         "Map 1 0b01 0xe3 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "urhadd z4.h, p7/m, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "urhadd z2.h, p7/m, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhuw xmm0, xmm1, xmm2": {
@@ -5654,11 +5654,11 @@
         "Map 1 0b01 0xe4 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umulh z4.h, p6/m, z4.h, z5.h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umulh z2.h, p6/m, z2.h, z3.h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhuw ymm0, ymm1, ymm2": {
@@ -5668,10 +5668,10 @@
         "Map 1 0b01 0xe4 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umulh z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umulh z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhw xmm0, xmm1, xmm2": {
@@ -5681,11 +5681,11 @@
         "Map 1 0b01 0xe5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smulh z4.h, p6/m, z4.h, z5.h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smulh z2.h, p6/m, z2.h, z3.h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhw ymm0, ymm1, ymm2": {
@@ -5695,10 +5695,10 @@
         "Map 1 0b01 0xe5 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smulh z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smulh z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvttpd2dq xmm0, xmm1": {
@@ -5708,12 +5708,12 @@
         "Map 1 0b01 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtn v4.2s, v4.2d",
-        "fcvtzs v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtn v2.2s, v2.2d",
+        "fcvtzs v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvttpd2dq xmm0, ymm1": {
@@ -5723,12 +5723,12 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtnt z4.s, p7/m, z4.d",
-        "uzp2 z4.s, z4.s, z4.s",
-        "fcvtzs z4.s, p7/m, z4.s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtnt z2.s, p7/m, z2.d",
+        "uzp2 z2.s, z2.s, z2.s",
+        "fcvtzs z2.s, p7/m, z2.s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtdq2pd xmm0, xmm1": {
@@ -5738,11 +5738,11 @@
         "Map 1 0b10 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.2d, v4.2s",
-        "scvtf v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.2d, v2.2s",
+        "scvtf v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtdq2pd ymm0, xmm1": {
@@ -5752,10 +5752,10 @@
         "Map 1 0b10 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.d, z4.s",
-        "scvtf z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.d, z2.s",
+        "scvtf z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtpd2dq xmm0, xmm1": {
@@ -5765,13 +5765,13 @@
         "Map 1 0b11 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtn v4.2s, v4.2d",
-        "frinti v4.4s, v4.4s",
-        "fcvtzs v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtn v2.2s, v2.2d",
+        "frinti v2.4s, v2.4s",
+        "fcvtzs v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtpd2dq xmm0, ymm1": {
@@ -5781,13 +5781,13 @@
         "Map 1 0b11 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "fcvtnt z4.s, p7/m, z4.d",
-        "uzp2 z4.s, z4.s, z4.s",
-        "frinti z4.s, p7/m, z4.s",
-        "fcvtzs z4.s, p7/m, z4.s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "fcvtnt z2.s, p7/m, z2.d",
+        "uzp2 z2.s, z2.s, z2.s",
+        "frinti z2.s, p7/m, z2.s",
+        "fcvtzs z2.s, p7/m, z2.s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovntdq [rax], xmm0": {
@@ -5797,8 +5797,8 @@
         "Map 1 0b01 0xe7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "str q4, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "str q2, [x4]"
       ]
     },
     "vmovntdq [rax], ymm0": {
@@ -5808,8 +5808,8 @@
         "Map 1 0b01 0xe7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "st1b {z4.b}, p7, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "st1b {z2.b}, p7, [x4]"
       ]
     },
     "vpsubsb xmm0, xmm1, xmm2": {
@@ -5819,11 +5819,11 @@
         "Map 1 0b01 0xe8 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqsub v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqsub v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubsb ymm0, ymm1, ymm2": {
@@ -5833,10 +5833,10 @@
         "Map 1 0b01 0xe8 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqsub z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqsub z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubsw xmm0, xmm1, xmm2": {
@@ -5846,11 +5846,11 @@
         "Map 1 0b01 0xe9 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqsub v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqsub v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubsw ymm0, ymm1, ymm2": {
@@ -5860,10 +5860,10 @@
         "Map 1 0b01 0xe9 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqsub z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqsub z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsw xmm0, xmm1, xmm2": {
@@ -5873,11 +5873,11 @@
         "Map 1 0b01 0xea 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsw ymm0, ymm1, ymm2": {
@@ -5887,10 +5887,10 @@
         "Map 1 0b01 0xea 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin z4.h, p7/m, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin z2.h, p7/m, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpor xmm0, xmm1, xmm2": {
@@ -5900,11 +5900,11 @@
         "Map 1 0b01 0xeb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "orr v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "orr v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpor ymm0, ymm1, ymm2": {
@@ -5914,10 +5914,10 @@
         "Map 1 0b01 0xeb 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "orr z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "orr z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddsb xmm0, xmm1, xmm2": {
@@ -5927,11 +5927,11 @@
         "Map 1 0b01 0xec 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqadd v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqadd v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddsb ymm0, ymm1, ymm2": {
@@ -5941,10 +5941,10 @@
         "Map 1 0b01 0xec 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqadd z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqadd z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddsw xmm0, xmm1, xmm2": {
@@ -5954,11 +5954,11 @@
         "Map 1 0b01 0xed 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqadd v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqadd v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddsw ymm0, ymm1, ymm2": {
@@ -5968,10 +5968,10 @@
         "Map 1 0b01 0xed 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqadd z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqadd z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsw xmm0, xmm1, xmm2": {
@@ -5981,11 +5981,11 @@
         "Map 1 0b01 0xee 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsw ymm0, ymm1, ymm2": {
@@ -5995,10 +5995,10 @@
         "Map 1 0b01 0xee 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax z4.h, p7/m, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax z2.h, p7/m, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpxor xmm0, xmm1, xmm2": {
@@ -6008,11 +6008,11 @@
         "Map 1 0b01 0xef 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpxor ymm0, ymm1, ymm2": {
@@ -6022,10 +6022,10 @@
         "Map 1 0b01 0xef 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "eor z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "eor z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vlddqu xmm0, [rax]": {
@@ -6035,8 +6035,8 @@
         "Map 1 0b11 0xf0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vlddqu ymm0, [rax]": {
@@ -6046,8 +6046,8 @@
         "Map 1 0b11 0xf0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw xmm0, xmm1, xmm2": {
@@ -6057,12 +6057,12 @@
         "Map 1 0b01 0xf1 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.h, p6/m, z4.h, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.h, p6/m, z2.h, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw ymm0, ymm1, xmm2": {
@@ -6072,11 +6072,11 @@
         "Map 1 0b01 0xf1 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.h, p7/m, z4.h, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.h, p7/m, z2.h, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld xmm0, xmm1, xmm2": {
@@ -6086,12 +6086,12 @@
         "Map 1 0b01 0xf2 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.s, p6/m, z4.s, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.s, p6/m, z2.s, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld ymm0, ymm1, xmm2": {
@@ -6101,11 +6101,11 @@
         "Map 1 0b01 0xf2 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.s, p7/m, z4.s, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.s, p7/m, z2.s, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq xmm0, xmm1, xmm2": {
@@ -6115,12 +6115,12 @@
         "Map 1 0b01 0xf3 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.d, p6/m, z4.d, z0.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.d, p6/m, z2.d, z0.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq ymm0, ymm1, xmm2": {
@@ -6130,11 +6130,11 @@
         "Map 1 0b01 0xf3 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z0.d, d5",
-        "lsl z4.d, p7/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z0.d, d3",
+        "lsl z2.d, p7/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmuludq xmm0, xmm1, xmm2": {
@@ -6144,13 +6144,13 @@
         "Map 1 0b01 0xf4 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v4.4s, v4.4s, v4.4s",
-        "uzp1 v5.4s, v5.4s, v5.4s",
-        "umull v4.2d, v4.2s, v5.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v2.4s, v2.4s, v2.4s",
+        "uzp1 v3.4s, v3.4s, v3.4s",
+        "umull v2.2d, v2.2s, v3.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmuludq ymm0, ymm1, ymm2": {
@@ -6160,14 +6160,14 @@
         "Map 1 0b01 0xf4 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z4.s, z4.s, z4.s",
-        "uzp1 z5.s, z5.s, z5.s",
-        "umullb z0.d, z4.s, z5.s",
-        "umullt z1.d, z4.s, z5.s",
-        "zip1 z4.d, z0.d, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z2.s, z2.s, z2.s",
+        "uzp1 z3.s, z3.s, z3.s",
+        "umullb z0.d, z2.s, z3.s",
+        "umullt z1.d, z2.s, z3.s",
+        "zip1 z2.d, z0.d, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaddwd xmm0, xmm1, xmm2": {
@@ -6177,13 +6177,13 @@
         "Map 1 0b01 0xf5 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smull v6.4s, v4.4h, v5.4h",
-        "smull2 v4.4s, v4.8h, v5.8h",
-        "addp v4.4s, v6.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smull v4.4s, v2.4h, v3.4h",
+        "smull2 v2.4s, v2.8h, v3.8h",
+        "addp v2.4s, v4.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaddwd ymm0, ymm1, ymm2": {
@@ -6193,20 +6193,20 @@
         "Map 1 0b01 0xf5 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smullb z0.s, z4.h, z5.h",
-        "smullt z1.s, z4.h, z5.h",
-        "zip1 z6.s, z0.s, z1.s",
-        "smullb z0.s, z4.h, z5.h",
-        "smullt z1.s, z4.h, z5.h",
-        "zip2 z4.s, z0.s, z1.s",
-        "movprfx z0, z6",
-        "addp z0.s, p7/m, z0.s, z4.s",
-        "uzp1 z4.s, z0.s, z0.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smullb z0.s, z2.h, z3.h",
+        "smullt z1.s, z2.h, z3.h",
+        "zip1 z4.s, z0.s, z1.s",
+        "smullb z0.s, z2.h, z3.h",
+        "smullt z1.s, z2.h, z3.h",
+        "zip2 z2.s, z0.s, z1.s",
+        "movprfx z0, z4",
+        "addp z0.s, p7/m, z0.s, z2.s",
+        "uzp1 z2.s, z0.s, z0.s",
         "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsadbw xmm0, xmm1, xmm2": {
@@ -6216,15 +6216,15 @@
         "Map 1 0b01 0xf6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uabdl v6.8h, v4.8b, v5.8b",
-        "uabdl2 v4.8h, v4.16b, v5.16b",
-        "addv h5, v6.8h",
-        "addv h4, v4.8h",
-        "zip1 v4.2d, v5.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uabdl v4.8h, v2.8b, v3.8b",
+        "uabdl2 v2.8h, v2.16b, v3.16b",
+        "addv h3, v4.8h",
+        "addv h2, v2.8h",
+        "zip1 v2.2d, v3.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsadbw ymm0, ymm1, ymm2": {
@@ -6234,41 +6234,41 @@
         "Map 1 0b01 0xf6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uabdlb z0.h, z4.b, z5.b",
-        "uabdlt z1.h, z4.b, z5.b",
-        "zip1 z6.h, z0.h, z1.h",
-        "uabdlb z0.h, z4.b, z5.b",
-        "uabdlt z1.h, z4.b, z5.b",
-        "zip2 z4.h, z0.h, z1.h",
-        "addv h5, v6.8h",
-        "addv h7, v4.8h",
-        "zip1 z5.d, z5.d, z7.d",
-        "mov z6.q, z6.q[1]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uabdlb z0.h, z2.b, z3.b",
+        "uabdlt z1.h, z2.b, z3.b",
+        "zip1 z4.h, z0.h, z1.h",
+        "uabdlb z0.h, z2.b, z3.b",
+        "uabdlt z1.h, z2.b, z3.b",
+        "zip2 z2.h, z0.h, z1.h",
+        "addv h3, v4.8h",
+        "addv h5, v2.8h",
+        "zip1 z3.d, z3.d, z5.d",
         "mov z4.q, z4.q[1]",
-        "addv h6, v6.8h",
+        "mov z2.q, z2.q[1]",
         "addv h4, v4.8h",
-        "mov z1.d, d4",
-        "mov z4.d, z6.d",
+        "addv h2, v2.8h",
+        "mov z1.d, d2",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z1.d, z4.d[1]",
-        "mov z5.d, z4.d",
+        "mov z2.b, p0/m, z1.b",
+        "mov z1.d, z2.d[1]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovdqu xmm0, xmm1": {
@@ -6278,12 +6278,12 @@
         "Map 1 0b01 0xf7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmlt v4.16b, v4.16b, #0",
-        "mov z5.d, p7/m, z16.d",
-        "ldr q6, [x11]",
-        "bsl v4.16b, v5.16b, v6.16b",
-        "str q4, [x11]"
+        "mov z2.d, p7/m, z17.d",
+        "cmlt v2.16b, v2.16b, #0",
+        "mov z3.d, p7/m, z16.d",
+        "ldr q4, [x11]",
+        "bsl v2.16b, v3.16b, v4.16b",
+        "str q2, [x11]"
       ]
     },
     "vpsubb xmm0, xmm1, xmm2": {
@@ -6293,11 +6293,11 @@
         "Map 1 0b01 0xf8 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubb ymm0, ymm1, ymm2": {
@@ -6307,10 +6307,10 @@
         "Map 1 0b01 0xf8 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubw xmm0, xmm1, xmm2": {
@@ -6320,11 +6320,11 @@
         "Map 1 0b01 0xf9 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubw ymm0, ymm1, ymm2": {
@@ -6334,10 +6334,10 @@
         "Map 1 0b01 0xf9 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubd xmm0, xmm1, xmm2": {
@@ -6347,11 +6347,11 @@
         "Map 1 0b01 0xfa 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubd ymm0, ymm1, ymm2": {
@@ -6361,10 +6361,10 @@
         "Map 1 0b01 0xfa 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubq xmm0, xmm1, xmm2": {
@@ -6374,11 +6374,11 @@
         "Map 1 0b01 0xfb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsubq ymm0, ymm1, ymm2": {
@@ -6388,10 +6388,10 @@
         "Map 1 0b01 0xfb 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sub z4.d, z4.d, z5.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sub z2.d, z2.d, z3.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddb xmm0, xmm1, xmm2": {
@@ -6401,11 +6401,11 @@
         "Map 1 0b01 0xfc 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddb ymm0, ymm1, ymm2": {
@@ -6415,10 +6415,10 @@
         "Map 1 0b01 0xfc 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddw xmm0, xmm1, xmm2": {
@@ -6428,11 +6428,11 @@
         "Map 1 0b01 0xfd 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddw ymm0, ymm1, ymm2": {
@@ -6442,10 +6442,10 @@
         "Map 1 0b01 0xfd 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddd xmm0, xmm1, xmm2": {
@@ -6455,11 +6455,11 @@
         "Map 1 0b01 0xfe 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpaddd ymm0, ymm1, ymm2": {
@@ -6469,10 +6469,10 @@
         "Map 1 0b01 0xfe 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "add z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "add z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json
index 5ba4d6d49..0bdfe7e34 100644
--- a/unittests/InstructionCountCI/VEX_map1_FCMA.json
+++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json
@@ -16,12 +16,12 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v5.16b, v5.16b, v5.16b, #8",
-        "fcadd v4.2d, v4.2d, v5.2d, #90",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v3.16b, v3.16b, v3.16b, #8",
+        "fcadd v2.2d, v2.2d, v3.2d, #90",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubpd ymm0, ymm1, ymm2": {
@@ -31,11 +31,11 @@
         "Map 1 0b01 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext z5.b, z5.b, z5.b, #8",
-        "fcadd z4.d, p7/m, z4.d, z5.d, #90",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext z3.b, z3.b, z3.b, #8",
+        "fcadd z2.d, p7/m, z2.d, z3.d, #90",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubps xmm0, xmm1, xmm2": {
@@ -45,12 +45,12 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "rev64 v5.4s, v5.4s",
-        "fcadd v4.4s, v4.4s, v5.4s, #90",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "rev64 v3.4s, v3.4s",
+        "fcadd v2.4s, v2.4s, v3.4s, #90",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaddsubps ymm0, ymm1, ymm2": {
@@ -60,11 +60,11 @@
         "Map 1 0b11 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "revw z5.d, p7/m, z5.d",
-        "fcadd z4.s, p7/m, z4.s, z5.s, #90",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "revw z3.d, p7/m, z3.d",
+        "fcadd z2.s, p7/m, z2.s, z3.s, #90",
+        "mov z16.d, p7/m, z2.d"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index e188ac332..f2e5e66f8 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -14,13 +14,13 @@
         "Map 2 0b01 0x00 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.16b, #0x8f",
-        "and v5.16b, v5.16b, v6.16b",
-        "tbl v4.16b, {v4.16b}, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.16b, #0x8f",
+        "and v3.16b, v3.16b, v4.16b",
+        "tbl v2.16b, {v2.16b}, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpshufb ymm0, ymm1, ymm2": {
@@ -30,19 +30,19 @@
         "Map 2 0b01 0x00 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.b, #-113",
-        "and z5.d, z5.d, z6.d",
-        "tbl v6.16b, {v4.16b}, v5.16b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "tbl v4.16b, {v4.16b}, v5.16b",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.b, #-113",
+        "and z3.d, z3.d, z4.d",
+        "tbl v4.16b, {v2.16b}, v3.16b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "tbl v2.16b, {v2.16b}, v3.16b",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddw xmm0, xmm1, xmm2": {
@@ -52,11 +52,11 @@
         "Map 2 0b01 0x01 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "addp v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "addp v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddw ymm0, ymm1, ymm2": {
@@ -66,24 +66,24 @@
         "Map 2 0b01 0x01 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "addp z0.h, p7/m, z0.h, z5.h",
-        "uzp1 z4.h, z0.h, z0.h",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movprfx z0, z2",
+        "addp z0.h, p7/m, z0.h, z3.h",
+        "uzp1 z2.h, z0.h, z0.h",
         "uzp2 z1.h, z0.h, z0.h",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddd xmm0, xmm1, xmm2": {
@@ -93,11 +93,11 @@
         "Map 2 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "addp v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "addp v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddd ymm0, ymm1, ymm2": {
@@ -107,24 +107,24 @@
         "Map 2 0b01 0x02 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "addp z0.s, p7/m, z0.s, z5.s",
-        "uzp1 z4.s, z0.s, z0.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movprfx z0, z2",
+        "addp z0.s, p7/m, z0.s, z3.s",
+        "uzp1 z2.s, z0.s, z0.s",
         "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddsw xmm0, xmm1, xmm2": {
@@ -134,13 +134,13 @@
         "Map 2 0b01 0x03 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.8h, v4.8h, v5.8h",
-        "uzp2 v4.8h, v4.8h, v5.8h",
-        "sqadd v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.8h, v2.8h, v3.8h",
+        "uzp2 v2.8h, v2.8h, v3.8h",
+        "sqadd v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphaddsw ymm0, ymm1, ymm2": {
@@ -150,22 +150,22 @@
         "Map 2 0b01 0x03 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.h, z4.h, z5.h",
-        "uzp2 z4.h, z4.h, z5.h",
-        "sqadd z4.h, z6.h, z4.h",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.h, z2.h, z3.h",
+        "uzp2 z2.h, z2.h, z3.h",
+        "sqadd z2.h, z4.h, z2.h",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaddubsw xmm0, xmm1, xmm2": {
@@ -175,19 +175,19 @@
         "Map 2 0b01 0x04 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uxtl v6.8h, v4.8b",
-        "sxtl v7.8h, v5.8b",
-        "mul v6.8h, v6.8h, v7.8h",
-        "uxtl2 v4.8h, v4.16b",
-        "sxtl2 v5.8h, v5.16b",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uxtl v4.8h, v2.8b",
+        "sxtl v5.8h, v3.8b",
         "mul v4.8h, v4.8h, v5.8h",
-        "uzp1 v5.8h, v6.8h, v4.8h",
-        "uzp2 v4.8h, v6.8h, v4.8h",
-        "sqadd v4.8h, v5.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "uxtl2 v2.8h, v2.16b",
+        "sxtl2 v3.8h, v3.16b",
+        "mul v2.8h, v2.8h, v3.8h",
+        "uzp1 v3.8h, v4.8h, v2.8h",
+        "uzp2 v2.8h, v4.8h, v2.8h",
+        "sqadd v2.8h, v3.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaddubsw ymm0, ymm1, ymm2": {
@@ -197,18 +197,18 @@
         "Map 2 0b01 0x04 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uunpklo z6.h, z4.b",
-        "sunpklo z7.h, z5.b",
-        "mul z6.h, z6.h, z7.h",
-        "uunpkhi z4.h, z4.b",
-        "sunpkhi z5.h, z5.b",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uunpklo z4.h, z2.b",
+        "sunpklo z5.h, z3.b",
         "mul z4.h, z4.h, z5.h",
-        "uzp1 z5.h, z6.h, z4.h",
-        "uzp2 z4.h, z6.h, z4.h",
-        "sqadd z4.h, z5.h, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "uunpkhi z2.h, z2.b",
+        "sunpkhi z3.h, z3.b",
+        "mul z2.h, z2.h, z3.h",
+        "uzp1 z3.h, z4.h, z2.h",
+        "uzp2 z2.h, z4.h, z2.h",
+        "sqadd z2.h, z3.h, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubw xmm0, xmm1, xmm2": {
@@ -218,13 +218,13 @@
         "Map 2 0b01 0x05 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.8h, v4.8h, v5.8h",
-        "uzp2 v4.8h, v4.8h, v5.8h",
-        "sub v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.8h, v2.8h, v3.8h",
+        "uzp2 v2.8h, v2.8h, v3.8h",
+        "sub v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubw ymm0, ymm1, ymm2": {
@@ -234,22 +234,22 @@
         "Map 2 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.h, z4.h, z5.h",
-        "uzp2 z4.h, z4.h, z5.h",
-        "sub z4.h, z6.h, z4.h",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.h, z2.h, z3.h",
+        "uzp2 z2.h, z2.h, z3.h",
+        "sub z2.h, z4.h, z2.h",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubd xmm0, xmm1, xmm2": {
@@ -259,13 +259,13 @@
         "Map 2 0b01 0x06 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.4s, v4.4s, v5.4s",
-        "uzp2 v4.4s, v4.4s, v5.4s",
-        "sub v4.4s, v6.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.4s, v2.4s, v3.4s",
+        "uzp2 v2.4s, v2.4s, v3.4s",
+        "sub v2.4s, v4.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubd ymm0, ymm1, ymm2": {
@@ -275,22 +275,22 @@
         "Map 2 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.s, z4.s, z5.s",
-        "uzp2 z4.s, z4.s, z5.s",
-        "sub z4.s, z6.s, z4.s",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.s, z2.s, z3.s",
+        "uzp2 z2.s, z2.s, z3.s",
+        "sub z2.s, z4.s, z2.s",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubsw xmm0, xmm1, xmm2": {
@@ -300,13 +300,13 @@
         "Map 2 0b01 0x07 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v6.8h, v4.8h, v5.8h",
-        "uzp2 v4.8h, v4.8h, v5.8h",
-        "sqsub v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v4.8h, v2.8h, v3.8h",
+        "uzp2 v2.8h, v2.8h, v3.8h",
+        "sqsub v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphsubsw ymm0, ymm1, ymm2": {
@@ -316,22 +316,22 @@
         "Map 2 0b01 0x07 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z6.h, z4.h, z5.h",
-        "uzp2 z4.h, z4.h, z5.h",
-        "sqsub z4.h, z6.h, z4.h",
-        "mov z1.d, z4.d[2]",
-        "mov z5.d, z4.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z4.h, z2.h, z3.h",
+        "uzp2 z2.h, z2.h, z3.h",
+        "sqsub z2.h, z4.h, z2.h",
+        "mov z1.d, z2.d[2]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignb xmm0, xmm1, xmm2": {
@@ -341,13 +341,13 @@
         "Map 2 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl v5.16b, v5.16b, #7",
-        "srshr v5.16b, v5.16b, #7",
-        "mul v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl v3.16b, v3.16b, #7",
+        "srshr v3.16b, v3.16b, #7",
+        "mul v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignb ymm0, ymm1, ymm2": {
@@ -357,12 +357,12 @@
         "Map 2 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl z5.b, p7/m, z5.b, #7",
-        "srshr z5.b, p7/m, z5.b, #7",
-        "mul z4.b, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl z3.b, p7/m, z3.b, #7",
+        "srshr z3.b, p7/m, z3.b, #7",
+        "mul z2.b, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignw xmm0, xmm1, xmm2": {
@@ -372,13 +372,13 @@
         "Map 2 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl v5.8h, v5.8h, #15",
-        "srshr v5.8h, v5.8h, #15",
-        "mul v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl v3.8h, v3.8h, #15",
+        "srshr v3.8h, v3.8h, #15",
+        "mul v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignw ymm0, ymm1, ymm2": {
@@ -388,12 +388,12 @@
         "Map 2 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl z5.h, p7/m, z5.h, #15",
-        "srshr z5.h, p7/m, z5.h, #15",
-        "mul z4.h, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl z3.h, p7/m, z3.h, #15",
+        "srshr z3.h, p7/m, z3.h, #15",
+        "mul z2.h, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignd xmm0, xmm1, xmm2": {
@@ -403,13 +403,13 @@
         "Map 2 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl v5.4s, v5.4s, #31",
-        "srshr v5.4s, v5.4s, #31",
-        "mul v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl v3.4s, v3.4s, #31",
+        "srshr v3.4s, v3.4s, #31",
+        "mul v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsignd ymm0, ymm1, ymm2": {
@@ -419,12 +419,12 @@
         "Map 2 0b01 0x0a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqshl z5.s, p7/m, z5.s, #31",
-        "srshr z5.s, p7/m, z5.s, #31",
-        "mul z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqshl z3.s, p7/m, z3.s, #31",
+        "srshr z3.s, p7/m, z3.s, #31",
+        "mul z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhrsw xmm0, xmm1, xmm2": {
@@ -434,21 +434,21 @@
         "Map 2 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smull v6.4s, v4.4h, v5.4h",
-        "smull2 v4.4s, v4.8h, v5.8h",
-        "sshr v5.4s, v6.4s, #14",
-        "sshr v4.4s, v4.4s, #14",
-        "movi v6.4s, #0x1, lsl #0",
-        "add v5.4s, v5.4s, v6.4s",
-        "add v4.4s, v4.4s, v6.4s",
-        "shrn v5.4h, v5.4s, #1",
-        "mov v0.16b, v5.16b",
-        "shrn2 v0.8h, v4.4s, #1",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smull v4.4s, v2.4h, v3.4h",
+        "smull2 v2.4s, v2.8h, v3.8h",
+        "sshr v3.4s, v4.4s, #14",
+        "sshr v2.4s, v2.4s, #14",
+        "movi v4.4s, #0x1, lsl #0",
+        "add v3.4s, v3.4s, v4.4s",
+        "add v2.4s, v2.4s, v4.4s",
+        "shrn v3.4h, v3.4s, #1",
+        "mov v0.16b, v3.16b",
+        "shrn2 v0.8h, v2.4s, #1",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulhrsw ymm0, ymm1, ymm2": {
@@ -458,27 +458,27 @@
         "Map 2 0b01 0x0b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smullb z0.s, z4.h, z5.h",
-        "smullt z1.s, z4.h, z5.h",
-        "zip1 z6.s, z0.s, z1.s",
-        "smullb z0.s, z4.h, z5.h",
-        "smullt z1.s, z4.h, z5.h",
-        "zip2 z4.s, z0.s, z1.s",
-        "movprfx z5, z6",
-        "asr z5.s, p7/m, z5.s, #14",
-        "asr z4.s, p7/m, z4.s, #14",
-        "mov z6.s, #1",
-        "add z5.s, z5.s, z6.s",
-        "add z4.s, z4.s, z6.s",
-        "shrnb z5.h, z5.s, #1",
-        "uzp1 z5.h, z5.h, z5.h",
-        "shrnb z1.h, z4.s, #1",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smullb z0.s, z2.h, z3.h",
+        "smullt z1.s, z2.h, z3.h",
+        "zip1 z4.s, z0.s, z1.s",
+        "smullb z0.s, z2.h, z3.h",
+        "smullt z1.s, z2.h, z3.h",
+        "zip2 z2.s, z0.s, z1.s",
+        "movprfx z3, z4",
+        "asr z3.s, p7/m, z3.s, #14",
+        "asr z2.s, p7/m, z2.s, #14",
+        "mov z4.s, #1",
+        "add z3.s, z3.s, z4.s",
+        "add z2.s, z2.s, z4.s",
+        "shrnb z3.h, z3.s, #1",
+        "uzp1 z3.h, z3.h, z3.h",
+        "shrnb z1.h, z2.s, #1",
         "uzp1 z1.h, z1.h, z1.h",
-        "movprfx z4, z5",
-        "splice z4.h, p6, z4.h, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "movprfx z2, z3",
+        "splice z2.h, p6, z2.h, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps xmm0, xmm1, xmm2": {
@@ -488,20 +488,20 @@
         "Map 2 0b01 0x0c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.4s, #0x3, lsl #0",
-        "and v5.16b, v5.16b, v6.16b",
-        "trn1 v5.16b, v5.16b, v5.16b",
-        "trn1 v5.8h, v5.8h, v5.8h",
-        "shl v5.16b, v5.16b, #2",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.4s, #0x3, lsl #0",
+        "and v3.16b, v3.16b, v4.16b",
+        "trn1 v3.16b, v3.16b, v3.16b",
+        "trn1 v3.8h, v3.8h, v3.8h",
+        "shl v3.16b, v3.16b, #2",
         "mov w20, #0x100",
         "movk w20, #0x302, lsl #16",
-        "dup v6.4s, w20",
-        "add v5.16b, v6.16b, v5.16b",
-        "tbl v4.16b, {v4.16b}, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "dup v4.4s, w20",
+        "add v3.16b, v4.16b, v3.16b",
+        "tbl v2.16b, {v2.16b}, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps ymm0, ymm1, ymm2": {
@@ -511,25 +511,25 @@
         "Map 2 0b01 0x0c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.s, #3",
-        "and z5.d, z5.d, z6.d",
-        "trn1 z5.b, z5.b, z5.b",
-        "trn1 z5.h, z5.h, z5.h",
-        "lsl z5.b, p7/m, z5.b, #2",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.s, #3",
+        "and z3.d, z3.d, z4.d",
+        "trn1 z3.b, z3.b, z3.b",
+        "trn1 z3.h, z3.h, z3.h",
+        "lsl z3.b, p7/m, z3.b, #2",
         "mov w20, #0x100",
         "movk w20, #0x302, lsl #16",
-        "mov z6.s, w20",
-        "movi v7.2d, #0x0",
-        "mov z8.b, #16",
-        "mov z1.q, q8",
+        "mov z4.s, w20",
+        "movi v5.2d, #0x0",
+        "mov z6.b, #16",
+        "mov z1.q, q6",
         "not p0.b, p7/z, p6.b",
-        "mov z7.b, p0/m, z1.b",
-        "add z6.b, z6.b, z7.b",
-        "add z5.b, z6.b, z5.b",
-        "tbl z4.b, {z4.b}, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z5.b, p0/m, z1.b",
+        "add z4.b, z4.b, z5.b",
+        "add z3.b, z4.b, z3.b",
+        "tbl z2.b, {z2.b}, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd xmm0, xmm1, xmm2": {
@@ -539,25 +539,25 @@
         "Map 2 0b01 0x0d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ushr v5.2d, v5.2d, #1",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ushr v3.2d, v3.2d, #1",
         "mov w0, #0x1",
-        "dup v6.2d, x0",
-        "and v5.16b, v5.16b, v6.16b",
-        "trn1 v5.16b, v5.16b, v5.16b",
-        "trn1 v5.8h, v5.8h, v5.8h",
-        "trn1 v5.4s, v5.4s, v5.4s",
-        "shl v5.16b, v5.16b, #3",
+        "dup v4.2d, x0",
+        "and v3.16b, v3.16b, v4.16b",
+        "trn1 v3.16b, v3.16b, v3.16b",
+        "trn1 v3.8h, v3.8h, v3.8h",
+        "trn1 v3.4s, v3.4s, v3.4s",
+        "shl v3.16b, v3.16b, #3",
         "mov x20, #0x100",
         "movk x20, #0x302, lsl #16",
         "movk x20, #0x504, lsl #32",
         "movk x20, #0x706, lsl #48",
-        "dup v6.2d, x20",
-        "add v5.16b, v6.16b, v5.16b",
-        "tbl v4.16b, {v4.16b}, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "dup v4.2d, x20",
+        "add v3.16b, v4.16b, v3.16b",
+        "tbl v2.16b, {v2.16b}, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, ymm2": {
@@ -567,29 +567,29 @@
         "Map 2 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "lsr z5.d, p7/m, z5.d, #1",
-        "mov z6.d, #1",
-        "and z5.d, z5.d, z6.d",
-        "trn1 z5.b, z5.b, z5.b",
-        "trn1 z5.h, z5.h, z5.h",
-        "trn1 z5.s, z5.s, z5.s",
-        "lsl z5.b, p7/m, z5.b, #3",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "lsr z3.d, p7/m, z3.d, #1",
+        "mov z4.d, #1",
+        "and z3.d, z3.d, z4.d",
+        "trn1 z3.b, z3.b, z3.b",
+        "trn1 z3.h, z3.h, z3.h",
+        "trn1 z3.s, z3.s, z3.s",
+        "lsl z3.b, p7/m, z3.b, #3",
         "mov x20, #0x100",
         "movk x20, #0x302, lsl #16",
         "movk x20, #0x504, lsl #32",
         "movk x20, #0x706, lsl #48",
-        "mov z6.d, x20",
-        "movi v7.2d, #0x0",
-        "mov z8.b, #16",
-        "mov z1.q, q8",
+        "mov z4.d, x20",
+        "movi v5.2d, #0x0",
+        "mov z6.b, #16",
+        "mov z1.q, q6",
         "not p0.b, p7/z, p6.b",
-        "mov z7.b, p0/m, z1.b",
-        "add z6.b, z6.b, z7.b",
-        "add z5.b, z6.b, z5.b",
-        "tbl z4.b, {z4.b}, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z5.b, p0/m, z1.b",
+        "add z4.b, z4.b, z5.b",
+        "add z3.b, z4.b, z3.b",
+        "tbl z2.b, {z2.b}, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vtestps xmm0, xmm1": {
@@ -599,20 +599,20 @@
         "Map 2 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
         "mov w20, #0x80000000",
-        "dup v6.4s, w20",
-        "and v7.16b, v5.16b, v4.16b",
-        "bic v4.16b, v5.16b, v4.16b",
-        "and v5.16b, v7.16b, v6.16b",
-        "and v4.16b, v4.16b, v6.16b",
-        "cnt v5.16b, v5.16b",
-        "cnt v4.16b, v4.16b",
-        "addv h5, v5.8h",
-        "addv h4, v4.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "dup v4.4s, w20",
+        "and v5.16b, v3.16b, v2.16b",
+        "bic v2.16b, v3.16b, v2.16b",
+        "and v3.16b, v5.16b, v4.16b",
+        "and v2.16b, v2.16b, v4.16b",
+        "cnt v3.16b, v3.16b",
+        "cnt v2.16b, v2.16b",
+        "addv h3, v3.8h",
+        "addv h2, v2.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -635,28 +635,28 @@
         "Map 2 0b01 0x0e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
         "mov w20, #0x80000000",
-        "mov z6.s, w20",
-        "and z7.d, z5.d, z4.d",
-        "bic z4.d, z5.d, z4.d",
-        "and z5.d, z7.d, z6.d",
-        "and z4.d, z4.d, z6.d",
-        "cnt z5.b, p7/m, z5.b",
-        "cnt z4.b, p7/m, z4.b",
+        "mov z4.s, w20",
+        "and z5.d, z3.d, z2.d",
+        "bic z2.d, z3.d, z2.d",
+        "and z3.d, z5.d, z4.d",
+        "and z2.d, z2.d, z4.d",
+        "cnt z3.b, p7/m, z3.b",
+        "cnt z2.b, p7/m, z2.b",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z5.d",
-        "addv h1, v5.8h",
+        "compact z0.d, p0, z3.d",
+        "addv h1, v3.8h",
         "addv h0, v0.8h",
-        "add v5.8h, v0.8h, v1.8h",
+        "add v3.8h, v0.8h, v1.8h",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "addv h1, v4.8h",
+        "compact z0.d, p0, z2.d",
+        "addv h1, v2.8h",
         "addv h0, v0.8h",
-        "add v4.8h, v0.8h, v1.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "add v2.8h, v0.8h, v1.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -679,20 +679,20 @@
         "Map 2 0b01 0x0f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
         "mov x20, #0x8000000000000000",
-        "dup v6.2d, x20",
-        "and v7.16b, v5.16b, v4.16b",
-        "bic v4.16b, v5.16b, v4.16b",
-        "and v5.16b, v7.16b, v6.16b",
-        "and v4.16b, v4.16b, v6.16b",
-        "cnt v5.16b, v5.16b",
-        "cnt v4.16b, v4.16b",
-        "addv h5, v5.8h",
-        "addv h4, v4.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "dup v4.2d, x20",
+        "and v5.16b, v3.16b, v2.16b",
+        "bic v2.16b, v3.16b, v2.16b",
+        "and v3.16b, v5.16b, v4.16b",
+        "and v2.16b, v2.16b, v4.16b",
+        "cnt v3.16b, v3.16b",
+        "cnt v2.16b, v2.16b",
+        "addv h3, v3.8h",
+        "addv h2, v2.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -715,28 +715,28 @@
         "Map 2 0b01 0x0f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
         "mov x20, #0x8000000000000000",
-        "mov z6.d, x20",
-        "and z7.d, z5.d, z4.d",
-        "bic z4.d, z5.d, z4.d",
-        "and z5.d, z7.d, z6.d",
-        "and z4.d, z4.d, z6.d",
-        "cnt z5.b, p7/m, z5.b",
-        "cnt z4.b, p7/m, z4.b",
+        "mov z4.d, x20",
+        "and z5.d, z3.d, z2.d",
+        "bic z2.d, z3.d, z2.d",
+        "and z3.d, z5.d, z4.d",
+        "and z2.d, z2.d, z4.d",
+        "cnt z3.b, p7/m, z3.b",
+        "cnt z2.b, p7/m, z2.b",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z5.d",
-        "addv h1, v5.8h",
+        "compact z0.d, p0, z3.d",
+        "addv h1, v3.8h",
         "addv h0, v0.8h",
-        "add v5.8h, v0.8h, v1.8h",
+        "add v3.8h, v0.8h, v1.8h",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "addv h1, v4.8h",
+        "compact z0.d, p0, z2.d",
+        "addv h1, v2.8h",
         "addv h0, v0.8h",
-        "add v4.8h, v0.8h, v1.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "add v2.8h, v0.8h, v1.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -775,19 +775,19 @@
         "Map 2 0b01 0x16 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.s, #7",
-        "and z4.d, z4.d, z6.d",
-        "trn1 z4.b, z4.b, z4.b",
-        "trn1 z4.h, z4.h, z4.h",
-        "lsl z4.b, p7/m, z4.b, #2",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.s, #7",
+        "and z2.d, z2.d, z4.d",
+        "trn1 z2.b, z2.b, z2.b",
+        "trn1 z2.h, z2.h, z2.h",
+        "lsl z2.b, p7/m, z2.b, #2",
         "mov w20, #0x100",
         "movk w20, #0x302, lsl #16",
-        "mov z6.s, w20",
-        "add z4.b, z4.b, z6.b",
-        "tbl z4.b, {z5.b}, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z4.s, w20",
+        "add z2.b, z2.b, z4.b",
+        "tbl z2.b, {z3.b}, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vptest xmm0, xmm1": {
@@ -797,16 +797,16 @@
         "Map 2 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and v6.16b, v4.16b, v5.16b",
-        "bic v4.16b, v5.16b, v4.16b",
-        "cnt v5.16b, v6.16b",
-        "cnt v4.16b, v4.16b",
-        "addv h5, v5.8h",
-        "addv h4, v4.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and v4.16b, v2.16b, v3.16b",
+        "bic v2.16b, v3.16b, v2.16b",
+        "cnt v3.16b, v4.16b",
+        "cnt v2.16b, v2.16b",
+        "addv h3, v3.8h",
+        "addv h2, v2.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -829,24 +829,24 @@
         "Map 2 0b01 0x16 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "and z6.d, z4.d, z5.d",
-        "bic z4.d, z5.d, z4.d",
-        "cnt z5.b, p7/m, z6.b",
-        "cnt z4.b, p7/m, z4.b",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "and z4.d, z2.d, z3.d",
+        "bic z2.d, z3.d, z2.d",
+        "cnt z3.b, p7/m, z4.b",
+        "cnt z2.b, p7/m, z2.b",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z5.d",
-        "addv h1, v5.8h",
+        "compact z0.d, p0, z3.d",
+        "addv h1, v3.8h",
         "addv h0, v0.8h",
-        "add v5.8h, v0.8h, v1.8h",
+        "add v3.8h, v0.8h, v1.8h",
         "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z4.d",
-        "addv h1, v4.8h",
+        "compact z0.d, p0, z2.d",
+        "addv h1, v2.8h",
         "addv h0, v0.8h",
-        "add v4.8h, v0.8h, v1.8h",
-        "umov w20, v5.h[0]",
-        "umov w21, v4.h[0]",
+        "add v2.8h, v0.8h, v1.8h",
+        "umov w20, v3.h[0]",
+        "umov w21, v2.h[0]",
         "mov w22, #0x0",
         "mov w23, #0x1",
         "cmp x20, #0x0 (0)",
@@ -869,9 +869,9 @@
         "Map 2 0b01 0x18 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rw {z4.s}, p6/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rw {z2.s}, p6/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vbroadcastss ymm0, [rax]": {
@@ -881,8 +881,8 @@
         "Map 2 0b01 0x18 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rw {z4.s}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rw {z2.s}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vbroadcastsd ymm0, [rax]": {
@@ -892,8 +892,8 @@
         "Map 2 0b01 0x19 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rd {z4.d}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rd {z2.d}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vbroadcastf128 ymm0, [rax]": {
@@ -903,8 +903,8 @@
         "Map 2 0b01 0x1a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rqb {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rqb {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsb xmm0, xmm1": {
@@ -914,10 +914,10 @@
         "Map 2 0b01 0x1c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs v4.16b, v4.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs v2.16b, v2.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsb ymm0, ymm1": {
@@ -927,9 +927,9 @@
         "Map 2 0b01 0x1c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs z4.b, p7/m, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs z2.b, p7/m, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsw xmm0, xmm1": {
@@ -939,10 +939,10 @@
         "Map 2 0b01 0x1d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs v4.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs v2.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsw ymm0, ymm1": {
@@ -952,9 +952,9 @@
         "Map 2 0b01 0x1d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs z4.h, p7/m, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs z2.h, p7/m, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsd xmm0, xmm1": {
@@ -964,10 +964,10 @@
         "Map 2 0b01 0x1e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpabsd ymm0, ymm1": {
@@ -977,9 +977,9 @@
         "Map 2 0b01 0x1e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "abs z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "abs z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbw xmm0, xmm1": {
@@ -989,10 +989,10 @@
         "Map 2 0b01 0x20 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.8h, v4.8b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.8h, v2.8b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbw ymm0, xmm1": {
@@ -1002,9 +1002,9 @@
         "Map 2 0b01 0x20 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.h, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.h, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbd xmm0, xmm1": {
@@ -1014,11 +1014,11 @@
         "Map 2 0b01 0x21 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.8h, v4.8b",
-        "sxtl v4.4s, v4.4h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.8h, v2.8b",
+        "sxtl v2.4s, v2.4h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbd ymm0, xmm1": {
@@ -1028,10 +1028,10 @@
         "Map 2 0b01 0x21 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.h, z4.b",
-        "sunpklo z4.s, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.h, z2.b",
+        "sunpklo z2.s, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbq xmm0, xmm1": {
@@ -1041,12 +1041,12 @@
         "Map 2 0b01 0x22 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.8h, v4.8b",
-        "sxtl v4.4s, v4.4h",
-        "sxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.8h, v2.8b",
+        "sxtl v2.4s, v2.4h",
+        "sxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxbq ymm0, xmm1": {
@@ -1056,11 +1056,11 @@
         "Map 2 0b01 0x22 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.h, z4.b",
-        "sunpklo z4.s, z4.h",
-        "sunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.h, z2.b",
+        "sunpklo z2.s, z2.h",
+        "sunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxwd xmm0, xmm1": {
@@ -1070,10 +1070,10 @@
         "Map 2 0b01 0x23 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.4s, v4.4h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.4s, v2.4h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxwd ymm0, xmm1": {
@@ -1083,9 +1083,9 @@
         "Map 2 0b01 0x23 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.s, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.s, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxwq xmm0, xmm1": {
@@ -1095,11 +1095,11 @@
         "Map 2 0b01 0x24 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.4s, v4.4h",
-        "sxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.4s, v2.4h",
+        "sxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxwq ymm0, xmm1": {
@@ -1109,10 +1109,10 @@
         "Map 2 0b01 0x24 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.s, z4.h",
-        "sunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.s, z2.h",
+        "sunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxdq xmm0, xmm1": {
@@ -1122,10 +1122,10 @@
         "Map 2 0b01 0x25 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovsxdq ymm0, xmm1": {
@@ -1135,9 +1135,9 @@
         "Map 2 0b01 0x25 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmuldq xmm0, xmm1, xmm2": {
@@ -1147,13 +1147,13 @@
         "Map 2 0b01 0x28 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 v4.4s, v4.4s, v4.4s",
-        "uzp1 v5.4s, v5.4s, v5.4s",
-        "smull v4.2d, v4.2s, v5.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 v2.4s, v2.4s, v2.4s",
+        "uzp1 v3.4s, v3.4s, v3.4s",
+        "smull v2.2d, v2.2s, v3.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmuldq ymm0, ymm1, ymm2": {
@@ -1163,14 +1163,14 @@
         "Map 2 0b01 0x28 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "uzp1 z4.s, z4.s, z4.s",
-        "uzp1 z5.s, z5.s, z5.s",
-        "smullb z0.d, z4.s, z5.s",
-        "smullt z1.d, z4.s, z5.s",
-        "zip1 z4.d, z0.d, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "uzp1 z2.s, z2.s, z2.s",
+        "uzp1 z3.s, z3.s, z3.s",
+        "smullb z0.d, z2.s, z3.s",
+        "smullt z1.d, z2.s, z3.s",
+        "zip1 z2.d, z0.d, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqq xmm0, xmm1, xmm2": {
@@ -1180,11 +1180,11 @@
         "Map 2 0b01 0x29 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmeq v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmeq v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpeqq ymm0, ymm1, ymm2": {
@@ -1194,13 +1194,13 @@
         "Map 2 0b01 0x29 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpeq p0.d, p7/z, z4.d, z5.d",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpeq p0.d, p7/z, z2.d, z3.d",
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovntdqa xmm0, [rax]": {
@@ -1210,8 +1210,8 @@
         "Map 2 0b01 0x2a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q4, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q2, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmovntdqa ymm0, [rax]": {
@@ -1221,8 +1221,8 @@
         "Map 2 0b01 0x2a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1b {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1b {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackusdw xmm0, xmm1, xmm2": {
@@ -1232,12 +1232,12 @@
         "Map 2 0b01 0x2b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtun v4.4h, v4.4s",
-        "sqxtun2 v4.8h, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtun v2.4h, v2.4s",
+        "sqxtun2 v2.8h, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpackusdw ymm0, ymm1, ymm2": {
@@ -1247,24 +1247,24 @@
         "Map 2 0b01 0x2b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "sqxtunb z1.h, z5.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "sqxtunb z1.h, z3.s",
         "uzp1 z1.h, z1.h, z1.h",
-        "sqxtunb z4.h, z4.s",
-        "uzp1 z4.h, z4.h, z4.h",
-        "splice z4.h, p6, z4.h, z1.h",
-        "mov z1.d, z4.d[1]",
-        "mov z5.d, z4.d",
+        "sqxtunb z2.h, z2.s",
+        "uzp1 z2.h, z2.h, z2.h",
+        "splice z2.h, p6, z2.h, z1.h",
+        "mov z1.d, z2.d[1]",
+        "mov z3.d, z2.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovps xmm0, xmm1, [rax]": {
@@ -1274,11 +1274,11 @@
         "Map 2 0b01 0x2c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.s, p6/z, z4.s, #0",
-        "ld1w {z4.s}, p0/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.s, p6/z, z2.s, #0",
+        "ld1w {z2.s}, p0/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovps ymm0, ymm1, [rax]": {
@@ -1288,10 +1288,10 @@
         "Map 2 0b01 0x2c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.s, p7/z, z4.s, #0",
-        "ld1w {z4.s}, p0/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.s, p7/z, z2.s, #0",
+        "ld1w {z2.s}, p0/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovpd xmm0, xmm1, [rax]": {
@@ -1301,11 +1301,11 @@
         "Map 2 0b01 0x2d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.d, p6/z, z4.d, #0",
-        "ld1d {z4.d}, p0/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.d, p6/z, z2.d, #0",
+        "ld1d {z2.d}, p0/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovpd ymm0, ymm1, [rax]": {
@@ -1315,10 +1315,10 @@
         "Map 2 0b01 0x2d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.d, p7/z, z4.d, #0",
-        "ld1d {z4.d}, p0/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.d, p7/z, z2.d, #0",
+        "ld1d {z2.d}, p0/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmaskmovps [rax], xmm0, xmm1": {
@@ -1328,10 +1328,10 @@
         "Map 2 0b01 0x2e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.s, p6/z, z4.s, #0",
-        "st1w {z5.s}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.s, p6/z, z2.s, #0",
+        "st1w {z3.s}, p0, [x4]"
       ]
     },
     "vmaskmovps [rax], ymm0, ymm1": {
@@ -1341,10 +1341,10 @@
         "Map 2 0b01 0x2e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.s, p7/z, z4.s, #0",
-        "st1w {z5.s}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.s, p7/z, z2.s, #0",
+        "st1w {z3.s}, p0, [x4]"
       ]
     },
     "vmaskmovpd [rax], xmm0, xmm1": {
@@ -1354,10 +1354,10 @@
         "Map 2 0b01 0x2f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.d, p6/z, z4.d, #0",
-        "st1d {z5.d}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.d, p6/z, z2.d, #0",
+        "st1d {z3.d}, p0, [x4]"
       ]
     },
     "vmaskmovpd [rax], ymm0, ymm1": {
@@ -1367,10 +1367,10 @@
         "Map 2 0b01 0x2f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.d, p7/z, z4.d, #0",
-        "st1d {z5.d}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.d, p7/z, z2.d, #0",
+        "st1d {z3.d}, p0, [x4]"
       ]
     },
     "vpmovzxbw xmm0, xmm1": {
@@ -1380,10 +1380,10 @@
         "Map 2 0b01 0x30 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.8h, v4.8b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.8h, v2.8b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxbw ymm0, xmm1": {
@@ -1393,9 +1393,9 @@
         "Map 2 0b01 0x30 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.h, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.h, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxbd xmm0, xmm1": {
@@ -1405,11 +1405,11 @@
         "Map 2 0b01 0x31 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.8h, v4.8b",
-        "uxtl v4.4s, v4.4h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.8h, v2.8b",
+        "uxtl v2.4s, v2.4h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxbd ymm0, xmm1": {
@@ -1419,10 +1419,10 @@
         "Map 2 0b01 0x31 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.h, z4.b",
-        "uunpklo z4.s, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.h, z2.b",
+        "uunpklo z2.s, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxbq xmm0, xmm1": {
@@ -1432,12 +1432,12 @@
         "Map 2 0b01 0x32 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.8h, v4.8b",
-        "uxtl v4.4s, v4.4h",
-        "uxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.8h, v2.8b",
+        "uxtl v2.4s, v2.4h",
+        "uxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxbq ymm0, xmm1": {
@@ -1447,11 +1447,11 @@
         "Map 2 0b01 0x32 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.h, z4.b",
-        "uunpklo z4.s, z4.h",
-        "uunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.h, z2.b",
+        "uunpklo z2.s, z2.h",
+        "uunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxwd xmm0, xmm1": {
@@ -1461,10 +1461,10 @@
         "Map 2 0b01 0x33 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.4s, v4.4h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.4s, v2.4h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxwd ymm0, xmm1": {
@@ -1474,9 +1474,9 @@
         "Map 2 0b01 0x33 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.s, z4.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.s, z2.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxwq xmm0, xmm1": {
@@ -1486,11 +1486,11 @@
         "Map 2 0b01 0x34 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.4s, v4.4h",
-        "uxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.4s, v2.4h",
+        "uxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxwq ymm0, xmm1": {
@@ -1500,10 +1500,10 @@
         "Map 2 0b01 0x34 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.s, z4.h",
-        "uunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.s, z2.h",
+        "uunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxdq xmm0, xmm1": {
@@ -1513,10 +1513,10 @@
         "Map 2 0b01 0x35 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uxtl v4.2d, v4.2s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uxtl v2.2d, v2.2s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmovzxdq ymm0, xmm1": {
@@ -1526,9 +1526,9 @@
         "Map 2 0b01 0x35 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "uunpklo z4.d, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "uunpklo z2.d, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermd ymm0, ymm1, ymm2": {
@@ -1538,19 +1538,19 @@
         "Map 2 0b01 0x36 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.s, #7",
-        "and z4.d, z4.d, z6.d",
-        "trn1 z4.b, z4.b, z4.b",
-        "trn1 z4.h, z4.h, z4.h",
-        "lsl z4.b, p7/m, z4.b, #2",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.s, #7",
+        "and z2.d, z2.d, z4.d",
+        "trn1 z2.b, z2.b, z2.b",
+        "trn1 z2.h, z2.h, z2.h",
+        "lsl z2.b, p7/m, z2.b, #2",
         "mov w20, #0x100",
         "movk w20, #0x302, lsl #16",
-        "mov z6.s, w20",
-        "add z4.b, z4.b, z6.b",
-        "tbl z4.b, {z5.b}, z4.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z4.s, w20",
+        "add z2.b, z2.b, z4.b",
+        "tbl z2.b, {z3.b}, z2.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtq xmm0, xmm1, xmm2": {
@@ -1560,11 +1560,11 @@
         "Map 2 0b01 0x37 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmgt v4.2d, v4.2d, v5.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmgt v2.2d, v2.2d, v3.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpcmpgtq ymm0, ymm1, ymm2": {
@@ -1574,13 +1574,13 @@
         "Map 2 0b01 0x37 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "cmpgt p0.d, p7/z, z4.d, z5.d",
-        "not z0.d, p0/m, z4.d",
-        "movprfx z4.d, p0/z, z4.d",
-        "orr z4.d, p0/m, z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "cmpgt p0.d, p7/z, z2.d, z3.d",
+        "not z0.d, p0/m, z2.d",
+        "movprfx z2.d, p0/z, z2.d",
+        "orr z2.d, p0/m, z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsb xmm0, xmm1, xmm2": {
@@ -1590,11 +1590,11 @@
         "Map 2 0b01 0x38 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsb ymm0, ymm1, ymm2": {
@@ -1604,10 +1604,10 @@
         "Map 2 0b01 0x38 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin z4.b, p7/m, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin z2.b, p7/m, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsd xmm0, xmm1, xmm2": {
@@ -1617,11 +1617,11 @@
         "Map 2 0b01 0x39 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminsd ymm0, ymm1, ymm2": {
@@ -1631,10 +1631,10 @@
         "Map 2 0b01 0x39 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smin z4.s, p7/m, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smin z2.s, p7/m, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminuw xmm0, xmm1, xmm2": {
@@ -1644,11 +1644,11 @@
         "Map 2 0b01 0x3a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminuw ymm0, ymm1, ymm2": {
@@ -1658,10 +1658,10 @@
         "Map 2 0b01 0x3a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin z4.h, p7/m, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin z2.h, p7/m, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminud xmm0, xmm1, xmm2": {
@@ -1671,11 +1671,11 @@
         "Map 2 0b01 0x3b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpminud ymm0, ymm1, ymm2": {
@@ -1685,10 +1685,10 @@
         "Map 2 0b01 0x3b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umin z4.s, p7/m, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umin z2.s, p7/m, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsb xmm0, xmm1, xmm2": {
@@ -1698,11 +1698,11 @@
         "Map 2 0b01 0x3c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsb ymm0, ymm1, ymm2": {
@@ -1712,10 +1712,10 @@
         "Map 2 0b01 0x3c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax z4.b, p7/m, z4.b, z5.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax z2.b, p7/m, z2.b, z3.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsd xmm0, xmm1, xmm2": {
@@ -1725,11 +1725,11 @@
         "Map 2 0b01 0x3d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxsd ymm0, ymm1, ymm2": {
@@ -1739,10 +1739,10 @@
         "Map 2 0b01 0x3d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "smax z4.s, p7/m, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "smax z2.s, p7/m, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxuw xmm0, xmm1, xmm2": {
@@ -1752,11 +1752,11 @@
         "Map 2 0b01 0x3e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax v4.8h, v4.8h, v5.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax v2.8h, v2.8h, v3.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxuw ymm0, ymm1, ymm2": {
@@ -1766,10 +1766,10 @@
         "Map 2 0b01 0x3e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax z4.h, p7/m, z4.h, z5.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax z2.h, p7/m, z2.h, z3.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxud xmm0, xmm1, xmm2": {
@@ -1779,11 +1779,11 @@
         "Map 2 0b01 0x3f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaxud ymm0, ymm1, ymm2": {
@@ -1793,10 +1793,10 @@
         "Map 2 0b01 0x3f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "umax z4.s, p7/m, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "umax z2.s, p7/m, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulld xmm0, xmm1, xmm2": {
@@ -1806,11 +1806,11 @@
         "Map 2 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mul v4.4s, v4.4s, v5.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mul v2.4s, v2.4s, v3.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmulld ymm0, ymm1, ymm2": {
@@ -1820,10 +1820,10 @@
         "Map 2 0b01 0x40 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mul z4.s, z4.s, z5.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mul z2.s, z2.s, z3.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vphminposuw xmm0, xmm1": {
@@ -1833,16 +1833,16 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "ldr x0, [x28, #1552]",
-        "ldr q5, [x0]",
-        "zip1 v6.8h, v5.8h, v4.8h",
-        "zip2 v4.8h, v5.8h, v4.8h",
-        "umin v4.4s, v6.4s, v4.4s",
-        "uminv s4, v4.4s",
-        "rev32 v4.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ldr q3, [x0]",
+        "zip1 v4.8h, v3.8h, v2.8h",
+        "zip2 v2.8h, v3.8h, v2.8h",
+        "umin v2.4s, v4.4s, v2.4s",
+        "uminv s2, v2.4s",
+        "rev32 v2.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlvd xmm0, xmm1, xmm2": {
@@ -1852,14 +1852,14 @@
         "Map 2 0b01 0x45 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "movi v0.4s, #0x20, lsl #0",
-        "umin v0.4s, v0.4s, v5.4s",
+        "umin v0.4s, v0.4s, v3.4s",
         "neg v0.4s, v0.4s",
-        "ushl v4.4s, v4.4s, v0.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ushl v2.4s, v2.4s, v0.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlvd ymm0, ymm1, ymm2": {
@@ -1869,12 +1869,12 @@
         "Map 2 0b01 0x45 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov z1.s, #32",
-        "umin z1.s, p7/m, z1.s, z5.s",
-        "lsr z4.s, p7/m, z4.s, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "umin z1.s, p7/m, z1.s, z3.s",
+        "lsr z2.s, p7/m, z2.s, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlvq xmm0, xmm1, xmm2": {
@@ -1884,16 +1884,16 @@
         "Map 2 0b01 0x45 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov w0, #0x40",
         "dup v0.2d, x0",
-        "cmhi v1.2d, v5.2d, v0.2d",
-        "bif v0.16b, v5.16b, v1.16b",
+        "cmhi v1.2d, v3.2d, v0.2d",
+        "bif v0.16b, v3.16b, v1.16b",
         "neg v0.2d, v0.2d",
-        "ushl v4.2d, v4.2d, v0.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ushl v2.2d, v2.2d, v0.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlvq ymm0, ymm1, ymm2": {
@@ -1903,12 +1903,12 @@
         "Map 2 0b01 0x45 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov z1.d, #64",
-        "umin z1.d, p7/m, z1.d, z5.d",
-        "lsr z4.d, p7/m, z4.d, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "umin z1.d, p7/m, z1.d, z3.d",
+        "lsr z2.d, p7/m, z2.d, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsravd xmm0, xmm1, xmm2": {
@@ -1918,14 +1918,14 @@
         "Map 2 0b01 0x46 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "movi v0.4s, #0x1f, lsl #0",
-        "umin v0.4s, v0.4s, v5.4s",
+        "umin v0.4s, v0.4s, v3.4s",
         "neg v0.4s, v0.4s",
-        "sshl v4.4s, v4.4s, v0.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "sshl v2.4s, v2.4s, v0.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsravd ymm0, ymm1, ymm2": {
@@ -1935,12 +1935,12 @@
         "Map 2 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov z0.s, #31",
-        "umin z0.s, p7/m, z0.s, z5.s",
-        "asr z4.s, p7/m, z4.s, z0.s",
-        "mov z16.d, p7/m, z4.d"
+        "umin z0.s, p7/m, z0.s, z3.s",
+        "asr z2.s, p7/m, z2.s, z0.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllvd xmm0, xmm1, xmm2": {
@@ -1950,13 +1950,13 @@
         "Map 2 0b01 0x47 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "movi v0.4s, #0x20, lsl #0",
-        "umin v0.4s, v0.4s, v5.4s",
-        "ushl v4.4s, v4.4s, v0.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "umin v0.4s, v0.4s, v3.4s",
+        "ushl v2.4s, v2.4s, v0.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllvd ymm0, ymm1, ymm2": {
@@ -1966,12 +1966,12 @@
         "Map 2 0b01 0x47 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov z1.s, #32",
-        "umin z1.s, p7/m, z1.s, z5.s",
-        "lsl z4.s, p7/m, z4.s, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "umin z1.s, p7/m, z1.s, z3.s",
+        "lsl z2.s, p7/m, z2.s, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllvq xmm0, xmm1, xmm2": {
@@ -1981,15 +1981,15 @@
         "Map 2 0b01 0x47 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov w0, #0x40",
         "dup v0.2d, x0",
-        "cmhi v1.2d, v5.2d, v0.2d",
-        "bif v0.16b, v5.16b, v1.16b",
-        "ushl v4.2d, v4.2d, v0.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "cmhi v1.2d, v3.2d, v0.2d",
+        "bif v0.16b, v3.16b, v1.16b",
+        "ushl v2.2d, v2.2d, v0.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllvq ymm0, ymm1, ymm2": {
@@ -1999,12 +1999,12 @@
         "Map 2 0b01 0x47 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "mov z1.d, #64",
-        "umin z1.d, p7/m, z1.d, z5.d",
-        "lsl z4.d, p7/m, z4.d, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "umin z1.d, p7/m, z1.d, z3.d",
+        "lsl z2.d, p7/m, z2.d, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastd xmm0, xmm1": {
@@ -2014,10 +2014,10 @@
         "Map 2 0b01 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "dup v4.4s, v4.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "dup v2.4s, v2.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastd xmm0, [rax]": {
@@ -2027,9 +2027,9 @@
         "Map 2 0b01 0x58 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rw {z4.s}, p6/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rw {z2.s}, p6/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastd ymm0, xmm1": {
@@ -2039,9 +2039,9 @@
         "Map 2 0b01 0x58 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.s, s4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.s, s2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastd ymm0, [rax]": {
@@ -2051,8 +2051,8 @@
         "Map 2 0b01 0x58 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rw {z4.s}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rw {z2.s}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastq xmm0, xmm1": {
@@ -2062,10 +2062,10 @@
         "Map 2 0b01 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "dup v4.2d, v4.d[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "dup v2.2d, v2.d[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastq xmm0, [rax]": {
@@ -2075,9 +2075,9 @@
         "Map 2 0b01 0x59 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rd {z4.d}, p6/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rd {z2.d}, p6/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastq ymm0, xmm1": {
@@ -2087,9 +2087,9 @@
         "Map 2 0b01 0x59 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, d4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, d2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastq ymm0, [rax]": {
@@ -2100,8 +2100,8 @@
       ],
       "ExpectedInstructionCount": 2,
       "ExpectedArm64ASM": [
-        "ld1rd {z4.d}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rd {z2.d}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vbroadcasti128 ymm0, [rax]": {
@@ -2111,8 +2111,8 @@
         "Map 2 0b01 0x5a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rqb {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rqb {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastb xmm0, xmm1": {
@@ -2122,10 +2122,10 @@
         "Map 2 0b01 0x78 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "dup v4.16b, v4.b[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "dup v2.16b, v2.b[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastb xmm0, [rax]": {
@@ -2135,9 +2135,9 @@
         "Map 2 0b01 0x78 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rb {z4.b}, p6/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rb {z2.b}, p6/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastb ymm0, xmm1": {
@@ -2147,9 +2147,9 @@
         "Map 2 0b01 0x78 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.b, b4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.b, b2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastb ymm0, [rax]": {
@@ -2160,8 +2160,8 @@
       ],
       "ExpectedInstructionCount": 2,
       "ExpectedArm64ASM": [
-        "ld1rb {z4.b}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rb {z2.b}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastw xmm0, xmm1": {
@@ -2171,10 +2171,10 @@
         "Map 2 0b01 0x79 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "dup v4.8h, v4.h[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "dup v2.8h, v2.h[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastw xmm0, [rax]": {
@@ -2184,9 +2184,9 @@
         "Map 2 0b01 0x79 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ld1rh {z4.h}, p6/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rh {z2.h}, p6/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastw ymm0, xmm1": {
@@ -2196,9 +2196,9 @@
         "Map 2 0b01 0x79 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.h, h4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.h, h2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpbroadcastw ymm0, [rax]": {
@@ -2209,8 +2209,8 @@
       ],
       "ExpectedInstructionCount": 2,
       "ExpectedArm64ASM": [
-        "ld1rh {z4.h}, p7/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "ld1rh {z2.h}, p7/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaskmovd xmm0, xmm1, [rax]": {
@@ -2220,11 +2220,11 @@
         "Map 2 0b01 0x8c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.s, p6/z, z4.s, #0",
-        "ld1w {z4.s}, p0/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.s, p6/z, z2.s, #0",
+        "ld1w {z2.s}, p0/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaskmovd ymm0, ymm1, [rax]": {
@@ -2234,10 +2234,10 @@
         "Map 2 0b01 0x8c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.s, p7/z, z4.s, #0",
-        "ld1w {z4.s}, p0/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.s, p7/z, z2.s, #0",
+        "ld1w {z2.s}, p0/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaskmovq xmm0, xmm1, [rax]": {
@@ -2247,11 +2247,11 @@
         "Map 2 0b01 0x8c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.d, p6/z, z4.d, #0",
-        "ld1d {z4.d}, p0/z, [x4]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.d, p6/z, z2.d, #0",
+        "ld1d {z2.d}, p0/z, [x4]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaskmovq ymm0, ymm1, [rax]": {
@@ -2261,10 +2261,10 @@
         "Map 2 0b01 0x8c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "cmplt p0.d, p7/z, z4.d, #0",
-        "ld1d {z4.d}, p0/z, [x4]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "cmplt p0.d, p7/z, z2.d, #0",
+        "ld1d {z2.d}, p0/z, [x4]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpmaskmovd [rax], xmm0, xmm1": {
@@ -2274,10 +2274,10 @@
         "Map 2 0b01 0x8e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.s, p6/z, z4.s, #0",
-        "st1w {z5.s}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.s, p6/z, z2.s, #0",
+        "st1w {z3.s}, p0, [x4]"
       ]
     },
     "vpmaskmovd [rax], ymm0, ymm1": {
@@ -2287,10 +2287,10 @@
         "Map 2 0b01 0x8e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.s, p7/z, z4.s, #0",
-        "st1w {z5.s}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.s, p7/z, z2.s, #0",
+        "st1w {z3.s}, p0, [x4]"
       ]
     },
     "vpmaskmovq [rax], xmm0, xmm1": {
@@ -2300,10 +2300,10 @@
         "Map 2 0b01 0x8e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.d, p6/z, z4.d, #0",
-        "st1d {z5.d}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.d, p6/z, z2.d, #0",
+        "st1d {z3.d}, p0, [x4]"
       ]
     },
     "vpmaskmovq [rax], ymm0, ymm1": {
@@ -2313,10 +2313,10 @@
         "Map 2 0b01 0x8e 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "cmplt p0.d, p7/z, z4.d, #0",
-        "st1d {z5.d}, p0, [x4]"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "cmplt p0.d, p7/z, z2.d, #0",
+        "st1d {z3.d}, p0, [x4]"
       ]
     },
     "vpgatherdd xmm0, [xmm1*1 + rax], xmm2": {
@@ -3606,10 +3606,10 @@
         "Map 2 0b01 0xdb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "unimplemented (Unimplemented)",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaesenc xmm0, xmm1, xmm2": {
@@ -3619,14 +3619,14 @@
         "Map 2 0b01 0xdc 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
         "unimplemented (Unimplemented)",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaesenc ymm0, ymm1, ymm2": {
@@ -3644,13 +3644,13 @@
         "Map 2 0b01 0xdd 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaesenclast ymm0, ymm1, ymm2": {
@@ -3668,14 +3668,14 @@
         "Map 2 0b01 0xde 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
         "unimplemented (Unimplemented)",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaesdec ymm0, ymm1, ymm2": {
@@ -3693,13 +3693,13 @@
         "Map 2 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
-        "eor v4.16b, v4.16b, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "eor v2.16b, v2.16b, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaesdeclast ymm0, ymm1, ymm2": {
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index 44cbf9558..3bb36d0f2 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -14,9 +14,9 @@
         "Map 3 0b01 0x00 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, d4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, d2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermq ymm0, ymm1, 01010101b": {
@@ -26,9 +26,9 @@
         "Map 3 0b01 0x00 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[1]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[1]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermq ymm0, ymm1, 10101010b": {
@@ -38,9 +38,9 @@
         "Map 3 0b01 0x00 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[2]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[2]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermq ymm0, ymm1, 11111111b": {
@@ -50,9 +50,9 @@
         "Map 3 0b01 0x00 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[3]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[3]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermpd ymm0, ymm1, 00000000b": {
@@ -62,9 +62,9 @@
         "Map 3 0b01 0x01 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, d4",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, d2",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermpd ymm0, ymm1, 01010101b": {
@@ -74,9 +74,9 @@
         "Map 3 0b01 0x01 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[1]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[1]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermpd ymm0, ymm1, 10101010b": {
@@ -86,9 +86,9 @@
         "Map 3 0b01 0x01 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[2]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[2]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermpd ymm0, ymm1, 11111111b": {
@@ -98,9 +98,9 @@
         "Map 3 0b01 0x01 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.d, z4.d[3]",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.d, z2.d[3]",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0000b": {
@@ -110,9 +110,9 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0001b": {
@@ -122,19 +122,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[0], v5.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[1]",
-        "mov v5.s[2], v4.s[2]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[0], v3.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[1]",
+        "mov v3.s[2], v2.s[2]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0010b": {
@@ -144,19 +144,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v5.s[1]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[2], v4.s[2]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v3.s[1]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[2], v2.s[2]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0011b": {
@@ -166,19 +166,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v5.s[1]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[2], v4.s[2]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v3.s[1]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[2], v2.s[2]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0100b": {
@@ -188,19 +188,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v6.s[1], v4.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v5.s[2]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v4.s[1], v2.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v3.s[2]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0101b": {
@@ -210,19 +210,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v6.s[1], v4.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v5.s[2]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v4.s[1], v2.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v3.s[2]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0110b": {
@@ -232,19 +232,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v6.s[1], v5.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v5.s[2]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v4.s[1], v3.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v3.s[2]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 0111b": {
@@ -254,19 +254,19 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v6.s[1], v5.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v5.s[2]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v4.s[1], v3.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v3.s[2]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1000b": {
@@ -276,17 +276,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v6.s[1], v4.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v4.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v4.s[1], v2.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v2.s[2]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1001b": {
@@ -296,17 +296,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v6.s[1], v4.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v4.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v4.s[1], v2.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v2.s[2]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1010b": {
@@ -316,17 +316,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v6.s[1], v5.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v4.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v4.s[1], v3.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v2.s[2]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1011b": {
@@ -336,17 +336,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v6.s[1], v5.s[1]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[2], v4.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v4.s[1], v3.s[1]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[2], v2.s[2]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1100b": {
@@ -356,17 +356,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v4.s[0]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[2]",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v2.s[0]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[2]",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1101b": {
@@ -376,17 +376,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v6.s[0], v5.s[0]",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[1], v4.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[2], v5.s[2]",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v4.s[0], v3.s[0]",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[1], v2.s[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[2], v3.s[2]",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1110b": {
@@ -396,17 +396,17 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.s[1], v5.s[1]",
-        "mov v4.s[2], v5.s[2]",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.s[1], v3.s[1]",
+        "mov v2.s[2], v3.s[2]",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd xmm0, xmm1, 1111b": {
@@ -416,9 +416,9 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd ymm0, ymm1, 00000000b": {
@@ -428,8 +428,8 @@
         "Map 3 0b01 0x02 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z16.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd ymm0, ymm1, 01010101b": {
@@ -439,44 +439,44 @@
         "Map 3 0b01 0x02 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.s, s5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[1]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[2]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[3]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[4]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[6]",
-        "mov z5.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[6]",
+        "mov z3.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd ymm0, ymm1, 10101010b": {
@@ -486,43 +486,43 @@
         "Map 3 0b01 0x02 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.s, s4",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[1]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[2]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[3]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z5.s[5]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z3.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[7]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendd ymm0, ymm1, 11111111b": {
@@ -532,8 +532,8 @@
         "Map 3 0b01 0x02 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps xmm0, xmm1, 00000000b": {
@@ -543,16 +543,16 @@
         "Map 3 0b01 0x03 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.s[0], v4.s[0]",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.s[0], v2.s[0]",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps xmm0, xmm1, 01010101b": {
@@ -562,16 +562,16 @@
         "Map 3 0b01 0x03 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.s[0], v4.s[1]",
-        "mov v5.s[1], v4.s[1]",
-        "mov v5.s[2], v4.s[1]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.s[0], v2.s[1]",
+        "mov v3.s[1], v2.s[1]",
+        "mov v3.s[2], v2.s[1]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps xmm0, xmm1, 10101010b": {
@@ -581,16 +581,16 @@
         "Map 3 0b01 0x03 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.s[0], v4.s[2]",
-        "mov v5.s[1], v4.s[2]",
-        "mov v5.s[2], v4.s[2]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[2]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.s[0], v2.s[2]",
+        "mov v3.s[1], v2.s[2]",
+        "mov v3.s[2], v2.s[2]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[2]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps xmm0, xmm1, 11111111b": {
@@ -600,16 +600,16 @@
         "Map 3 0b01 0x03 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.s[0], v4.s[3]",
-        "mov v5.s[1], v4.s[3]",
-        "mov v5.s[2], v4.s[3]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.s[0], v2.s[3]",
+        "mov v3.s[1], v2.s[3]",
+        "mov v3.s[2], v2.s[3]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps ymm0, ymm1, 00000000b": {
@@ -619,42 +619,42 @@
         "Map 3 0b01 0x03 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.s, s4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps ymm0, ymm1, 01010101b": {
@@ -664,42 +664,42 @@
         "Map 3 0b01 0x03 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.s, z4.s[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[1]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[1]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[1]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps ymm0, ymm1, 10101010b": {
@@ -709,42 +709,42 @@
         "Map 3 0b01 0x03 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.s, z4.s[2]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[2]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[2]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[2]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilps ymm0, ymm1, 11111111b": {
@@ -754,42 +754,42 @@
         "Map 3 0b01 0x03 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.s, z4.s[3]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[3]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[3]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[3]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, z4.s[7]",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, z2.s[7]",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd xmm0, xmm1, 00b": {
@@ -799,14 +799,14 @@
         "Map 3 0b01 0x05 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.d[0], v4.d[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.d[0], v2.d[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd xmm0, xmm1, 01b": {
@@ -816,14 +816,14 @@
         "Map 3 0b01 0x05 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.d[0], v4.d[1]",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.d[0], v2.d[1]",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd xmm0, xmm1, 10b": {
@@ -833,14 +833,14 @@
         "Map 3 0b01 0x05 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.d[0], v4.d[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.d[0], v2.d[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd xmm0, xmm1, 11b": {
@@ -850,14 +850,14 @@
         "Map 3 0b01 0x05 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov v5.d[0], v4.d[1]",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov v3.d[0], v2.d[1]",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0000b": {
@@ -867,26 +867,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0001b": {
@@ -896,26 +896,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0010b": {
@@ -925,26 +925,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0011b": {
@@ -954,26 +954,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0100b": {
@@ -983,26 +983,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0101b": {
@@ -1012,26 +1012,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0110b": {
@@ -1041,26 +1041,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 0111b": {
@@ -1070,26 +1070,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1000b": {
@@ -1099,26 +1099,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1001b": {
@@ -1128,26 +1128,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1010b": {
@@ -1157,26 +1157,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1011b": {
@@ -1186,26 +1186,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1100b": {
@@ -1215,26 +1215,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1101b": {
@@ -1244,26 +1244,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, d4",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1110b": {
@@ -1273,26 +1273,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpermilpd ymm0, ymm1, 1111b": {
@@ -1302,26 +1302,26 @@
         "Map 3 0b01 0x05 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.d, z4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 000000b": {
@@ -1331,15 +1331,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 000001b": {
@@ -1349,15 +1349,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 000010b": {
@@ -1367,17 +1367,17 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q5",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q3",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 000011b": {
@@ -1387,17 +1387,17 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z5.q[1]",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z3.q[1]",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 010000b": {
@@ -1407,15 +1407,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 010001b": {
@@ -1425,15 +1425,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 010010b": {
@@ -1443,17 +1443,17 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q5",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q3",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 010011b": {
@@ -1463,17 +1463,17 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z5.q[1]",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z3.q[1]",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 100000b": {
@@ -1483,16 +1483,16 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 100001b": {
@@ -1502,16 +1502,16 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 100010b": {
@@ -1521,15 +1521,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 100011b": {
@@ -1539,15 +1539,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 110000b": {
@@ -1557,16 +1557,16 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 110001b": {
@@ -1576,16 +1576,16 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov z5.d, p7/m, z17.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
+        "mov z2.d, p7/m, z16.d",
+        "mov z3.d, p7/m, z17.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 110010b": {
@@ -1595,15 +1595,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2f128 ymm0, ymm1, 110011b": {
@@ -1613,15 +1613,15 @@
         "Map 3 0b01 0x06 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps xmm0, xmm1, 00000000b": {
@@ -1632,10 +1632,10 @@
         "Map 3 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps xmm0, xmm1, 00000001b": {
@@ -1646,10 +1646,10 @@
         "Map 3 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps xmm0, xmm1, 00000010b": {
@@ -1660,10 +1660,10 @@
         "Map 3 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps xmm0, xmm1, 00000011b": {
@@ -1674,10 +1674,10 @@
         "Map 3 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps xmm0, xmm1, 00000100b": {
@@ -1688,10 +1688,10 @@
         "Map 3 0b01 0x08 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti v4.4s, v4.4s",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti v2.4s, v2.4s",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps ymm0, ymm1, 00000000b": {
@@ -1702,9 +1702,9 @@
         "Map 3 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps ymm0, ymm1, 00000001b": {
@@ -1715,9 +1715,9 @@
         "Map 3 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps ymm0, ymm1, 00000010b": {
@@ -1728,9 +1728,9 @@
         "Map 3 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps ymm0, ymm1, 00000011b": {
@@ -1741,9 +1741,9 @@
         "Map 3 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundps ymm0, ymm1, 00000100b": {
@@ -1754,9 +1754,9 @@
         "Map 3 0b01 0x08 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti z4.s, p7/m, z4.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti z2.s, p7/m, z2.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd xmm0, xmm1, 00000000b": {
@@ -1767,10 +1767,10 @@
         "Map 3 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd xmm0, xmm1, 00000001b": {
@@ -1781,10 +1781,10 @@
         "Map 3 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd xmm0, xmm1, 00000010b": {
@@ -1795,10 +1795,10 @@
         "Map 3 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd xmm0, xmm1, 00000011b": {
@@ -1809,10 +1809,10 @@
         "Map 3 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd xmm0, xmm1, 00000100b": {
@@ -1823,10 +1823,10 @@
         "Map 3 0b01 0x09 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti v4.2d, v4.2d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti v2.2d, v2.2d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd ymm0, ymm1, 00000000b": {
@@ -1837,9 +1837,9 @@
         "Map 3 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd ymm0, ymm1, 00000001b": {
@@ -1850,9 +1850,9 @@
         "Map 3 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd ymm0, ymm1, 00000010b": {
@@ -1863,9 +1863,9 @@
         "Map 3 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd ymm0, ymm1, 00000011b": {
@@ -1876,9 +1876,9 @@
         "Map 3 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundpd ymm0, ymm1, 00000100b": {
@@ -1889,9 +1889,9 @@
         "Map 3 0b01 0x09 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti z4.d, p7/m, z4.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti z2.d, p7/m, z2.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundss xmm0, xmm1, 00000000b": {
@@ -1902,14 +1902,14 @@
         "Map 3 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn s4, s4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn s2, s2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundss xmm0, xmm1, 00000001b": {
@@ -1920,14 +1920,14 @@
         "Map 3 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm s4, s4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm s2, s2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundss xmm0, xmm1, 00000010b": {
@@ -1938,14 +1938,14 @@
         "Map 3 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp s4, s4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp s2, s2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundss xmm0, xmm1, 00000011b": {
@@ -1956,14 +1956,14 @@
         "Map 3 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz s4, s4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz s2, s2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundss xmm0, xmm1, 00000100b": {
@@ -1974,14 +1974,14 @@
         "Map 3 0b01 0x0a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti s4, s4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti s2, s2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundsd xmm0, xmm1, 00000000b": {
@@ -1992,14 +1992,14 @@
         "Map 3 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintn d4, d4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintn d2, d2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundsd xmm0, xmm1, 00000001b": {
@@ -2010,14 +2010,14 @@
         "Map 3 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintm d4, d4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintm d2, d2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundsd xmm0, xmm1, 00000010b": {
@@ -2028,14 +2028,14 @@
         "Map 3 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintp d4, d4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintp d2, d2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundsd xmm0, xmm1, 00000011b": {
@@ -2046,14 +2046,14 @@
         "Map 3 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frintz d4, d4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frintz d2, d2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vroundsd xmm0, xmm1, 00000100b": {
@@ -2064,14 +2064,14 @@
         "Map 3 0b01 0x0b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "frinti d4, d4",
-        "mov z5.d, p7/m, z16.d",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "frinti d2, d2",
+        "mov z3.d, p7/m, z16.d",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps xmm0, xmm1, xmm2, 0000b": {
@@ -2081,9 +2081,9 @@
         "Map 3 0b01 0x0c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps xmm0, xmm1, xmm2, 0001b": {
@@ -2093,19 +2093,19 @@
         "Map 3 0b01 0x0c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[0], v5.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[1]",
-        "mov v5.s[2], v4.s[2]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[3]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[0], v3.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[1]",
+        "mov v3.s[2], v2.s[2]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[3]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps xmm0, xmm1, xmm2, 1111b": {
@@ -2115,9 +2115,9 @@
         "Map 3 0b01 0x0c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps ymm0, ymm1, ymm2, 00000000b": {
@@ -2127,8 +2127,8 @@
         "Map 3 0b01 0x0c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps ymm0, ymm1, ymm2, 10000001b": {
@@ -2138,43 +2138,43 @@
         "Map 3 0b01 0x0c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.s, s5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.s, s3",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[1]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[1]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[2]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[2]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[3]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[3]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[4]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[4]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[5]",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[5]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z6.s, p0/m, z1.s",
-        "mov z1.s, z4.s[6]",
-        "mov z4.d, z6.d",
+        "mov z4.s, p0/m, z1.s",
+        "mov z1.s, z2.s[6]",
+        "mov z2.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, z5.s[7]",
+        "mov z2.s, p0/m, z1.s",
+        "mov z1.s, z3.s[7]",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendps ymm0, ymm1, ymm2, 11111111b": {
@@ -2184,8 +2184,8 @@
         "Map 3 0b01 0x0c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd xmm0, xmm1, xmm2, 00b": {
@@ -2195,9 +2195,9 @@
         "Map 3 0b01 0x0d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd xmm0, xmm1, xmm2, 01b": {
@@ -2207,17 +2207,17 @@
         "Map 3 0b01 0x0d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.d[0], v5.d[0]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[1]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.d[0], v3.d[0]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[1]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd xmm0, xmm1, xmm2, 10b": {
@@ -2227,15 +2227,15 @@
         "Map 3 0b01 0x0d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.d[1], v5.d[1]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.d[1], v3.d[1]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd xmm0, xmm1, xmm2, 11b": {
@@ -2245,9 +2245,9 @@
         "Map 3 0b01 0x0d 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0000b": {
@@ -2257,8 +2257,8 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0001b": {
@@ -2268,28 +2268,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
-        "mov z5.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0010b": {
@@ -2299,28 +2299,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0011b": {
@@ -2330,28 +2330,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0100b": {
@@ -2361,28 +2361,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0101b": {
@@ -2392,28 +2392,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0110b": {
@@ -2423,28 +2423,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 0111b": {
@@ -2454,28 +2454,28 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
-        "mov z5.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
+        "mov z3.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z5.d, p0/m, z1.d",
-        "mov z1.d, z4.d[3]",
-        "mov z4.d, z5.d",
+        "mov z3.d, p0/m, z1.d",
+        "mov z1.d, z2.d[3]",
+        "mov z2.d, z3.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1000b": {
@@ -2485,27 +2485,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1001b": {
@@ -2515,27 +2515,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1010b": {
@@ -2545,27 +2545,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1011b": {
@@ -2575,27 +2575,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[2]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[2]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1100b": {
@@ -2605,27 +2605,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1101b": {
@@ -2635,27 +2635,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d3",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z6.d, p0/m, z1.d",
-        "mov z1.d, z4.d[1]",
-        "mov z4.d, z6.d",
+        "mov z4.d, p0/m, z1.d",
+        "mov z1.d, z2.d[1]",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1110b": {
@@ -2665,27 +2665,27 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.d, d4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.d, d2",
+        "mov z2.d, z4.d",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-2",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[1]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[1]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #-1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[2]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[2]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #0",
-        "mov z4.d, p0/m, z1.d",
-        "mov z1.d, z5.d[3]",
+        "mov z2.d, p0/m, z1.d",
+        "mov z1.d, z3.d[3]",
         "index z0.d, #-2, #1",
         "cmpeq p0.d, p7/z, z0.d, #1",
-        "mov z4.d, p0/m, z1.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p0/m, z1.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendpd ymm0, ymm1, ymm2, 1111b": {
@@ -2695,8 +2695,8 @@
         "Map 3 0b01 0x0d 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw xmm0, xmm1, xmm2, 00000000b": {
@@ -2706,9 +2706,9 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw xmm0, xmm1, xmm2, 00000001b": {
@@ -2718,23 +2718,23 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov v0.16b, v6.16b",
-        "mov v0.h[0], v5.h[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.h[1], v4.h[1]",
-        "mov v5.h[2], v4.h[2]",
-        "mov v5.h[3], v4.h[3]",
-        "mov v5.h[4], v4.h[4]",
-        "mov v5.h[5], v4.h[5]",
-        "mov v5.h[6], v4.h[6]",
-        "mov v0.16b, v5.16b",
-        "mov v0.h[7], v4.h[7]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov v0.16b, v4.16b",
+        "mov v0.h[0], v3.h[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.h[1], v2.h[1]",
+        "mov v3.h[2], v2.h[2]",
+        "mov v3.h[3], v2.h[3]",
+        "mov v3.h[4], v2.h[4]",
+        "mov v3.h[5], v2.h[5]",
+        "mov v3.h[6], v2.h[6]",
+        "mov v0.16b, v3.16b",
+        "mov v0.h[7], v2.h[7]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw xmm0, xmm1, xmm2, 11111111b": {
@@ -2744,9 +2744,9 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw ymm0, ymm1, ymm2, 00000000b": {
@@ -2756,8 +2756,8 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw ymm0, ymm1, ymm2, 00000001b": {
@@ -2767,76 +2767,76 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.h, h5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.h, h3",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-8",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[1]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[1]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-7",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[2]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[2]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-6",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[3]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[3]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-5",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[4]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[4]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-4",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[5]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[5]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-3",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[6]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[6]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-2",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z4.h[7]",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z2.h[7]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #-1",
-        "mov z6.h, p0/m, z1.h",
-        "mov z1.h, z5.h[8]",
-        "mov z5.d, z6.d",
+        "mov z4.h, p0/m, z1.h",
+        "mov z1.h, z3.h[8]",
+        "mov z3.d, z4.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #0",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[9]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[9]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #1",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[10]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[10]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #2",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[11]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[11]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #3",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[12]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[12]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #4",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[13]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[13]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #5",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[14]",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[14]",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #6",
-        "mov z5.h, p0/m, z1.h",
-        "mov z1.h, z4.h[15]",
-        "mov z4.d, z5.d",
+        "mov z3.h, p0/m, z1.h",
+        "mov z1.h, z2.h[15]",
+        "mov z2.d, z3.d",
         "index z0.h, #-8, #1",
         "cmpeq p0.h, p7/z, z0.h, #7",
-        "mov z4.h, p0/m, z1.h",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.h, p0/m, z1.h",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendw ymm0, ymm1, ymm2, 11111111b": {
@@ -2846,8 +2846,8 @@
         "Map 3 0b01 0x0e 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z18.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr xmm0, xmm1, xmm2, 0": {
@@ -2857,11 +2857,11 @@
         "Map 3 0b01 0x0f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v4.16b, v5.16b, v4.16b, #0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v2.16b, v3.16b, v2.16b, #0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr xmm0, xmm1, xmm2, 1": {
@@ -2871,11 +2871,11 @@
         "Map 3 0b01 0x0f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v4.16b, v5.16b, v4.16b, #1",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v2.16b, v3.16b, v2.16b, #1",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr xmm0, xmm1, xmm2, 15": {
@@ -2885,11 +2885,11 @@
         "Map 3 0b01 0x0f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v4.16b, v5.16b, v4.16b, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v2.16b, v3.16b, v2.16b, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr xmm0, xmm1, xmm2, 16": {
@@ -2899,12 +2899,12 @@
         "Map 3 0b01 0x0f 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "movi v0.2d, #0x0",
-        "ext v4.16b, v4.16b, v0.16b, #0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "ext v2.16b, v2.16b, v0.16b, #0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr ymm0, ymm1, ymm2, 0": {
@@ -2914,19 +2914,19 @@
         "Map 3 0b01 0x0f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v6.16b, v5.16b, v4.16b, #0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "ext v4.16b, v5.16b, v4.16b, #0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v4.16b, v3.16b, v2.16b, #0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "ext v2.16b, v3.16b, v2.16b, #0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr ymm0, ymm1, ymm2, 1": {
@@ -2936,19 +2936,19 @@
         "Map 3 0b01 0x0f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v6.16b, v5.16b, v4.16b, #1",
-        "mov z1.q, z4.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "ext v4.16b, v5.16b, v4.16b, #1",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v4.16b, v3.16b, v2.16b, #1",
+        "mov z1.q, z2.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "ext v2.16b, v3.16b, v2.16b, #1",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr ymm0, ymm1, ymm2, 15": {
@@ -2958,19 +2958,19 @@
         "Map 3 0b01 0x0f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "ext v6.16b, v5.16b, v4.16b, #15",
-        "mov z1.q, z4.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "ext v4.16b, v5.16b, v4.16b, #15",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "ext v4.16b, v3.16b, v2.16b, #15",
+        "mov z1.q, z2.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "ext v2.16b, v3.16b, v2.16b, #15",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpalignr ymm0, ymm1, ymm2, 16": {
@@ -2980,21 +2980,21 @@
         "Map 3 0b01 0x0f 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "movi v0.2d, #0x0",
-        "ext v6.16b, v4.16b, v0.16b, #0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
-        "mov z5.b, p6/m, z1.b",
+        "ext v4.16b, v2.16b, v0.16b, #0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
+        "mov z3.b, p6/m, z1.b",
         "movi v0.2d, #0x0",
-        "ext v4.16b, v4.16b, v0.16b, #0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "ext v2.16b, v2.16b, v0.16b, #0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpextrb rax, xmm0, 0": {
@@ -3004,8 +3004,8 @@
         "Map 3 0b01 0x14 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.b[0]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.b[0]",
         "uxtb x4, w20"
       ]
     },
@@ -3016,8 +3016,8 @@
         "Map 3 0b01 0x14 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.b[15]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.b[15]",
         "uxtb x4, w20"
       ]
     },
@@ -3028,8 +3028,8 @@
         "Map 3 0b01 0x15 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.h[0]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.h[0]",
         "uxth x4, w20"
       ]
     },
@@ -3040,8 +3040,8 @@
         "Map 3 0b01 0x15 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "umov w20, v4.h[7]",
+        "mov z2.d, p7/m, z16.d",
+        "umov w20, v2.h[7]",
         "uxth x4, w20"
       ]
     },
@@ -3052,8 +3052,8 @@
         "Map 3 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov w4, v4.s[0]"
+        "mov z2.d, p7/m, z16.d",
+        "mov w4, v2.s[0]"
       ]
     },
     "vpextrd rax, xmm0, 3": {
@@ -3063,8 +3063,8 @@
         "Map 3 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov w4, v4.s[3]"
+        "mov z2.d, p7/m, z16.d",
+        "mov w4, v2.s[3]"
       ]
     },
     "vextractps eax, xmm0, 0": {
@@ -3074,8 +3074,8 @@
         "Map 3 0b01 0x17 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov w4, v4.s[0]"
+        "mov z2.d, p7/m, z16.d",
+        "mov w4, v2.s[0]"
       ]
     },
     "vextractps eax, xmm0, 3": {
@@ -3085,8 +3085,8 @@
         "Map 3 0b01 0x17 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z16.d",
-        "mov w4, v4.s[3]"
+        "mov z2.d, p7/m, z16.d",
+        "mov w4, v2.s[3]"
       ]
     },
     "vinsertf128 ymm0, ymm1, xmm2, 0": {
@@ -3096,11 +3096,11 @@
         "Map 3 0b01 0x18 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.q, q5",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.q, q3",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinsertf128 ymm0, ymm1, xmm2, 1": {
@@ -3110,12 +3110,12 @@
         "Map 3 0b01 0x18 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vextractf128 xmm0, ymm1, 0": {
@@ -3125,9 +3125,9 @@
         "Map 3 0b01 0x19 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vextractf128 xmm0, ymm1, 1": {
@@ -3137,10 +3137,10 @@
         "Map 3 0b01 0x19 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.q, z4.q[1]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.q, z2.q[1]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vcvtps2ph xmm0, xmm1, 00000000b": {
@@ -3242,10 +3242,10 @@
       ],
       "ExpectedArm64ASM": [
         "lsr w20, w4, #0",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.b[0], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.b[0], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrb xmm0, xmm1, eax, 15": {
@@ -3257,10 +3257,10 @@
       ],
       "ExpectedArm64ASM": [
         "lsr w20, w4, #0",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.b[15], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.b[15], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b0000))": {
@@ -3271,11 +3271,11 @@
         "Map 3 0b01 0x21 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.s[0], v5.s[0]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.s[0], v3.s[0]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b1111))": {
@@ -3286,9 +3286,9 @@
         "Map 3 0b01 0x21 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinsertps xmm0, xmm1, xmm2, ((0b11 << 6) | (0b11 << 4) | (0b0000))": {
@@ -3299,11 +3299,11 @@
         "Map 3 0b01 0x21 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov v4.s[3], v5.s[3]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov v2.s[3], v3.s[3]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrd xmm0, xmm1, eax, 0": {
@@ -3315,10 +3315,10 @@
       ],
       "ExpectedArm64ASM": [
         "lsr w20, w4, #0",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.s[0], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.s[0], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrd xmm0, xmm1, eax, 3": {
@@ -3330,10 +3330,10 @@
       ],
       "ExpectedArm64ASM": [
         "lsr w20, w4, #0",
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.s[3], w20",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.s[3], w20",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrq xmm0, xmm1, rax, 0": {
@@ -3344,10 +3344,10 @@
         "Map 3 0b01 0x22 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.d[0], x4",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.d[0], x4",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpinsrq xmm0, xmm1, rax, 1": {
@@ -3358,10 +3358,10 @@
         "Map 3 0b01 0x22 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.d[1], x4",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.d[1], x4",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinserti128 ymm0, ymm1, xmm2, 0": {
@@ -3371,11 +3371,11 @@
         "Map 3 0b01 0x38 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.q, q5",
-        "mov z4.b, p6/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.q, q3",
+        "mov z2.b, p6/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vinserti128 ymm0, ymm1, xmm2, 1": {
@@ -3385,12 +3385,12 @@
         "Map 3 0b01 0x38 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vextracti128 xmm0, ymm1, 0": {
@@ -3400,9 +3400,9 @@
         "Map 3 0b01 0x39 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vextracti128 xmm0, ymm1, 1": {
@@ -3412,10 +3412,10 @@
         "Map 3 0b01 0x39 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z4.q, z4.q[1]",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z2.q, z2.q[1]",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps xmm0, xmm1, xmm2, 00000000b": {
@@ -3425,9 +3425,9 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps xmm0, xmm1, xmm2, 00001111b": {
@@ -3437,26 +3437,26 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul v4.4s, v4.4s, v5.4s",
-        "mov v4.s[0], v6.s[0]",
-        "mov v4.s[1], v6.s[0]",
-        "mov v4.s[2], v6.s[0]",
-        "mov v4.s[3], v6.s[0]",
-        "faddp v4.4s, v4.4s, v6.4s",
-        "faddp v4.4s, v4.4s, v6.4s",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul v2.4s, v2.4s, v3.4s",
+        "mov v2.s[0], v4.s[0]",
+        "mov v2.s[1], v4.s[0]",
+        "mov v2.s[2], v4.s[0]",
+        "mov v2.s[3], v4.s[0]",
+        "faddp v2.4s, v2.4s, v4.4s",
+        "faddp v2.4s, v2.4s, v4.4s",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps xmm0, xmm1, xmm2, 11110000b": {
@@ -3466,9 +3466,9 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps xmm0, xmm1, xmm2, 11111111b": {
@@ -3478,22 +3478,22 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul v4.4s, v4.4s, v5.4s",
-        "faddp v4.4s, v4.4s, v6.4s",
-        "faddp v4.4s, v4.4s, v6.4s",
-        "mov v0.16b, v6.16b",
-        "mov v0.s[0], v4.s[0]",
-        "mov v5.16b, v0.16b",
-        "mov v5.s[1], v4.s[0]",
-        "mov v5.s[2], v4.s[0]",
-        "mov v0.16b, v5.16b",
-        "mov v0.s[3], v4.s[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul v2.4s, v2.4s, v3.4s",
+        "faddp v2.4s, v2.4s, v4.4s",
+        "faddp v2.4s, v2.4s, v4.4s",
+        "mov v0.16b, v4.16b",
+        "mov v0.s[0], v2.s[0]",
+        "mov v3.16b, v0.16b",
+        "mov v3.s[1], v2.s[0]",
+        "mov v3.s[2], v2.s[0]",
+        "mov v0.16b, v3.16b",
+        "mov v0.s[3], v2.s[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps ymm0, ymm1, ymm2, 00000000b": {
@@ -3503,8 +3503,8 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps ymm0, ymm1, ymm2, 00001111b": {
@@ -3514,87 +3514,87 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul z4.s, z4.s, z5.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z4.s, p0/m, z1.s",
-        "mov z1.s, s6",
-        "index z0.s, #-4, #1",
-        "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "movprfx z0, z4",
-        "faddp z0.s, p7/m, z0.s, z6.s",
-        "uzp1 z4.s, z0.s, z0.s",
-        "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "movprfx z0, z4",
-        "faddp z0.s, p7/m, z0.s, z6.s",
-        "uzp1 z4.s, z0.s, z0.s",
-        "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul z2.s, z2.s, z3.s",
         "mov z1.s, s4",
-        "mov z5.d, z6.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
+        "mov z2.s, p0/m, z1.s",
         "mov z1.s, s4",
-        "mov z4.d, z5.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "movprfx z0, z2",
+        "faddp z0.s, p7/m, z0.s, z4.s",
+        "uzp1 z2.s, z0.s, z0.s",
+        "uzp2 z1.s, z0.s, z0.s",
+        "splice z2.d, p6, z2.d, z1.d",
+        "movprfx z0, z2",
+        "faddp z0.s, p7/m, z0.s, z4.s",
+        "uzp1 z2.s, z0.s, z0.s",
+        "uzp2 z1.s, z0.s, z0.s",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.s, s2",
+        "mov z3.d, z4.d",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #-4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #-3",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #-2",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #-1",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #0",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #1",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #2",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "mov z2.d, z3.d",
+        "index z0.s, #-4, #1",
+        "cmpeq p0.s, p7/z, z0.s, #3",
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps ymm0, ymm1, ymm2, 11110000b": {
@@ -3604,8 +3604,8 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdpps ymm0, ymm1, ymm2, 11111111b": {
@@ -3615,55 +3615,55 @@
         "Map 3 0b01 0x40 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul z4.s, z4.s, z5.s",
-        "movprfx z0, z4",
-        "faddp z0.s, p7/m, z0.s, z6.s",
-        "uzp1 z4.s, z0.s, z0.s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul z2.s, z2.s, z3.s",
+        "movprfx z0, z2",
+        "faddp z0.s, p7/m, z0.s, z4.s",
+        "uzp1 z2.s, z0.s, z0.s",
         "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "movprfx z0, z4",
-        "faddp z0.s, p7/m, z0.s, z6.s",
-        "uzp1 z4.s, z0.s, z0.s",
+        "splice z2.d, p6, z2.d, z1.d",
+        "movprfx z0, z2",
+        "faddp z0.s, p7/m, z0.s, z4.s",
+        "uzp1 z2.s, z0.s, z0.s",
         "uzp2 z1.s, z0.s, z0.s",
-        "splice z4.d, p6, z4.d, z1.d",
-        "mov z1.s, s4",
-        "mov z5.d, z6.d",
+        "splice z2.d, p6, z2.d, z1.d",
+        "mov z1.s, s2",
+        "mov z3.d, z4.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-4",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-3",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #-1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #0",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #1",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #2",
-        "mov z5.s, p0/m, z1.s",
-        "mov z1.s, s4",
-        "mov z4.d, z5.d",
+        "mov z3.s, p0/m, z1.s",
+        "mov z1.s, s2",
+        "mov z2.d, z3.d",
         "index z0.s, #-4, #1",
         "cmpeq p0.s, p7/z, z0.s, #3",
-        "mov z4.s, p0/m, z1.s",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.s, p0/m, z1.s",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdppd xmm0, xmm1, xmm2, 00000000b": {
@@ -3673,9 +3673,9 @@
         "Map 3 0b01 0x41 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdppd xmm0, xmm1, xmm2, 00001111b": {
@@ -3685,21 +3685,21 @@
         "Map 3 0b01 0x41 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul v4.2d, v4.2d, v5.2d",
-        "mov v4.d[0], v6.d[0]",
-        "mov v4.d[1], v6.d[0]",
-        "faddp v4.2d, v4.2d, v6.2d",
-        "mov v0.16b, v6.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul v2.2d, v2.2d, v3.2d",
+        "mov v2.d[0], v4.d[0]",
+        "mov v2.d[1], v4.d[0]",
+        "faddp v2.2d, v2.2d, v4.2d",
+        "mov v0.16b, v4.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdppd xmm0, xmm1, xmm2, 11110000b": {
@@ -3709,9 +3709,9 @@
         "Map 3 0b01 0x41 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vdppd xmm0, xmm1, xmm2, 11111111b": {
@@ -3721,19 +3721,19 @@
         "Map 3 0b01 0x41 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "fmul v4.2d, v4.2d, v5.2d",
-        "faddp v4.2d, v4.2d, v6.2d",
-        "mov v0.16b, v6.16b",
-        "mov v0.d[0], v4.d[0]",
-        "mov v5.16b, v0.16b",
-        "mov v0.16b, v5.16b",
-        "mov v0.d[1], v4.d[0]",
-        "mov v4.16b, v0.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "fmul v2.2d, v2.2d, v3.2d",
+        "faddp v2.2d, v2.2d, v4.2d",
+        "mov v0.16b, v4.16b",
+        "mov v0.d[0], v2.d[0]",
+        "mov v3.16b, v0.16b",
+        "mov v0.16b, v3.16b",
+        "mov v0.d[1], v2.d[0]",
+        "mov v2.16b, v0.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 000b": {
@@ -3743,24 +3743,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[0]",
-        "ext v6.16b, v4.16b, v4.16b, #0",
-        "ext v7.16b, v4.16b, v4.16b, #1",
-        "ext v8.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[0]",
+        "ext v4.16b, v2.16b, v2.16b, #0",
+        "ext v5.16b, v2.16b, v2.16b, #1",
+        "ext v6.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 001b": {
@@ -3770,24 +3770,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[1]",
-        "ext v6.16b, v4.16b, v4.16b, #0",
-        "ext v7.16b, v4.16b, v4.16b, #1",
-        "ext v8.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[1]",
+        "ext v4.16b, v2.16b, v2.16b, #0",
+        "ext v5.16b, v2.16b, v2.16b, #1",
+        "ext v6.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 010b": {
@@ -3797,24 +3797,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[2]",
-        "ext v6.16b, v4.16b, v4.16b, #0",
-        "ext v7.16b, v4.16b, v4.16b, #1",
-        "ext v8.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[2]",
+        "ext v4.16b, v2.16b, v2.16b, #0",
+        "ext v5.16b, v2.16b, v2.16b, #1",
+        "ext v6.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 011b": {
@@ -3824,24 +3824,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[3]",
-        "ext v6.16b, v4.16b, v4.16b, #0",
-        "ext v7.16b, v4.16b, v4.16b, #1",
-        "ext v8.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[3]",
+        "ext v4.16b, v2.16b, v2.16b, #0",
+        "ext v5.16b, v2.16b, v2.16b, #1",
+        "ext v6.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 100b": {
@@ -3851,24 +3851,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[0]",
-        "ext v6.16b, v4.16b, v4.16b, #4",
-        "ext v7.16b, v4.16b, v4.16b, #5",
-        "ext v8.16b, v4.16b, v4.16b, #6",
-        "ext v4.16b, v4.16b, v4.16b, #7",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[0]",
+        "ext v4.16b, v2.16b, v2.16b, #4",
+        "ext v5.16b, v2.16b, v2.16b, #5",
+        "ext v6.16b, v2.16b, v2.16b, #6",
+        "ext v2.16b, v2.16b, v2.16b, #7",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 101b": {
@@ -3878,24 +3878,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[1]",
-        "ext v6.16b, v4.16b, v4.16b, #4",
-        "ext v7.16b, v4.16b, v4.16b, #5",
-        "ext v8.16b, v4.16b, v4.16b, #6",
-        "ext v4.16b, v4.16b, v4.16b, #7",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[1]",
+        "ext v4.16b, v2.16b, v2.16b, #4",
+        "ext v5.16b, v2.16b, v2.16b, #5",
+        "ext v6.16b, v2.16b, v2.16b, #6",
+        "ext v2.16b, v2.16b, v2.16b, #7",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 110b": {
@@ -3905,24 +3905,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[2]",
-        "ext v6.16b, v4.16b, v4.16b, #4",
-        "ext v7.16b, v4.16b, v4.16b, #5",
-        "ext v8.16b, v4.16b, v4.16b, #6",
-        "ext v4.16b, v4.16b, v4.16b, #7",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[2]",
+        "ext v4.16b, v2.16b, v2.16b, #4",
+        "ext v5.16b, v2.16b, v2.16b, #5",
+        "ext v6.16b, v2.16b, v2.16b, #6",
+        "ext v2.16b, v2.16b, v2.16b, #7",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw xmm0, xmm1, xmm2, 111b": {
@@ -3932,24 +3932,24 @@
         "Map 3 0b01 0x42 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v5.4s, v5.s[3]",
-        "ext v6.16b, v4.16b, v4.16b, #4",
-        "ext v7.16b, v4.16b, v4.16b, #5",
-        "ext v8.16b, v4.16b, v4.16b, #6",
-        "ext v4.16b, v4.16b, v4.16b, #7",
-        "uabdl v6.8h, v6.8b, v5.8b",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v6.8h, v8.8h",
-        "addp v4.8h, v7.8h, v4.8h",
-        "trn1 v6.4s, v5.4s, v4.4s",
-        "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v6.8h, v4.8h",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v3.4s, v3.s[3]",
+        "ext v4.16b, v2.16b, v2.16b, #4",
+        "ext v5.16b, v2.16b, v2.16b, #5",
+        "ext v6.16b, v2.16b, v2.16b, #6",
+        "ext v2.16b, v2.16b, v2.16b, #7",
+        "uabdl v4.8h, v4.8b, v3.8b",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v4.8h, v6.8h",
+        "addp v2.8h, v5.8h, v2.8h",
+        "trn1 v4.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v4.8h, v2.8h",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 000b": {
@@ -3959,43 +3959,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v10.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v8.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 001b": {
@@ -4005,43 +4005,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[1]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v10.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[1]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v8.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 010b": {
@@ -4051,43 +4051,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[2]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v10.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[2]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v8.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 011b": {
@@ -4097,43 +4097,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[3]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v10.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[3]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v8.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 100b": {
@@ -4143,43 +4143,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #4",
-        "ext v8.16b, v4.16b, v4.16b, #5",
-        "ext v9.16b, v4.16b, v4.16b, #6",
-        "ext v10.16b, v4.16b, v4.16b, #7",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #4",
+        "ext v6.16b, v2.16b, v2.16b, #5",
+        "ext v7.16b, v2.16b, v2.16b, #6",
+        "ext v8.16b, v2.16b, v2.16b, #7",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 101b": {
@@ -4189,43 +4189,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[1]",
-        "ext v7.16b, v4.16b, v4.16b, #4",
-        "ext v8.16b, v4.16b, v4.16b, #5",
-        "ext v9.16b, v4.16b, v4.16b, #6",
-        "ext v10.16b, v4.16b, v4.16b, #7",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[1]",
+        "ext v5.16b, v2.16b, v2.16b, #4",
+        "ext v6.16b, v2.16b, v2.16b, #5",
+        "ext v7.16b, v2.16b, v2.16b, #6",
+        "ext v8.16b, v2.16b, v2.16b, #7",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 110b": {
@@ -4235,43 +4235,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[2]",
-        "ext v7.16b, v4.16b, v4.16b, #4",
-        "ext v8.16b, v4.16b, v4.16b, #5",
-        "ext v9.16b, v4.16b, v4.16b, #6",
-        "ext v10.16b, v4.16b, v4.16b, #7",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[2]",
+        "ext v5.16b, v2.16b, v2.16b, #4",
+        "ext v6.16b, v2.16b, v2.16b, #5",
+        "ext v7.16b, v2.16b, v2.16b, #6",
+        "ext v8.16b, v2.16b, v2.16b, #7",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vmpsadbw ymm0, ymm1, ymm2, 111b": {
@@ -4281,43 +4281,43 @@
         "Map 3 0b01 0x42 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v6.4s, v5.s[3]",
-        "ext v7.16b, v4.16b, v4.16b, #4",
-        "ext v8.16b, v4.16b, v4.16b, #5",
-        "ext v9.16b, v4.16b, v4.16b, #6",
-        "ext v10.16b, v4.16b, v4.16b, #7",
-        "uabdl v7.8h, v7.8b, v6.8b",
-        "uabdl v8.8h, v8.8b, v6.8b",
-        "uabdl v9.8h, v9.8b, v6.8b",
-        "uabdl v6.8h, v10.8b, v6.8b",
-        "addp v7.8h, v7.8h, v9.8h",
-        "addp v6.8h, v8.8h, v6.8h",
-        "trn1 v8.4s, v7.4s, v6.4s",
-        "trn2 v6.4s, v7.4s, v6.4s",
-        "addp v6.8h, v8.8h, v6.8h",
-        "mov z4.q, z4.q[1]",
-        "mov z5.q, z5.q[1]",
-        "dup v5.4s, v5.s[0]",
-        "ext v7.16b, v4.16b, v4.16b, #0",
-        "ext v8.16b, v4.16b, v4.16b, #1",
-        "ext v9.16b, v4.16b, v4.16b, #2",
-        "ext v4.16b, v4.16b, v4.16b, #3",
-        "uabdl v7.8h, v7.8b, v5.8b",
-        "uabdl v8.8h, v8.8b, v5.8b",
-        "uabdl v9.8h, v9.8b, v5.8b",
-        "uabdl v4.8h, v4.8b, v5.8b",
-        "addp v5.8h, v7.8h, v9.8h",
-        "addp v4.8h, v8.8h, v4.8h",
-        "trn1 v7.4s, v5.4s, v4.4s",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v4.4s, v3.s[3]",
+        "ext v5.16b, v2.16b, v2.16b, #4",
+        "ext v6.16b, v2.16b, v2.16b, #5",
+        "ext v7.16b, v2.16b, v2.16b, #6",
+        "ext v8.16b, v2.16b, v2.16b, #7",
+        "uabdl v5.8h, v5.8b, v4.8b",
+        "uabdl v6.8h, v6.8b, v4.8b",
+        "uabdl v7.8h, v7.8b, v4.8b",
+        "uabdl v4.8h, v8.8b, v4.8b",
+        "addp v5.8h, v5.8h, v7.8h",
+        "addp v4.8h, v6.8h, v4.8h",
+        "trn1 v6.4s, v5.4s, v4.4s",
         "trn2 v4.4s, v5.4s, v4.4s",
-        "addp v4.8h, v7.8h, v4.8h",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "addp v4.8h, v6.8h, v4.8h",
+        "mov z2.q, z2.q[1]",
+        "mov z3.q, z3.q[1]",
+        "dup v3.4s, v3.s[0]",
+        "ext v5.16b, v2.16b, v2.16b, #0",
+        "ext v6.16b, v2.16b, v2.16b, #1",
+        "ext v7.16b, v2.16b, v2.16b, #2",
+        "ext v2.16b, v2.16b, v2.16b, #3",
+        "uabdl v5.8h, v5.8b, v3.8b",
+        "uabdl v6.8h, v6.8b, v3.8b",
+        "uabdl v7.8h, v7.8b, v3.8b",
+        "uabdl v2.8h, v2.8b, v3.8b",
+        "addp v3.8h, v5.8h, v7.8h",
+        "addp v2.8h, v6.8h, v2.8h",
+        "trn1 v5.4s, v3.4s, v2.4s",
+        "trn2 v2.4s, v3.4s, v2.4s",
+        "addp v2.8h, v5.8h, v2.8h",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpclmulqdq xmm0, xmm1, xmm2, 00000b": {
@@ -4327,11 +4327,11 @@
         "Map 3 0b01 0x44 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "unallocated (Unallocated)",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpclmulqdq xmm0, xmm1, xmm2, 00001b": {
@@ -4341,12 +4341,12 @@
         "Map 3 0b01 0x44 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v0.2d, v4.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v0.2d, v2.d[1]",
         "unallocated (Unallocated)",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpclmulqdq xmm0, xmm1, xmm2, 10000b": {
@@ -4356,12 +4356,12 @@
         "Map 3 0b01 0x44 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "dup v0.2d, v5.d[1]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "dup v0.2d, v3.d[1]",
         "unallocated (Unallocated)",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpclmulqdq xmm0, xmm1, xmm2, 10001b": {
@@ -4371,11 +4371,11 @@
         "Map 3 0b01 0x44 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
         "unallocated (Unallocated)",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpclmulqdq ymm0, ymm1, ymm2, 00000b": {
@@ -4417,15 +4417,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 01b": {
@@ -4435,15 +4435,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 10b": {
@@ -4453,17 +4453,17 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q5",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q3",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 11b": {
@@ -4473,17 +4473,17 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z5.q[1]",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z3.q[1]",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 010000b": {
@@ -4493,15 +4493,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 010001b": {
@@ -4511,15 +4511,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 010010b": {
@@ -4529,17 +4529,17 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q5",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q3",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 010011b": {
@@ -4549,17 +4549,17 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z5.q[1]",
-        "mov z5.d, z6.d",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z3.q[1]",
+        "mov z3.d, z4.d",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 100000b": {
@@ -4569,16 +4569,16 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 100001b": {
@@ -4588,16 +4588,16 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, q5",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, q3",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 100010b": {
@@ -4607,15 +4607,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z18.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 100011b": {
@@ -4625,15 +4625,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, q4",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z18.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, q2",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 110000b": {
@@ -4643,16 +4643,16 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 110001b": {
@@ -4662,16 +4662,16 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "movi v6.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z6.d",
-        "mov z4.b, p6/m, z1.b",
-        "mov z1.q, z5.q[1]",
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "movi v4.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z4.d",
+        "mov z2.b, p6/m, z1.b",
+        "mov z1.q, z3.q[1]",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 110010b": {
@@ -4681,15 +4681,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, q4",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z18.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, q2",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vperm2i128 ymm0, ymm1, ymm2, 110011b": {
@@ -4699,15 +4699,15 @@
         "Map 3 0b01 0x46 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z18.d",
-        "movi v5.2d, #0x0",
-        "mov z1.q, z4.q[1]",
-        "mov z5.b, p6/m, z1.b",
-        "mov z1.q, z4.q[1]",
-        "mov z4.d, z5.d",
+        "mov z2.d, p7/m, z18.d",
+        "movi v3.2d, #0x0",
+        "mov z1.q, z2.q[1]",
+        "mov z3.b, p6/m, z1.b",
+        "mov z1.q, z2.q[1]",
+        "mov z2.d, z3.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendvps xmm0, xmm1, xmm2, xmm3": {
@@ -4717,13 +4717,13 @@
         "Map 3 0b01 0x4a 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "sshr v6.4s, v6.4s, #31",
-        "bit v4.16b, v5.16b, v6.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "sshr v4.4s, v4.4s, #31",
+        "bit v2.16b, v3.16b, v4.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendvps ymm0, ymm1, ymm2, ymm3": {
@@ -4733,14 +4733,14 @@
         "Map 3 0b01 0x4a 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "asr z6.s, p7/m, z6.s, #31",
-        "movprfx z0, z5",
-        "bsl z0.d, z0.d, z4.d, z6.d",
-        "mov z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "asr z4.s, p7/m, z4.s, #31",
+        "movprfx z0, z3",
+        "bsl z0.d, z0.d, z2.d, z4.d",
+        "mov z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendvpd xmm0, xmm1, xmm2, xmm3": {
@@ -4750,13 +4750,13 @@
         "Map 3 0b01 0x4b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "sshr v6.2d, v6.2d, #63",
-        "bit v4.16b, v5.16b, v6.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "sshr v4.2d, v4.2d, #63",
+        "bit v2.16b, v3.16b, v4.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vblendvpd ymm0, ymm1, ymm2, ymm3": {
@@ -4766,14 +4766,14 @@
         "Map 3 0b01 0x4b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "asr z6.d, p7/m, z6.d, #63",
-        "movprfx z0, z5",
-        "bsl z0.d, z0.d, z4.d, z6.d",
-        "mov z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "asr z4.d, p7/m, z4.d, #63",
+        "movprfx z0, z3",
+        "bsl z0.d, z0.d, z2.d, z4.d",
+        "mov z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendvb xmm0, xmm1, xmm2, xmm3": {
@@ -4783,13 +4783,13 @@
         "Map 3 0b01 0x4c 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "sshr v6.16b, v6.16b, #7",
-        "bit v4.16b, v5.16b, v6.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "sshr v4.16b, v4.16b, #7",
+        "bit v2.16b, v3.16b, v4.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpblendvb ymm0, ymm1, ymm2, ymm3": {
@@ -4799,14 +4799,14 @@
         "Map 3 0b01 0x4c 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z5.d, p7/m, z18.d",
-        "mov z6.d, p7/m, z19.d",
-        "asr z6.b, p7/m, z6.b, #7",
-        "movprfx z0, z5",
-        "bsl z0.d, z0.d, z4.d, z6.d",
-        "mov z4.d, z0.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z3.d, p7/m, z18.d",
+        "mov z4.d, p7/m, z19.d",
+        "asr z4.b, p7/m, z4.b, #7",
+        "movprfx z0, z3",
+        "bsl z0.d, z0.d, z2.d, z4.d",
+        "mov z2.d, z0.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
@@ -5056,14 +5056,14 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "ldr x0, [x28, #1608]",
-        "ldr q5, [x0]",
-        "movi v6.2d, #0x0",
+        "ldr q3, [x0]",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
-        "tbl v4.16b, {v4.16b}, v5.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "tbl v2.16b, {v2.16b}, v3.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vaeskeygenassist xmm0, xmm1, 0xFF": {
@@ -5073,17 +5073,17 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
+        "mov z2.d, p7/m, z17.d",
         "ldr x0, [x28, #1608]",
-        "ldr q5, [x0]",
-        "movi v6.2d, #0x0",
+        "ldr q3, [x0]",
+        "movi v4.2d, #0x0",
         "unimplemented (Unimplemented)",
-        "tbl v4.16b, {v4.16b}, v5.16b",
+        "tbl v2.16b, {v2.16b}, v3.16b",
         "mov x0, #0xff00000000",
         "dup v1.2d, x0",
-        "eor v4.16b, v4.16b, v1.16b",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "eor v2.16b, v2.16b, v1.16b",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "rorx eax, ebx, 0": {
diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json
index ac216af87..314751ac1 100644
--- a/unittests/InstructionCountCI/VEX_map_group.json
+++ b/unittests/InstructionCountCI/VEX_map_group.json
@@ -14,9 +14,9 @@
         "Map group 12 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw xmm0, xmm1, 15": {
@@ -26,10 +26,10 @@
         "Map group 12 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ushr v4.8h, v4.8h, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ushr v2.8h, v2.8h, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw xmm0, xmm1, 16": {
@@ -39,10 +39,10 @@
         "Map group 12 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw ymm0, ymm1, 0": {
@@ -52,8 +52,8 @@
         "Map group 12 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw ymm0, ymm1, 15": {
@@ -63,9 +63,9 @@
         "Map group 12 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsr z4.h, p7/m, z4.h, #15",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsr z2.h, p7/m, z2.h, #15",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlw ymm0, ymm1, 16": {
@@ -75,9 +75,9 @@
         "Map group 12 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw xmm0, xmm1, 0": {
@@ -87,9 +87,9 @@
         "Map group 12 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw xmm0, xmm1, 15": {
@@ -99,10 +99,10 @@
         "Map group 12 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sshr v4.8h, v4.8h, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sshr v2.8h, v2.8h, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw xmm0, xmm1, 16": {
@@ -112,10 +112,10 @@
         "Map group 12 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sshr v4.8h, v4.8h, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sshr v2.8h, v2.8h, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw ymm0, ymm1, 0": {
@@ -125,8 +125,8 @@
         "Map group 12 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw ymm0, ymm1, 15": {
@@ -136,9 +136,9 @@
         "Map group 12 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "asr z4.h, p7/m, z4.h, #15",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "asr z2.h, p7/m, z2.h, #15",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsraw ymm0, ymm1, 16": {
@@ -148,9 +148,9 @@
         "Map group 12 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "asr z4.h, p7/m, z4.h, #15",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "asr z2.h, p7/m, z2.h, #15",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw xmm0, xmm1, 0": {
@@ -160,9 +160,9 @@
         "Map group 12 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw xmm0, xmm1, 15": {
@@ -172,10 +172,10 @@
         "Map group 12 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "shl v4.8h, v4.8h, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "shl v2.8h, v2.8h, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw xmm0, xmm1, 16": {
@@ -185,10 +185,10 @@
         "Map group 12 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw ymm0, ymm1, 0": {
@@ -198,8 +198,8 @@
         "Map group 12 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw ymm0, ymm1, 15": {
@@ -209,9 +209,9 @@
         "Map group 12 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsl z4.h, p7/m, z4.h, #15",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsl z2.h, p7/m, z2.h, #15",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllw ymm0, ymm1, 16": {
@@ -221,9 +221,9 @@
         "Map group 12 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld xmm0, xmm1, 0": {
@@ -233,9 +233,9 @@
         "Map group 13 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld xmm0, xmm1, 31": {
@@ -245,10 +245,10 @@
         "Map group 13 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ushr v4.4s, v4.4s, #31",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ushr v2.4s, v2.4s, #31",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld xmm0, xmm1, 32": {
@@ -258,10 +258,10 @@
         "Map group 13 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld ymm0, ymm1, 0": {
@@ -271,8 +271,8 @@
         "Map group 13 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld ymm0, ymm1, 31": {
@@ -282,9 +282,9 @@
         "Map group 13 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsr z4.s, p7/m, z4.s, #31",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsr z2.s, p7/m, z2.s, #31",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrld ymm0, ymm1, 32": {
@@ -294,9 +294,9 @@
         "Map group 13 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad xmm0, xmm1, 0": {
@@ -306,9 +306,9 @@
         "Map group 13 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad xmm0, xmm1, 31": {
@@ -318,10 +318,10 @@
         "Map group 13 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sshr v4.4s, v4.4s, #31",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sshr v2.4s, v2.4s, #31",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad xmm0, xmm1, 32": {
@@ -331,10 +331,10 @@
         "Map group 13 0b100 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "sshr v4.4s, v4.4s, #31",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "sshr v2.4s, v2.4s, #31",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad ymm0, ymm1, 0": {
@@ -344,8 +344,8 @@
         "Map group 13 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad ymm0, ymm1, 31": {
@@ -355,9 +355,9 @@
         "Map group 13 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "asr z4.s, p7/m, z4.s, #31",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "asr z2.s, p7/m, z2.s, #31",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrad ymm0, ymm1, 32": {
@@ -367,9 +367,9 @@
         "Map group 13 0b100 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "asr z4.s, p7/m, z4.s, #31",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "asr z2.s, p7/m, z2.s, #31",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld xmm0, xmm1, 0": {
@@ -379,9 +379,9 @@
         "Map group 13 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld xmm0, xmm1, 31": {
@@ -391,10 +391,10 @@
         "Map group 13 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "shl v4.4s, v4.4s, #31",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "shl v2.4s, v2.4s, #31",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld xmm0, xmm1, 32": {
@@ -404,10 +404,10 @@
         "Map group 13 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld ymm0, ymm1, 0": {
@@ -417,8 +417,8 @@
         "Map group 13 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld ymm0, ymm1, 31": {
@@ -428,9 +428,9 @@
         "Map group 13 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsl z4.s, p7/m, z4.s, #31",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsl z2.s, p7/m, z2.s, #31",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslld ymm0, ymm1, 32": {
@@ -440,9 +440,9 @@
         "Map group 13 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq xmm0, xmm1, 0": {
@@ -452,9 +452,9 @@
         "Map group 14 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq xmm0, xmm1, 63": {
@@ -464,10 +464,10 @@
         "Map group 14 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "ushr v4.2d, v4.2d, #63",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "ushr v2.2d, v2.2d, #63",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq xmm0, xmm1, 64": {
@@ -477,10 +477,10 @@
         "Map group 14 0b010 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq ymm0, ymm1, 0": {
@@ -490,8 +490,8 @@
         "Map group 14 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq ymm0, ymm1, 63": {
@@ -501,9 +501,9 @@
         "Map group 14 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsr z4.d, p7/m, z4.d, #63",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsr z2.d, p7/m, z2.d, #63",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrlq ymm0, ymm1, 64": {
@@ -513,9 +513,9 @@
         "Map group 14 0b010 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq xmm0, xmm1, 0": {
@@ -525,9 +525,9 @@
         "Map group 14 0b011 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq xmm0, xmm1, 15": {
@@ -537,11 +537,11 @@
         "Map group 14 0b011 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "ext v4.16b, v4.16b, v5.16b, #15",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "ext v2.16b, v2.16b, v3.16b, #15",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq xmm0, xmm1, 16": {
@@ -551,9 +551,9 @@
         "Map group 14 0b011 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq ymm0, ymm1, 0": {
@@ -563,8 +563,8 @@
         "Map group 14 0b011 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq ymm0, ymm1, 15": {
@@ -574,15 +574,15 @@
         "Map group 14 0b011 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "ext v6.16b, v4.16b, v5.16b, #15",
-        "ext z4.b, z4.b, z5.b, #31",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "ext v4.16b, v2.16b, v3.16b, #15",
+        "ext z2.b, z2.b, z3.b, #31",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsrldq ymm0, ymm1, 16": {
@@ -592,8 +592,8 @@
         "Map group 14 0b011 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq xmm0, xmm1, 0": {
@@ -603,9 +603,9 @@
         "Map group 14 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq xmm0, xmm1, 63": {
@@ -615,10 +615,10 @@
         "Map group 14 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "shl v4.2d, v4.2d, #63",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "shl v2.2d, v2.2d, #63",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq xmm0, xmm1, 64": {
@@ -628,10 +628,10 @@
         "Map group 14 0b110 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq ymm0, ymm1, 0": {
@@ -641,8 +641,8 @@
         "Map group 14 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq ymm0, ymm1, 63": {
@@ -652,9 +652,9 @@
         "Map group 14 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "lsl z4.d, p7/m, z4.d, #63",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "lsl z2.d, p7/m, z2.d, #63",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpsllq ymm0, ymm1, 64": {
@@ -664,9 +664,9 @@
         "Map group 14 0b110 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq xmm0, xmm1, 0": {
@@ -676,9 +676,9 @@
         "Map group 14 0b111 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq xmm0, xmm1, 15": {
@@ -688,11 +688,11 @@
         "Map group 14 0b111 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "ext v4.16b, v5.16b, v4.16b, #1",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "ext v2.16b, v3.16b, v2.16b, #1",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq xmm0, xmm1, 16": {
@@ -702,9 +702,9 @@
         "Map group 14 0b111 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov v4.16b, v4.16b",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov v2.16b, v2.16b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq ymm0, ymm1, 0": {
@@ -714,8 +714,8 @@
         "Map group 14 0b111 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.d, p7/m, z17.d",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq ymm0, ymm1, 15": {
@@ -725,17 +725,17 @@
         "Map group 14 0b111 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov z4.d, p7/m, z17.d",
-        "movi v5.2d, #0x0",
-        "ext v6.16b, v5.16b, v4.16b, #1",
-        "movprfx z1, z5",
-        "ext z1.b, z1.b, z4.b, #17",
-        "mov z4.d, z1.d",
-        "mov z1.q, q4",
-        "mov z4.d, z6.d",
+        "mov z2.d, p7/m, z17.d",
+        "movi v3.2d, #0x0",
+        "ext v4.16b, v3.16b, v2.16b, #1",
+        "movprfx z1, z3",
+        "ext z1.b, z1.b, z2.b, #17",
+        "mov z2.d, z1.d",
+        "mov z1.q, q2",
+        "mov z2.d, z4.d",
         "not p0.b, p7/z, p6.b",
-        "mov z4.b, p0/m, z1.b",
-        "mov z16.d, p7/m, z4.d"
+        "mov z2.b, p0/m, z1.b",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vpslldq ymm0, ymm1, 16": {
@@ -745,8 +745,8 @@
         "Map group 14 0b111 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "movi v4.2d, #0x0",
-        "mov z16.d, p7/m, z4.d"
+        "movi v2.2d, #0x0",
+        "mov z16.d, p7/m, z2.d"
       ]
     },
     "vldmxcsr [rax]": {
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index d1e5aa567..f120abff6 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -9,14 +9,14 @@
   },
   "Instructions": {
     "fadd dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /0"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -30,15 +30,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -56,11 +58,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -74,18 +76,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -103,22 +107,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /1"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -132,15 +136,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -158,11 +164,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -176,18 +182,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -205,22 +213,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcom dword [rax]": {
-      "ExpectedInstructionCount": 99,
+      "ExpectedInstructionCount": 103,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /2"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -234,15 +242,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -260,11 +270,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -278,18 +288,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -321,14 +333,14 @@
       ]
     },
     "fcomp dword [rax]": {
-      "ExpectedInstructionCount": 107,
+      "ExpectedInstructionCount": 111,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /3"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -342,15 +354,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -368,11 +382,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -386,18 +400,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -437,14 +453,14 @@
       ]
     },
     "fsub dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /4"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -458,15 +474,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -484,11 +502,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -502,18 +520,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -531,22 +551,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /5"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -560,15 +580,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -586,11 +608,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -604,18 +626,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -633,22 +657,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /6"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -662,15 +686,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -688,11 +714,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -706,18 +732,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -735,22 +763,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xd8 !11b /7"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -764,15 +792,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -790,11 +820,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -808,18 +838,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -837,15 +869,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc0 /0"
@@ -855,9 +887,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -871,18 +903,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -900,15 +934,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc1 /0"
@@ -918,9 +952,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -934,18 +968,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -963,15 +999,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc2 /0"
@@ -981,9 +1017,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -997,18 +1033,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1026,15 +1064,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc3 /0"
@@ -1044,9 +1082,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1060,18 +1098,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1089,15 +1129,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc4 /0"
@@ -1107,9 +1147,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1123,18 +1163,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1152,15 +1194,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc5 /0"
@@ -1170,9 +1212,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1186,18 +1228,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1215,15 +1259,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc6 /0"
@@ -1233,9 +1277,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1249,18 +1293,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1278,15 +1324,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc7 /0"
@@ -1296,9 +1342,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1312,18 +1358,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1341,15 +1389,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc8 /1"
@@ -1359,9 +1407,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1375,18 +1423,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1404,15 +1454,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc9 /1"
@@ -1422,9 +1472,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1438,18 +1488,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1467,15 +1519,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xca /1"
@@ -1485,9 +1537,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1501,18 +1553,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1530,15 +1584,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xcb /1"
@@ -1548,9 +1602,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1564,18 +1618,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1593,15 +1649,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xcc /1"
@@ -1611,9 +1667,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1627,18 +1683,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1656,15 +1714,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xcd /1"
@@ -1674,9 +1732,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1690,18 +1748,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1719,15 +1779,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xce /1"
@@ -1737,9 +1797,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1753,18 +1813,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1782,15 +1844,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xcf /1"
@@ -1800,9 +1862,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1816,18 +1878,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1845,15 +1909,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcom st0, st0": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd0 /2"
@@ -1864,9 +1928,9 @@
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1880,18 +1944,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1922,7 +1988,7 @@
       ]
     },
     "fcom st0, st1": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd1 /2"
@@ -1932,9 +1998,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -1948,18 +2014,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -1991,7 +2059,7 @@
       ]
     },
     "fcom st0, st2": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd2 /2"
@@ -2001,9 +2069,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2017,18 +2085,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2060,7 +2130,7 @@
       ]
     },
     "fcom st0, st3": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd3 /2"
@@ -2070,9 +2140,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2086,18 +2156,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2129,7 +2201,7 @@
       ]
     },
     "fcom st0, st4": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd4 /2"
@@ -2139,9 +2211,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2155,18 +2227,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2198,7 +2272,7 @@
       ]
     },
     "fcom st0, st5": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd5 /2"
@@ -2208,9 +2282,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2224,18 +2298,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2267,7 +2343,7 @@
       ]
     },
     "fcom st0, st6": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd6 /2"
@@ -2277,9 +2353,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2293,18 +2369,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2336,7 +2414,7 @@
       ]
     },
     "fcom st0, st7": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd7 /2"
@@ -2346,9 +2424,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2362,18 +2440,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2405,7 +2485,7 @@
       ]
     },
     "fcomp st0, st0": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd8 /3"
@@ -2416,9 +2496,9 @@
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2432,18 +2512,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2482,7 +2564,7 @@
       ]
     },
     "fcomp st0, st1": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xd9 /3"
@@ -2493,9 +2575,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2509,18 +2591,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2559,7 +2643,7 @@
       ]
     },
     "fcomp st0, st2": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xda /3"
@@ -2569,9 +2653,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2585,18 +2669,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2636,7 +2722,7 @@
       ]
     },
     "fcomp st0, st3": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xdb /3"
@@ -2646,9 +2732,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2662,18 +2748,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2713,7 +2801,7 @@
       ]
     },
     "fcomp st0, st4": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xdc /3"
@@ -2723,9 +2811,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2739,18 +2827,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2790,7 +2880,7 @@
       ]
     },
     "fcomp st0, st5": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xdd /3"
@@ -2800,9 +2890,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2816,18 +2906,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2867,7 +2959,7 @@
       ]
     },
     "fcomp st0, st6": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xde /3"
@@ -2877,9 +2969,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2893,18 +2985,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -2944,7 +3038,7 @@
       ]
     },
     "fcomp st0, st7": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xdf /3"
@@ -2954,9 +3048,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -2970,18 +3064,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3021,7 +3117,7 @@
       ]
     },
     "fsub st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe0 /4"
@@ -3031,9 +3127,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3047,18 +3143,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3076,15 +3174,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe1 /4"
@@ -3094,9 +3192,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3110,18 +3208,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3139,15 +3239,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe2 /4"
@@ -3157,9 +3257,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3173,18 +3273,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3202,15 +3304,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe3 /4"
@@ -3220,9 +3322,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3236,18 +3338,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3265,15 +3369,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe4 /4"
@@ -3283,9 +3387,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3299,18 +3403,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3328,15 +3434,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe5 /4"
@@ -3346,9 +3452,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3362,18 +3468,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3391,15 +3499,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe6 /4"
@@ -3409,9 +3517,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3425,18 +3533,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3454,15 +3564,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe7 /4"
@@ -3472,9 +3582,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3488,18 +3598,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3517,15 +3629,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe8 /5"
@@ -3535,9 +3647,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3551,18 +3663,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3580,15 +3694,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xe9 /5"
@@ -3598,9 +3712,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3614,18 +3728,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3643,15 +3759,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xea /5"
@@ -3661,9 +3777,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3677,18 +3793,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3706,15 +3824,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xeb /5"
@@ -3724,9 +3842,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3740,18 +3858,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3769,15 +3889,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xec /5"
@@ -3787,9 +3907,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3803,18 +3923,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3832,15 +3954,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xed /5"
@@ -3850,9 +3972,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3866,18 +3988,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3895,15 +4019,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xee /5"
@@ -3913,9 +4037,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3929,18 +4053,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -3958,15 +4084,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xef /5"
@@ -3976,9 +4102,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -3992,18 +4118,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4021,15 +4149,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf0 /6"
@@ -4039,9 +4167,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4055,18 +4183,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4084,15 +4214,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf1 /6"
@@ -4102,9 +4232,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4118,18 +4248,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4147,15 +4279,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf2 /6"
@@ -4165,9 +4297,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4181,18 +4313,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4210,15 +4344,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf3 /6"
@@ -4228,9 +4362,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4244,18 +4378,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4273,15 +4409,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf4 /6"
@@ -4291,9 +4427,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4307,18 +4443,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4336,15 +4474,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf5 /6"
@@ -4354,9 +4492,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4370,18 +4508,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4399,15 +4539,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf6 /6"
@@ -4417,9 +4557,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4433,18 +4573,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4462,15 +4604,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf7 /6"
@@ -4480,9 +4622,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4496,18 +4638,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4525,15 +4669,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf8 /7"
@@ -4543,9 +4687,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4559,18 +4703,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4588,15 +4734,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st1": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xf9 /7"
@@ -4606,9 +4752,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4622,18 +4768,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4651,15 +4799,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st2": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xfa /7"
@@ -4669,9 +4817,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4685,18 +4833,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4714,15 +4864,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st3": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xfb /7"
@@ -4732,9 +4882,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4748,18 +4898,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4777,15 +4929,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st4": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xfc /7"
@@ -4795,9 +4947,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4811,18 +4963,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4840,15 +4994,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st5": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xfd /7"
@@ -4858,9 +5012,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4874,18 +5028,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4903,15 +5059,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st6": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xfe /7"
@@ -4921,9 +5077,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -4937,18 +5093,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -4966,15 +5124,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st0, st7": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xff /7"
@@ -4984,9 +5142,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -5000,18 +5158,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5029,22 +5189,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld dword [rax]": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd9 !11b /0"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr s4, [x4]",
+        "ldr s2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -5058,15 +5218,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "fmov s0, s4",
+        "fmov s0, s2",
         "ldr x0, [x28, #1152]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5084,9 +5246,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5096,11 +5258,11 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst dword [rax]": {
-      "ExpectedInstructionCount": 45,
+      "ExpectedInstructionCount": 47,
       "Optimal": "No",
       "Comment": [
         "0xd9 !11b /2"
@@ -5108,7 +5270,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -5122,16 +5284,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1168]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5149,12 +5313,12 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "fmov s4, s0",
-        "str s4, [x4]"
+        "fmov s2, s0",
+        "str s2, [x4]"
       ]
     },
     "fstp dword [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xd9 !11b /3"
@@ -5162,7 +5326,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -5176,16 +5340,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1168]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5203,8 +5369,8 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "fmov s4, s0",
-        "str s4, [x4]",
+        "fmov s2, s0",
+        "str s2, [x4]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -5216,7 +5382,7 @@
       ]
     },
     "fldenv [rax]": {
-      "ExpectedInstructionCount": 102,
+      "ExpectedInstructionCount": 104,
       "Optimal": "No",
       "Comment": [
         "0xd9 !11b /4"
@@ -5236,8 +5402,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -5245,6 +5412,7 @@
         "uxth w0, w20",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5327,7 +5495,7 @@
       ]
     },
     "fldcw [rax]": {
-      "ExpectedInstructionCount": 41,
+      "ExpectedInstructionCount": 43,
       "Optimal": "No",
       "Comment": [
         "0xd9 !11b /5"
@@ -5347,8 +5515,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -5356,6 +5525,7 @@
         "uxth w0, w20",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5479,7 +5649,7 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5489,7 +5659,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st1": {
@@ -5504,7 +5674,7 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "ldrb w22, [x28, #1010]",
@@ -5513,7 +5683,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st2": {
@@ -5527,7 +5697,7 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5537,7 +5707,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st3": {
@@ -5551,7 +5721,7 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5561,7 +5731,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st4": {
@@ -5575,7 +5745,7 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5585,7 +5755,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st5": {
@@ -5599,7 +5769,7 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5609,7 +5779,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st6": {
@@ -5623,7 +5793,7 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5633,7 +5803,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld st7": {
@@ -5647,7 +5817,7 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -5657,7 +5827,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st0": {
@@ -5671,13 +5841,13 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st1": {
@@ -5691,13 +5861,13 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st2": {
@@ -5711,13 +5881,13 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st3": {
@@ -5731,13 +5901,13 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st4": {
@@ -5751,13 +5921,13 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st5": {
@@ -5771,13 +5941,13 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st6": {
@@ -5791,13 +5961,13 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxch st0, st7": {
@@ -5811,13 +5981,13 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fnop": {
@@ -5837,14 +6007,14 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w21, #0x0",
         "mov w22, #0x8000",
-        "fmov d5, x21",
-        "mov v5.d[1], x22",
-        "eor v4.16b, v4.16b, v5.16b",
+        "fmov d3, x21",
+        "mov v3.d[1], x22",
+        "eor v2.16b, v2.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fabs": {
@@ -5856,18 +6026,18 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x7fff",
-        "fmov d5, x21",
-        "mov v5.d[1], x22",
-        "and v4.16b, v4.16b, v5.16b",
+        "fmov d3, x21",
+        "mov v3.d[1], x22",
+        "and v2.16b, v2.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "ftst": {
-      "ExpectedInstructionCount": 57,
+      "ExpectedInstructionCount": 59,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xe4 /4"
@@ -5875,9 +6045,9 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "mov w20, #0x0",
-        "fmov d5, x20",
+        "fmov d3, x20",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -5891,18 +6061,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -5941,8 +6113,8 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "mov x21, v4.d[1]",
+        "ldr q2, [x0, #752]",
+        "mov x21, v2.d[1]",
         "ubfx x21, x21, #15, #1",
         "strb w21, [x28, #745]",
         "ldrb w21, [x28, #1010]",
@@ -5975,10 +6147,10 @@
         "strb w20, [x28, #747]",
         "mov x21, #0x8000000000000000",
         "mov w22, #0x3fff",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldl2t": {
@@ -6002,10 +6174,10 @@
         "movk x21, #0x784b, lsl #32",
         "movk x21, #0xd49a, lsl #48",
         "mov w22, #0x4000",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldl2e": {
@@ -6029,10 +6201,10 @@
         "movk x21, #0x3b29, lsl #32",
         "movk x21, #0xb8aa, lsl #48",
         "mov w22, #0x3fff",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldpi": {
@@ -6056,10 +6228,10 @@
         "movk x21, #0xdaa2, lsl #32",
         "movk x21, #0xc90f, lsl #48",
         "mov w22, #0x4000",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldlg2": {
@@ -6083,10 +6255,10 @@
         "movk x21, #0x9a84, lsl #32",
         "movk x21, #0x9a20, lsl #48",
         "mov w22, #0x3ffd",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldln2": {
@@ -6110,10 +6282,10 @@
         "movk x21, #0x17f7, lsl #32",
         "movk x21, #0xb172, lsl #48",
         "mov w22, #0x3ffe",
-        "fmov d4, x21",
-        "mov v4.d[1], x22",
+        "fmov d2, x21",
+        "mov v2.d[1], x22",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fldz": {
@@ -6133,14 +6305,14 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "mov w21, #0x0",
-        "fmov d4, x21",
-        "mov v4.d[1], x21",
+        "fmov d2, x21",
+        "mov v2.d[1], x21",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "f2xm1": {
-      "ExpectedInstructionCount": 48,
+      "ExpectedInstructionCount": 50,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf0 /6"
@@ -6148,7 +6320,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6162,16 +6334,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1320]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6189,15 +6363,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fyl2x": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf1 /6"
@@ -6213,9 +6387,9 @@
         "and w21, w21, #0x7",
         "strb w21, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6229,18 +6403,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1424]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6258,15 +6434,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fptan": {
-      "ExpectedInstructionCount": 64,
+      "ExpectedInstructionCount": 66,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf2 /6"
@@ -6282,7 +6458,7 @@
         "strb w21, [x28, #1010]",
         "strb w22, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6296,16 +6472,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1328]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6323,23 +6501,23 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov x21, #0x8000000000000000",
         "mov w23, #0x3fff",
-        "fmov d5, x21",
-        "mov v5.d[1], x23",
+        "fmov d3, x21",
+        "mov v3.d[1], x23",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "str q5, [x0, #752]"
+        "str q3, [x0, #752]"
       ]
     },
     "fpatan": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf3 /6"
@@ -6355,9 +6533,9 @@
         "and w21, w21, #0x7",
         "strb w21, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6371,18 +6549,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1432]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6400,15 +6580,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fxtract": {
-      "ExpectedInstructionCount": 101,
+      "ExpectedInstructionCount": 105,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf4 /6"
@@ -6424,7 +6604,7 @@
         "strb w21, [x28, #1010]",
         "strb w22, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6438,16 +6618,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1360]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6465,9 +6647,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v5.16b, v5.16b, v5.16b",
-        "mov v5.d[0], x0",
-        "mov v5.h[4], w1",
+        "eor v3.16b, v3.16b, v3.16b",
+        "mov v3.d[0], x0",
+        "mov v3.h[4], w1",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6481,16 +6663,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1368]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6508,17 +6692,17 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fprem1": {
-      "ExpectedInstructionCount": 56,
+      "ExpectedInstructionCount": 58,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf5 /6"
@@ -6528,9 +6712,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6544,18 +6728,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1440]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6573,13 +6759,13 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdecstp": {
@@ -6609,7 +6795,7 @@
       ]
     },
     "fprem": {
-      "ExpectedInstructionCount": 56,
+      "ExpectedInstructionCount": 58,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf8 /7"
@@ -6619,9 +6805,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6635,18 +6821,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1448]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6664,17 +6852,17 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fyl2xp1": {
-      "ExpectedInstructionCount": 109,
+      "ExpectedInstructionCount": 113,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xf9 /7"
@@ -6690,13 +6878,13 @@
         "and w21, w21, #0x7",
         "strb w21, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "mov x20, #0x8000000000000000",
         "mov w22, #0x3fff",
-        "fmov d6, x20",
-        "mov v6.d[1], x22",
+        "fmov d4, x20",
+        "mov v4.d[1], x22",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6710,18 +6898,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v6.d[0]",
-        "umov w3, v6.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v4.d[0]",
+        "umov w3, v4.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6739,9 +6929,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6755,18 +6945,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1424]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6784,15 +6976,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsqrt": {
-      "ExpectedInstructionCount": 48,
+      "ExpectedInstructionCount": 50,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xfa /7"
@@ -6800,7 +6992,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6814,16 +7006,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1336]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6841,15 +7035,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsincos": {
-      "ExpectedInstructionCount": 103,
+      "ExpectedInstructionCount": 107,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xfb /7"
@@ -6865,7 +7059,7 @@
         "strb w21, [x28, #1010]",
         "strb w22, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6879,16 +7073,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1344]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6906,9 +7102,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v5.16b, v5.16b, v5.16b",
-        "mov v5.d[0], x0",
-        "mov v5.h[4], w1",
+        "eor v3.16b, v3.16b, v3.16b",
+        "mov v3.d[0], x0",
+        "mov v3.h[4], w1",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6922,16 +7118,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1352]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -6949,19 +7147,19 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "frndint": {
-      "ExpectedInstructionCount": 48,
+      "ExpectedInstructionCount": 50,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xfc /7"
@@ -6969,7 +7167,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -6983,16 +7181,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1312]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7010,15 +7210,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fscale": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xfd /7"
@@ -7028,9 +7228,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7044,18 +7244,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1456]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7073,15 +7275,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsin": {
-      "ExpectedInstructionCount": 50,
+      "ExpectedInstructionCount": 52,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xfe /7"
@@ -7089,7 +7291,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7103,16 +7305,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1344]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7130,17 +7334,17 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcos": {
-      "ExpectedInstructionCount": 50,
+      "ExpectedInstructionCount": 52,
       "Optimal": "No",
       "Comment": [
         "0xd9 11b 0xff /7"
@@ -7148,7 +7352,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7162,16 +7366,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1352]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7189,17 +7395,17 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x0",
         "strb w21, [x28, #746]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fiadd dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /0"
@@ -7220,8 +7426,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7229,6 +7436,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7246,11 +7454,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7264,18 +7472,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7293,15 +7503,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fimul dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /1"
@@ -7322,8 +7532,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7331,6 +7542,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7348,11 +7560,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7366,18 +7578,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7395,15 +7609,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "ficom dword [rax]": {
-      "ExpectedInstructionCount": 99,
+      "ExpectedInstructionCount": 103,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /2"
@@ -7424,8 +7638,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7433,6 +7648,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7450,11 +7666,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7468,18 +7684,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7511,7 +7729,7 @@
       ]
     },
     "ficomp dword [rax]": {
-      "ExpectedInstructionCount": 107,
+      "ExpectedInstructionCount": 111,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /3"
@@ -7532,8 +7750,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7541,6 +7760,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7558,11 +7778,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7576,18 +7796,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7627,7 +7849,7 @@
       ]
     },
     "fisub dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /4"
@@ -7648,8 +7870,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7657,6 +7880,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7674,11 +7898,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7692,18 +7916,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7721,15 +7947,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fisubr dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /5"
@@ -7750,8 +7976,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7759,6 +7986,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7776,11 +8004,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7794,18 +8022,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7823,15 +8053,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fidiv dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /6"
@@ -7852,8 +8082,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7861,6 +8092,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7878,11 +8110,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7896,18 +8128,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7925,15 +8159,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fidivr dword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xda !11b /7"
@@ -7954,8 +8188,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -7963,6 +8198,7 @@
         "mov w0, w21",
         "ldr x1, [x28, #1304]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -7980,11 +8216,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -7998,18 +8234,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -8027,11 +8265,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovb st0, st0": {
@@ -8047,17 +8285,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8074,17 +8312,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8101,17 +8339,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8128,17 +8366,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8155,17 +8393,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8182,17 +8420,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8209,17 +8447,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8236,17 +8474,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8265,17 +8503,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8294,17 +8532,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8323,17 +8561,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8352,17 +8590,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8381,17 +8619,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8410,17 +8648,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8439,17 +8677,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8468,17 +8706,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -8497,17 +8735,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8526,17 +8764,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8555,17 +8793,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8584,17 +8822,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8613,17 +8851,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8642,17 +8880,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8671,17 +8909,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8700,17 +8938,17 @@
         "mov x23, #0xffffffffffffffff",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -8725,26 +8963,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st1": {
@@ -8758,26 +8996,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st2": {
@@ -8791,26 +9029,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st3": {
@@ -8824,26 +9062,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st4": {
@@ -8857,26 +9095,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st5": {
@@ -8890,26 +9128,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st6": {
@@ -8923,26 +9161,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovu st0, st7": {
@@ -8956,30 +9194,30 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov w21, #0x0",
         "mov x22, #0xffffffffffffffff",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fucompp": {
-      "ExpectedInstructionCount": 74,
+      "ExpectedInstructionCount": 76,
       "Optimal": "No",
       "Comment": [
         "0xda 11b 0xe9 /5"
@@ -8990,9 +9228,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -9006,18 +9244,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -9096,15 +9336,15 @@
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x24, eq",
         "orr x21, x23, x21",
-        "fmov d4, x25",
-        "fmov d5, x21",
-        "mov v4.d[1], v5.d[0]",
+        "fmov d2, x25",
+        "fmov d3, x21",
+        "mov v2.d[1], v3.d[0]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fisttp dword [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdb !11b /1"
@@ -9112,7 +9352,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -9126,16 +9366,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1216]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -9166,7 +9408,7 @@
       ]
     },
     "fist dword [rax]": {
-      "ExpectedInstructionCount": 45,
+      "ExpectedInstructionCount": 47,
       "Optimal": "No",
       "Comment": [
         "0xdb !11b /2"
@@ -9174,7 +9416,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -9188,16 +9430,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1192]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -9220,7 +9464,7 @@
       ]
     },
     "fistp dword [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /7"
@@ -9228,7 +9472,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -9242,16 +9486,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1192]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -9289,7 +9535,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -9299,7 +9545,7 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fstp tword [rax]": {
@@ -9311,9 +9557,9 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "str d4, [x4]",
-        "mov x21, v4.d[1]",
+        "ldr q2, [x0, #752]",
+        "str d2, [x4]",
+        "mov x21, v2.d[1]",
         "strh w21, [x4, #8]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
@@ -9338,17 +9584,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9365,17 +9611,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9392,17 +9638,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9419,17 +9665,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9446,17 +9692,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9473,17 +9719,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9500,17 +9746,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9527,17 +9773,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9556,17 +9802,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9585,17 +9831,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9614,17 +9860,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9643,17 +9889,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9672,17 +9918,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9701,17 +9947,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9730,17 +9976,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9759,17 +10005,17 @@
         "mov w23, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x22, x23, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w21, [x28, #728]"
       ]
     },
@@ -9788,17 +10034,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9817,17 +10063,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9846,17 +10092,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x2 (2)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9875,17 +10121,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x3 (3)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9904,17 +10150,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x4 (4)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9933,17 +10179,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x5 (5)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9962,17 +10208,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x6 (6)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -9991,17 +10237,17 @@
         "mov w23, #0x0",
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x23, eq",
-        "dup v4.2d, x21",
+        "dup v2.2d, x21",
         "ldrb w21, [x28, #747]",
         "add w22, w21, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "str w20, [x28, #728]"
       ]
     },
@@ -10016,26 +10262,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st1": {
@@ -10049,26 +10295,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st2": {
@@ -10082,26 +10328,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st3": {
@@ -10115,26 +10361,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st4": {
@@ -10148,26 +10394,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st5": {
@@ -10181,26 +10427,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st6": {
@@ -10214,26 +10460,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcmovnu st0, st7": {
@@ -10247,26 +10493,26 @@
         "mov w21, #0x1",
         "ldrb w22, [x28, #706]",
         "eor w22, w22, #0x1",
-        "fmov s4, w22",
-        "cnt v4.16b, v4.16b",
-        "umov w22, v4.b[0]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
         "and x21, x21, x22",
         "orr x20, x20, x21, lsl #2",
         "mov x21, #0xffffffffffffffff",
         "mov w22, #0x0",
         "cmp x20, #0x0 (0)",
         "csel x20, x21, x22, eq",
-        "dup v4.2d, x20",
+        "dup v2.2d, x20",
         "ldrb w20, [x28, #747]",
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "ldr q6, [x0, #752]",
-        "bsl v4.16b, v6.16b, v5.16b",
+        "ldr q4, [x0, #752]",
+        "bsl v2.16b, v4.16b, v3.16b",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fnclex": {
@@ -10278,7 +10524,7 @@
       "ExpectedArm64ASM": []
     },
     "fninit": {
-      "ExpectedInstructionCount": 48,
+      "ExpectedInstructionCount": 50,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xe3 /4"
@@ -10299,8 +10545,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -10308,6 +10555,7 @@
         "uxth w0, w21",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10335,7 +10583,7 @@
       ]
     },
     "fucomi st0, st0": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xe8 /5"
@@ -10345,9 +10593,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10361,18 +10609,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10404,7 +10654,7 @@
       ]
     },
     "fucomi st0, st1": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xe9 /5"
@@ -10414,9 +10664,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10430,18 +10680,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10473,7 +10725,7 @@
       ]
     },
     "fucomi st0, st2": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xea /5"
@@ -10483,9 +10735,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10499,18 +10751,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10542,7 +10796,7 @@
       ]
     },
     "fucomi st0, st3": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xeb /5"
@@ -10552,9 +10806,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10568,18 +10822,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10611,7 +10867,7 @@
       ]
     },
     "fucomi st0, st4": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xec /5"
@@ -10621,9 +10877,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10637,18 +10893,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10680,7 +10938,7 @@
       ]
     },
     "fucomi st0, st5": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xed /5"
@@ -10690,9 +10948,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10706,18 +10964,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10749,7 +11009,7 @@
       ]
     },
     "fucomi st0, st6": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xee /5"
@@ -10759,9 +11019,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10775,18 +11035,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10818,7 +11080,7 @@
       ]
     },
     "fucomi st0, st7": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xef /5"
@@ -10828,9 +11090,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10844,18 +11106,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10887,7 +11151,7 @@
       ]
     },
     "fcomi st0, st0": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf0 /6"
@@ -10897,9 +11161,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10913,18 +11177,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -10956,7 +11222,7 @@
       ]
     },
     "fcomi st0, st1": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf1 /6"
@@ -10966,9 +11232,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -10982,18 +11248,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11025,7 +11293,7 @@
       ]
     },
     "fcomi st0, st2": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf2 /6"
@@ -11035,9 +11303,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11051,18 +11319,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11094,7 +11364,7 @@
       ]
     },
     "fcomi st0, st3": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf3 /6"
@@ -11104,9 +11374,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11120,18 +11390,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11163,7 +11435,7 @@
       ]
     },
     "fcomi st0, st4": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf4 /6"
@@ -11173,9 +11445,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11189,18 +11461,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11232,7 +11506,7 @@
       ]
     },
     "fcomi st0, st5": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf5 /6"
@@ -11242,9 +11516,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11258,18 +11532,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11301,7 +11577,7 @@
       ]
     },
     "fcomi st0, st6": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf6 /6"
@@ -11311,9 +11587,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11327,18 +11603,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11370,7 +11648,7 @@
       ]
     },
     "fcomi st0, st7": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdb 11b 0xf7 /6"
@@ -11380,9 +11658,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11396,18 +11674,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11439,14 +11719,14 @@
       ]
     },
     "fadd qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /0"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11460,15 +11740,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11486,11 +11768,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11504,18 +11786,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11533,22 +11817,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /1"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11562,15 +11846,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11588,11 +11874,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11606,18 +11892,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11635,22 +11923,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcom qword [rax]": {
-      "ExpectedInstructionCount": 99,
+      "ExpectedInstructionCount": 103,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /2"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11664,15 +11952,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11690,11 +11980,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11708,18 +11998,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11751,14 +12043,14 @@
       ]
     },
     "fcomp qword [rax]": {
-      "ExpectedInstructionCount": 107,
+      "ExpectedInstructionCount": 111,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /3"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11772,15 +12064,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11798,11 +12092,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11816,18 +12110,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11867,14 +12163,14 @@
       ]
     },
     "fsub qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /4"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11888,15 +12184,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11914,11 +12212,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11932,18 +12230,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -11961,22 +12261,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /5"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -11990,15 +12290,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12016,11 +12318,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12034,18 +12336,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12063,22 +12367,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /6"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12092,15 +12396,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12118,11 +12424,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12136,18 +12442,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12165,22 +12473,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr qword [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xdc !11b /7"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12194,15 +12502,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12220,11 +12530,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12238,18 +12548,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12267,15 +12579,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xc0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fadd st0, st0",
@@ -12287,9 +12599,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12303,18 +12615,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12332,15 +12646,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc1 /0"
@@ -12350,9 +12664,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12366,18 +12680,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12395,15 +12711,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc2 /0"
@@ -12413,9 +12729,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12429,18 +12745,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12458,15 +12776,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc3 /0"
@@ -12476,9 +12794,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12492,18 +12810,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12521,15 +12841,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc4 /0"
@@ -12539,9 +12859,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12555,18 +12875,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12584,15 +12906,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc5 /0"
@@ -12602,9 +12924,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12618,18 +12940,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12647,15 +12971,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc6 /0"
@@ -12665,9 +12989,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12681,18 +13005,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12710,15 +13036,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fadd st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc7 /0"
@@ -12728,9 +13054,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12744,18 +13070,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12773,15 +13101,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xc8": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fmul st0, st0",
@@ -12793,9 +13121,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12809,18 +13137,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12838,15 +13168,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xc9 /1"
@@ -12856,9 +13186,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12872,18 +13202,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12901,15 +13233,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xca /1"
@@ -12919,9 +13251,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12935,18 +13267,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -12964,15 +13298,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xcb /1"
@@ -12982,9 +13316,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -12998,18 +13332,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13027,15 +13363,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xcc /1"
@@ -13045,9 +13381,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13061,18 +13397,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13090,15 +13428,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xcd /1"
@@ -13108,9 +13446,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13124,18 +13462,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13153,15 +13493,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xce /1"
@@ -13171,9 +13511,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13187,18 +13527,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13216,15 +13558,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmul st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xcf /1"
@@ -13234,9 +13576,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13250,18 +13592,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13279,15 +13623,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xe0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fsubr st0, st0",
@@ -13299,9 +13643,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13315,18 +13659,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13344,15 +13690,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe1 /4"
@@ -13362,9 +13708,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13378,18 +13724,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13407,15 +13755,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe2 /4"
@@ -13425,9 +13773,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13441,18 +13789,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13470,15 +13820,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe3 /4"
@@ -13488,9 +13838,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13504,18 +13854,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13533,15 +13885,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe4 /4"
@@ -13551,9 +13903,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13567,18 +13919,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13596,15 +13950,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe5 /4"
@@ -13614,9 +13968,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13630,18 +13984,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13659,15 +14015,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe6 /4"
@@ -13677,9 +14033,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13693,18 +14049,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13722,15 +14080,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubr st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe7 /4"
@@ -13740,9 +14098,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13756,18 +14114,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13785,15 +14145,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xe8": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fsub st0, st0",
@@ -13805,9 +14165,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13821,18 +14181,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13850,15 +14212,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xe9 /5"
@@ -13868,9 +14230,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13884,18 +14246,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13913,15 +14277,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xea /5"
@@ -13931,9 +14295,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -13947,18 +14311,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -13976,15 +14342,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xeb /5"
@@ -13994,9 +14360,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14010,18 +14376,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14039,15 +14407,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xec /5"
@@ -14057,9 +14425,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14073,18 +14441,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14102,15 +14472,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xed /5"
@@ -14120,9 +14490,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14136,18 +14506,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14165,15 +14537,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xee /5"
@@ -14183,9 +14555,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14199,18 +14571,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14228,15 +14602,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsub st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xef /5"
@@ -14246,9 +14620,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14262,18 +14636,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14291,15 +14667,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xf0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fdivr st0, st0",
@@ -14311,9 +14687,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14327,18 +14703,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14356,15 +14734,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf1 /6"
@@ -14374,9 +14752,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14390,18 +14768,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14419,15 +14799,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf2 /6"
@@ -14437,9 +14817,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14453,18 +14833,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14482,15 +14864,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf3 /6"
@@ -14500,9 +14882,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14516,18 +14898,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14545,15 +14929,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf4 /6"
@@ -14563,9 +14947,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14579,18 +14963,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14608,15 +14994,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf5 /6"
@@ -14626,9 +15012,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14642,18 +15028,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14671,15 +15059,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf6 /6"
@@ -14689,9 +15077,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14705,18 +15093,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14734,15 +15124,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivr st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf7 /6"
@@ -14752,9 +15142,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14768,18 +15158,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14797,15 +15189,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xdc, 0xf8": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "fdiv st0, st0",
@@ -14817,9 +15209,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14833,18 +15225,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14862,15 +15256,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st1, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xf9 /7"
@@ -14880,9 +15274,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14896,18 +15290,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14925,15 +15321,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st2, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xfa /7"
@@ -14943,9 +15339,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -14959,18 +15355,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -14988,15 +15386,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st3, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xfb /7"
@@ -15006,9 +15404,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15022,18 +15420,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15051,15 +15451,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st4, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xfc /7"
@@ -15069,9 +15469,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15085,18 +15485,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15114,15 +15516,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st5, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xfd /7"
@@ -15132,9 +15534,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15148,18 +15550,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15177,15 +15581,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st6, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xfe /7"
@@ -15195,9 +15599,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15211,18 +15615,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15240,15 +15646,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdiv st7, st0": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdc 11b 0xff /7"
@@ -15258,9 +15664,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15274,18 +15680,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15303,22 +15711,22 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fld qword [rax]": {
-      "ExpectedInstructionCount": 54,
+      "ExpectedInstructionCount": 56,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /0"
       ],
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
-        "ldr d4, [x4]",
+        "ldr d2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15332,15 +15740,17 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov v0.8b, v4.8b",
+        "mov v0.8b, v2.8b",
         "ldr x0, [x28, #1160]",
         "blr x0",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15358,9 +15768,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "mov w21, #0x1",
         "sub w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
@@ -15370,11 +15780,11 @@
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fisttp qword [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /1"
@@ -15382,7 +15792,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15396,16 +15806,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1224]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15436,7 +15848,7 @@
       ]
     },
     "fst qword [rax]": {
-      "ExpectedInstructionCount": 45,
+      "ExpectedInstructionCount": 47,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /2"
@@ -15444,7 +15856,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15458,16 +15870,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1176]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15485,12 +15899,12 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "mov v4.8b, v0.8b",
-        "str d4, [x4]"
+        "mov v2.8b, v0.8b",
+        "str d2, [x4]"
       ]
     },
     "fstp qword [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /3"
@@ -15498,7 +15912,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -15512,16 +15926,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1176]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15539,8 +15955,8 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "mov v4.8b, v0.8b",
-        "str d4, [x4]",
+        "mov v2.8b, v0.8b",
+        "str d2, [x4]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -15552,7 +15968,7 @@
       ]
     },
     "frstor [rax]": {
-      "ExpectedInstructionCount": 161,
+      "ExpectedInstructionCount": 163,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /4"
@@ -15572,8 +15988,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -15581,6 +15998,7 @@
         "uxth w0, w20",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -15663,66 +16081,66 @@
         "add x20, x4, #0x1c (28)",
         "mov x22, #0xffffffffffffffff",
         "mov w23, #0xffff",
-        "fmov d4, x22",
-        "mov v4.d[1], x23",
-        "ldur q5, [x4, #28]",
-        "and v5.16b, v5.16b, v4.16b",
+        "fmov d2, x22",
+        "mov v2.d[1], x23",
+        "ldur q3, [x4, #28]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x22, x20, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x20, #10]",
-        "and v5.16b, v5.16b, v4.16b",
+        "ldur q3, [x20, #10]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x20, x22, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x22, #10]",
-        "and v5.16b, v5.16b, v4.16b",
+        "ldur q3, [x22, #10]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x22, x20, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x20, #10]",
-        "and v5.16b, v5.16b, v4.16b",
+        "ldur q3, [x20, #10]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x20, x22, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x22, #10]",
-        "and v5.16b, v5.16b, v4.16b",
+        "ldur q3, [x22, #10]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x22, x20, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x20, #10]",
-        "and v5.16b, v5.16b, v4.16b",
+        "ldur q3, [x20, #10]",
+        "and v3.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q5, [x0, #752]",
+        "str q3, [x0, #752]",
         "add x20, x22, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur q5, [x22, #10]",
-        "and v4.16b, v5.16b, v4.16b",
+        "ldur q3, [x22, #10]",
+        "and v2.16b, v3.16b, v2.16b",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "add x22, x20, #0xa (10)",
         "add w21, w21, #0x1 (1)",
         "and w21, w21, #0x7",
-        "ldur d4, [x20, #10]",
-        "ldr h5, [x22, #8]",
-        "mov v4.h[4], v5.h[0]",
+        "ldur d2, [x20, #10]",
+        "ldr h3, [x22, #8]",
+        "mov v2.h[4], v3.h[0]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fnsave [rax]": {
-      "ExpectedInstructionCount": 167,
+      "ExpectedInstructionCount": 169,
       "Optimal": "No",
       "Comment": [
         "0xdd !11b /6"
@@ -15802,52 +16220,52 @@
         "str w21, [x4, #24]",
         "add x22, x4, #0x1c (28)",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x4, #28]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x4, #28]",
         "add x23, x22, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x22, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x22, #10]",
         "add x22, x23, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x23, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x23, #10]",
         "add x23, x22, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x22, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x22, #10]",
         "add x22, x23, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x23, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x23, #10]",
         "add x23, x22, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x22, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x22, #10]",
         "add x22, x23, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur q4, [x23, #10]",
+        "ldr q2, [x0, #752]",
+        "stur q2, [x23, #10]",
         "add x23, x22, #0xa (10)",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
-        "stur d4, [x22, #10]",
-        "dup v4.8h, v4.h[4]",
-        "str h4, [x23, #8]",
+        "ldr q2, [x0, #752]",
+        "stur d2, [x22, #10]",
+        "dup v2.8h, v2.h[4]",
+        "str h2, [x23, #8]",
         "mov w20, #0x37f",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
@@ -15862,8 +16280,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -15871,6 +16290,7 @@
         "uxth w0, w20",
         "ldr x1, [x28, #1144]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16070,9 +16490,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st1": {
@@ -16086,9 +16506,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st2": {
@@ -16102,9 +16522,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st3": {
@@ -16118,9 +16538,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st4": {
@@ -16134,9 +16554,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st5": {
@@ -16150,9 +16570,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st6": {
@@ -16166,9 +16586,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fst st7": {
@@ -16182,9 +16602,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fstp st0": {
@@ -16198,9 +16618,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16223,9 +16643,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w22, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w22, w21",
@@ -16246,9 +16666,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16270,9 +16690,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16294,9 +16714,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16318,9 +16738,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16342,9 +16762,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16366,9 +16786,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]",
+        "str q2, [x0, #752]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -16380,7 +16800,7 @@
       ]
     },
     "fucom st0": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe0 /4"
@@ -16391,9 +16811,9 @@
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16407,18 +16827,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16449,7 +16871,7 @@
       ]
     },
     "fucom st1": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe1 /4"
@@ -16459,9 +16881,9 @@
         "add w21, w20, #0x1 (1)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16475,18 +16897,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16518,7 +16942,7 @@
       ]
     },
     "fucom st2": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe2 /4"
@@ -16528,9 +16952,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16544,18 +16968,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16587,7 +17013,7 @@
       ]
     },
     "fucom st3": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe3 /4"
@@ -16597,9 +17023,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16613,18 +17039,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16656,7 +17084,7 @@
       ]
     },
     "fucom st4": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe4 /4"
@@ -16666,9 +17094,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16682,18 +17110,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16725,7 +17155,7 @@
       ]
     },
     "fucom st5": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe5 /4"
@@ -16735,9 +17165,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16751,18 +17181,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16794,7 +17226,7 @@
       ]
     },
     "fucom st6": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe6 /4"
@@ -16804,9 +17236,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16820,18 +17252,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16863,7 +17297,7 @@
       ]
     },
     "fucom st7": {
-      "ExpectedInstructionCount": 60,
+      "ExpectedInstructionCount": 62,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe7 /4"
@@ -16873,9 +17307,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16889,18 +17323,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -16932,7 +17368,7 @@
       ]
     },
     "fucomp st0": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe8 /5"
@@ -16943,9 +17379,9 @@
         "add w22, w20, #0x0 (0)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -16959,18 +17395,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17009,7 +17447,7 @@
       ]
     },
     "fucomp st1": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xe9 /5"
@@ -17020,9 +17458,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17036,18 +17474,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17086,7 +17526,7 @@
       ]
     },
     "fucomp st2": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xea /5"
@@ -17096,9 +17536,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17112,18 +17552,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17163,7 +17605,7 @@
       ]
     },
     "fucomp st3": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xeb /5"
@@ -17173,9 +17615,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17189,18 +17631,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17240,7 +17684,7 @@
       ]
     },
     "fucomp st4": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xec /5"
@@ -17250,9 +17694,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17266,18 +17710,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17317,7 +17763,7 @@
       ]
     },
     "fucomp st5": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xed /5"
@@ -17327,9 +17773,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17343,18 +17789,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17394,7 +17842,7 @@
       ]
     },
     "fucomp st6": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xee /5"
@@ -17404,9 +17852,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17420,18 +17868,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17471,7 +17921,7 @@
       ]
     },
     "fucomp st7": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdd 11b 0xef /5"
@@ -17481,9 +17931,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17497,18 +17947,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17548,7 +18000,7 @@
       ]
     },
     "fiadd word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /0"
@@ -17569,8 +18021,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -17578,6 +18031,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17595,11 +18049,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17613,18 +18067,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17642,15 +18098,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fimul word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /1"
@@ -17671,8 +18127,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -17680,6 +18137,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17697,11 +18155,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17715,18 +18173,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17744,15 +18204,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "ficom word [rax]": {
-      "ExpectedInstructionCount": 99,
+      "ExpectedInstructionCount": 103,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /2"
@@ -17773,8 +18233,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -17782,6 +18243,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17799,11 +18261,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17817,18 +18279,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17860,7 +18324,7 @@
       ]
     },
     "ficomp word [rax]": {
-      "ExpectedInstructionCount": 107,
+      "ExpectedInstructionCount": 111,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /3"
@@ -17881,8 +18345,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -17890,6 +18355,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17907,11 +18373,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -17925,18 +18391,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -17976,7 +18444,7 @@
       ]
     },
     "fisub word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /4"
@@ -17997,8 +18465,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -18006,6 +18475,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18023,11 +18493,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18041,18 +18511,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18070,15 +18542,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fisubr word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /5"
@@ -18099,8 +18571,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -18108,6 +18581,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18125,11 +18599,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18143,18 +18617,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18172,15 +18648,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fidiv word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /6"
@@ -18201,8 +18677,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -18210,6 +18687,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18227,11 +18705,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18245,18 +18723,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18274,15 +18754,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fidivr word [rax]": {
-      "ExpectedInstructionCount": 93,
+      "ExpectedInstructionCount": 97,
       "Optimal": "No",
       "Comment": [
         "0xde !11b /7"
@@ -18303,8 +18783,9 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
@@ -18312,6 +18793,7 @@
         "sxth w0, w21",
         "ldr x1, [x28, #1296]",
         "blr x1",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18329,11 +18811,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18347,18 +18829,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18376,15 +18860,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xd8 11b 0xc0 /0"
@@ -18394,9 +18878,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18410,18 +18894,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18439,9 +18925,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18451,11 +18937,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st1": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc1 /0"
@@ -18466,9 +18952,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18482,18 +18968,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18511,9 +18999,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -18522,11 +19010,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st2": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc2 /0"
@@ -18536,9 +19024,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18552,18 +19040,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18581,9 +19071,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18593,11 +19083,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st3": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc3 /0"
@@ -18607,9 +19097,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18623,18 +19113,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18652,9 +19144,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18664,11 +19156,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st4": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc4 /0"
@@ -18678,9 +19170,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18694,18 +19186,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18723,9 +19217,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18735,11 +19229,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st5": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc5 /0"
@@ -18749,9 +19243,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18765,18 +19259,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18794,9 +19290,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18806,11 +19302,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st6": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc6 /0"
@@ -18820,9 +19316,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18836,18 +19332,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18865,9 +19363,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18877,11 +19375,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "faddp st7": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc7 /0"
@@ -18891,9 +19389,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18907,18 +19405,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1392]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -18936,9 +19436,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -18948,11 +19448,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc8 /1"
@@ -18962,9 +19462,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -18978,18 +19478,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19007,9 +19509,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19019,11 +19521,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st1": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xc9 /1"
@@ -19034,9 +19536,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19050,18 +19552,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19079,9 +19583,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -19090,11 +19594,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st2": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xca /1"
@@ -19104,9 +19608,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19120,18 +19624,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19149,9 +19655,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19161,11 +19667,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st3": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xcb /1"
@@ -19175,9 +19681,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19191,18 +19697,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19220,9 +19728,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19232,11 +19740,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st4": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xcc /1"
@@ -19246,9 +19754,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19262,18 +19770,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19291,9 +19801,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19303,11 +19813,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st5": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xcd /1"
@@ -19317,9 +19827,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19333,18 +19843,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19362,9 +19874,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19374,11 +19886,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st6": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xce /1"
@@ -19388,9 +19900,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19404,18 +19916,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19433,9 +19947,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19445,11 +19959,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fmulp st7": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xcf /1"
@@ -19459,9 +19973,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19475,18 +19989,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1408]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19504,9 +20020,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19516,11 +20032,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fcompp": {
-      "ExpectedInstructionCount": 74,
+      "ExpectedInstructionCount": 76,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xd9 /3"
@@ -19531,9 +20047,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19547,18 +20063,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19603,7 +20121,7 @@
       ]
     },
     "db 0xde, 0xe0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "fsubrp st0, st0",
@@ -19615,9 +20133,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19631,18 +20149,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19660,9 +20180,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19672,11 +20192,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st1, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe1 /4"
@@ -19687,9 +20207,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19703,18 +20223,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19732,9 +20254,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -19743,11 +20265,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st2, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe2 /4"
@@ -19757,9 +20279,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19773,18 +20295,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19802,9 +20326,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19814,11 +20338,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st3, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe3 /4"
@@ -19828,9 +20352,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19844,18 +20368,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19873,9 +20399,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19885,11 +20411,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st4, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe4 /4"
@@ -19899,9 +20425,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19915,18 +20441,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -19944,9 +20472,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -19956,11 +20484,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st5, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe5 /4"
@@ -19970,9 +20498,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -19986,18 +20514,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20015,9 +20545,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20027,11 +20557,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st6, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe6 /4"
@@ -20041,9 +20571,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20057,18 +20587,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20086,9 +20618,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20098,11 +20630,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubrp st7, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe7 /4"
@@ -20112,9 +20644,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20128,18 +20660,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20157,9 +20691,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20169,11 +20703,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xde, 0xe8": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "fsubp st0, st0",
@@ -20185,9 +20719,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20201,18 +20735,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20230,9 +20766,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20242,11 +20778,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st1, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xe9 /5"
@@ -20257,9 +20793,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20273,18 +20809,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20302,9 +20840,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -20313,11 +20851,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st2, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xea /5"
@@ -20327,9 +20865,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20343,18 +20881,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20372,9 +20912,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20384,11 +20924,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st3, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xeb /5"
@@ -20398,9 +20938,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20414,18 +20954,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20443,9 +20985,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20455,11 +20997,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st4, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xec /5"
@@ -20469,9 +21011,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20485,18 +21027,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20514,9 +21058,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20526,11 +21070,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st5, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xed /5"
@@ -20540,9 +21084,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20556,18 +21100,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20585,9 +21131,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20597,11 +21143,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st6, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xee /5"
@@ -20611,9 +21157,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20627,18 +21173,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20656,9 +21204,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20668,11 +21216,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fsubp st7, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xef /5"
@@ -20682,9 +21230,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20698,18 +21246,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1400]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20727,9 +21277,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20739,11 +21289,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xde, 0xf0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "fdivrp st0, st0",
@@ -20755,9 +21305,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20771,18 +21321,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20800,9 +21352,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20812,11 +21364,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st1, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf1 /6"
@@ -20827,9 +21379,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20843,18 +21395,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20872,9 +21426,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -20883,11 +21437,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st2, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf2 /6"
@@ -20897,9 +21451,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20913,18 +21467,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -20942,9 +21498,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -20954,11 +21510,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st3, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf3 /6"
@@ -20968,9 +21524,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -20984,18 +21540,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21013,9 +21571,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21025,11 +21583,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st4, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf4 /6"
@@ -21039,9 +21597,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21055,18 +21613,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21084,9 +21644,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21096,11 +21656,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st5, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf5 /6"
@@ -21110,9 +21670,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21126,18 +21686,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21155,9 +21717,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21167,11 +21729,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st6, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf6 /6"
@@ -21181,9 +21743,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21197,18 +21759,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21226,9 +21790,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21238,11 +21802,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivrp st7, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf7 /6"
@@ -21252,9 +21816,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21268,18 +21832,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21297,9 +21863,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21309,11 +21875,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "db 0xde, 0xf8": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "fdivp st0, st0",
@@ -21325,9 +21891,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21341,18 +21907,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21370,9 +21938,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21382,11 +21950,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st1, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xf9 /7"
@@ -21397,9 +21965,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21413,18 +21981,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21442,9 +22012,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w23, [x28, #1010]",
         "lsl w21, w21, w20",
         "bic w21, w23, w21",
@@ -21453,11 +22023,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x22, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st2, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xfa /7"
@@ -21467,9 +22037,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21483,18 +22053,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21512,9 +22084,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21524,11 +22096,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st3, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xfb /7"
@@ -21538,9 +22110,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21554,18 +22126,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21583,9 +22157,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21595,11 +22169,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st4, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xfc /7"
@@ -21609,9 +22183,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21625,18 +22199,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21654,9 +22230,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21666,11 +22242,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st5, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xfd /7"
@@ -21680,9 +22256,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21696,18 +22272,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21725,9 +22303,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21737,11 +22315,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st6, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xfe /7"
@@ -21751,9 +22329,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21767,18 +22345,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21796,9 +22376,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21808,11 +22388,11 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fdivp st7, st0": {
-      "ExpectedInstructionCount": 62,
+      "ExpectedInstructionCount": 64,
       "Optimal": "No",
       "Comment": [
         "0xde 11b 0xff /7"
@@ -21822,9 +22402,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21838,18 +22418,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
-        "mov x2, v5.d[0]",
-        "umov w3, v5.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
+        "mov x2, v3.d[0]",
+        "umov w3, v3.h[4]",
         "ldr x4, [x28, #1416]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21867,9 +22449,9 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "ldrb w22, [x28, #1010]",
         "mov w23, #0x1",
         "lsl w23, w23, w20",
@@ -21879,7 +22461,7 @@
         "and w20, w20, #0x7",
         "strb w20, [x28, #747]",
         "add x0, x28, x21, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fild word [rax]": {
@@ -21917,15 +22499,15 @@
         "cmp x21, #0x0 (0)",
         "csel x21, x22, x24, eq",
         "orr x21, x23, x21",
-        "fmov d4, x25",
-        "fmov d5, x21",
-        "mov v4.d[1], v5.d[0]",
+        "fmov d2, x25",
+        "fmov d3, x21",
+        "mov v2.d[1], v3.d[0]",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fisttp word [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /1"
@@ -21933,7 +22515,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -21947,16 +22529,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1208]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -21987,7 +22571,7 @@
       ]
     },
     "fist word [rax]": {
-      "ExpectedInstructionCount": 45,
+      "ExpectedInstructionCount": 47,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /2"
@@ -21995,7 +22579,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22009,16 +22593,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1184]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22041,7 +22627,7 @@
       ]
     },
     "fistp word [rax]": {
-      "ExpectedInstructionCount": 53,
+      "ExpectedInstructionCount": 55,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /3"
@@ -22049,7 +22635,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22063,16 +22649,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1184]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22103,7 +22691,7 @@
       ]
     },
     "fbld tword [rax]": {
-      "ExpectedInstructionCount": 55,
+      "ExpectedInstructionCount": 57,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /4"
@@ -22118,7 +22706,7 @@
         "orr w21, w22, w21",
         "strb w21, [x28, #1010]",
         "strb w20, [x28, #747]",
-        "ldr q4, [x4]",
+        "ldr q2, [x4]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22132,16 +22720,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1384]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22159,15 +22749,15 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
         "add x0, x28, x20, lsl #4",
-        "str q4, [x0, #752]"
+        "str q2, [x0, #752]"
       ]
     },
     "fbstp tword [rax]": {
-      "ExpectedInstructionCount": 57,
+      "ExpectedInstructionCount": 59,
       "Optimal": "No",
       "Comment": [
         "0xdf !11b /6"
@@ -22175,7 +22765,7 @@
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #747]",
         "add x0, x28, x20, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22189,16 +22779,18 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v4.d[0]",
-        "umov w1, v4.h[4]",
+        "mov x0, v2.d[0]",
+        "umov w1, v2.h[4]",
         "ldr x2, [x28, #1376]",
         "blr x2",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22216,11 +22808,11 @@
         "ldp x14, x15, [x28, #88]",
         "ldp x16, x17, [x28, #104]",
         "ldp x19, x29, [x28, #120]",
-        "eor v4.16b, v4.16b, v4.16b",
-        "mov v4.d[0], x0",
-        "mov v4.h[4], w1",
-        "str d4, [x4]",
-        "mov x21, v4.d[1]",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
+        "str d2, [x4]",
+        "mov x21, v2.d[1]",
         "strh w21, [x4, #8]",
         "ldrb w21, [x28, #1010]",
         "mov w22, #0x1",
@@ -22363,7 +22955,7 @@
       ]
     },
     "fucomip st0": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xe8 /5"
@@ -22373,9 +22965,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22389,18 +22981,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22440,7 +23034,7 @@
       ]
     },
     "fucomip st1": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xe9 /5"
@@ -22451,9 +23045,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22467,18 +23061,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22517,7 +23113,7 @@
       ]
     },
     "fucomip st2": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xea /5"
@@ -22527,9 +23123,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22543,18 +23139,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22594,7 +23192,7 @@
       ]
     },
     "fucomip st3": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xeb /5"
@@ -22604,9 +23202,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22620,18 +23218,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22671,7 +23271,7 @@
       ]
     },
     "fucomip st4": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xec /5"
@@ -22681,9 +23281,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22697,18 +23297,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22748,7 +23350,7 @@
       ]
     },
     "fucomip st5": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xed /5"
@@ -22758,9 +23360,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22774,18 +23376,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22825,7 +23429,7 @@
       ]
     },
     "fucomip st6": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xee /5"
@@ -22835,9 +23439,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22851,18 +23455,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22902,7 +23508,7 @@
       ]
     },
     "fucomip st7": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xef /5"
@@ -22912,9 +23518,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -22928,18 +23534,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -22979,7 +23587,7 @@
       ]
     },
     "fcomip st0": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf0 /6"
@@ -22989,9 +23597,9 @@
         "add w21, w20, #0x0 (0)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23005,18 +23613,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23056,7 +23666,7 @@
       ]
     },
     "fcomip st1": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf1 /6"
@@ -23067,9 +23677,9 @@
         "add w22, w20, #0x1 (1)",
         "and w22, w22, #0x7",
         "add x0, x28, x22, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23083,18 +23693,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23133,7 +23745,7 @@
       ]
     },
     "fcomip st2": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf2 /6"
@@ -23143,9 +23755,9 @@
         "add w21, w20, #0x2 (2)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23159,18 +23771,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23210,7 +23824,7 @@
       ]
     },
     "fcomip st3": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf3 /6"
@@ -23220,9 +23834,9 @@
         "add w21, w20, #0x3 (3)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23236,18 +23850,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23287,7 +23903,7 @@
       ]
     },
     "fcomip st4": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf4 /6"
@@ -23297,9 +23913,9 @@
         "add w21, w20, #0x4 (4)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23313,18 +23929,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23364,7 +23982,7 @@
       ]
     },
     "fcomip st5": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf5 /6"
@@ -23374,9 +23992,9 @@
         "add w21, w20, #0x5 (5)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23390,18 +24008,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23441,7 +24061,7 @@
       ]
     },
     "fcomip st6": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf6 /6"
@@ -23451,9 +24071,9 @@
         "add w21, w20, #0x6 (6)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23467,18 +24087,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
@@ -23518,7 +24140,7 @@
       ]
     },
     "fcomip st7": {
-      "ExpectedInstructionCount": 68,
+      "ExpectedInstructionCount": 70,
       "Optimal": "No",
       "Comment": [
         "0xdf 11b 0xf7 /6"
@@ -23528,9 +24150,9 @@
         "add w21, w20, #0x7 (7)",
         "and w21, w21, #0x7",
         "add x0, x28, x21, lsl #4",
-        "ldr q4, [x0, #752]",
+        "ldr q2, [x0, #752]",
         "add x0, x28, x20, lsl #4",
-        "ldr q5, [x0, #752]",
+        "ldr q3, [x0, #752]",
         "stp x4, x5, [x28, #8]",
         "stp x6, x7, [x28, #24]",
         "stp x8, x9, [x28, #40]",
@@ -23544,18 +24166,20 @@
         "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
-        "sub sp, sp, #0xd0 (208)",
+        "sub sp, sp, #0xf0 (240)",
         "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
         "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
         "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
         "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
         "str x30, [x0]",
-        "mov x0, v5.d[0]",
-        "umov w1, v5.h[4]",
-        "mov x2, v4.d[0]",
-        "umov w3, v4.h[4]",
+        "mov x0, v3.d[0]",
+        "umov w1, v3.h[4]",
+        "mov x2, v2.d[0]",
+        "umov w3, v2.h[4]",
         "ldr x4, [x28, #1288]",
         "blr x4",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
         "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",