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https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
MemoryOps: Handle inline values in MemSet() MOPS path
Lets us handle potential inline memset values. Also fixes up the STOS tests to actually ensure all values in the verification step pass.
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@@ -1849,13 +1849,6 @@ DEF_OP(StoreMemTSO) {
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}
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DEF_OP(MemSet) {
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// TODO: A future looking task would be to support this with ARM's MOPS instructions.
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// The 8-bit non-atomic forward path directly matches ARM's SETP/SETM/SETE instruction,
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// while the backward version needs some fixup to convert it to a forward direction.
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//
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// Assuming non-atomicity and non-faulting behaviour, this can accelerate this implementation.
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// Additionally: This is commonly used as a memset to zero. If we know up-front with an inline constant
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// that the value is zero, we can optimize any operation larger than 8-bit down to 8-bit to use the MOPS implementation.
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const auto Op = IROp->C<IR::IROp_MemSet>();
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const bool IsAtomic = CTX->IsMemcpyAtomicTSOEnabled();
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@@ -1937,6 +1930,28 @@ DEF_OP(MemSet) {
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const int32_t SizeDirection = Size * Direction;
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const bool IsBackwards = Direction == -1;
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// Sets the result to the final address written depending on
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// whether or not the memset is forwards or backwards.
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const auto MakeFinalAddress = [&] {
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if (IsBackwards) {
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switch (OpSize) {
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case 1: sub(Dst.X(), MemReg.X(), Length.X()); break;
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case 2: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 1); break;
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case 4: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 2); break;
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case 8: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 3); break;
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default: LOGMAN_MSG_A_FMT("Unhandled MemSet size: {}", OpSize); break;
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}
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} else {
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switch (OpSize) {
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case 1: add(Dst.X(), MemReg.X(), Length.X()); break;
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case 2: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 1); break;
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case 4: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 2); break;
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case 8: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 3); break;
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default: LOGMAN_MSG_A_FMT("Unhandled MemSet size: {}", OpSize); break;
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}
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}
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};
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ARMEmitter::BiDirectionalLabel AgainInternal {};
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ARMEmitter::ForwardLabel DoneInternal {};
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@@ -1945,24 +1960,44 @@ DEF_OP(MemSet) {
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if (!IsAtomic) {
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if (CTX->HostFeatures.SupportsMOPS) {
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if (SubRegSize == ARMEmitter::SubRegSize::i8Bit) {
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const bool Is8Bit = SubRegSize == ARMEmitter::SubRegSize::i8Bit;
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// We can handle 8-bit memsets and any other size that happens
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// to be using an inlined zero value (resulting in the use of ZR).
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//
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// NOTE:
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// Strictly speaking, this can also be trivially expanded to handle other sizes
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// that happen to use any value that could fit inside a byte if the need
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// arises. This does increase branching and code generation, however, since
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// we'd still need to emit the fallback in the event a value for a larger size
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// falls outside the range of a byte instead of only generating the MOPS code.
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if (Is8Bit || Value == ARMEmitter::Reg::zr) {
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// If we're performing a non-byte-sized zeroing operation then we need to
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// scale the counter accordingly. (e.g. a 64-bit memset of size 2 needs to
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// be turned into an 8-bit memset of size 16)
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if (!Is8Bit) {
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lsl(ARMEmitter::Size::i64Bit, TMP1, TMP1, FEXCore::ToUnderlying(SubRegSize));
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}
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// If backwards, then we need to adjust the starting address because
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// set{p, m, e} memset forwards, so we need to slide this bad boy
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// back like: address - (count + 1).
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// back like: (address - count) + 1.
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//
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// This lets us offset the address such that we can treat a backwards
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// memset as if it were a forwards one.
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if (IsBackwards) {
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sub(TMP2, TMP2, TMP1);
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add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1);
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}
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// Unfortunately set operations fiddle with NZCV, so we need to preserve it.
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mrs(TMP3, ARMEmitter::SystemRegister::NZCV);
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setp(TMP2, TMP1, Value.X());
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setm(TMP2, TMP1, Value.X());
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sete(TMP2, TMP1, Value.X());
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msr(ARMEmitter::SystemRegister::NZCV, TMP3);
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if (IsBackwards) {
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sub(Dst.X(), MemReg.X(), Length.X());
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} else {
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add(Dst.X(), MemReg.X(), Length.X());
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}
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MakeFinalAddress();
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(void)Bind(&DoneInternal);
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return;
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@@ -2028,23 +2063,7 @@ DEF_OP(MemSet) {
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(void)Bind(&DoneInternal);
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if (SizeDirection >= 0) {
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switch (OpSize) {
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case 1: add(Dst.X(), MemReg.X(), Length.X()); break;
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case 2: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 1); break;
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case 4: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 2); break;
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case 8: add(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 3); break;
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default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, OpSize); break;
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}
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} else {
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switch (OpSize) {
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case 1: sub(Dst.X(), MemReg.X(), Length.X()); break;
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case 2: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 1); break;
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case 4: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 2); break;
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case 8: sub(Dst.X(), MemReg.X(), Length.X(), ARMEmitter::ShiftType::LSL, 3); break;
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default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, OpSize); break;
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}
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}
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MakeFinalAddress();
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};
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if (DirectionIsInline) {
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+20
-16
@@ -1,6 +1,10 @@
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%ifdef CONFIG
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{
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"Match": "All",
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"RegData": {
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"RDI": "0xE8000020",
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"R11": "0xDAD10"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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@@ -14,7 +18,7 @@ mov rax, 0xDEADBEEFBAD0DAD1
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mov rdi, 0xe8000000
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; How many elements we want to store
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mov rcx, 0x0
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mov rcx, 0x10
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; Direction to increment (Increment when cleared)
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cld
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@@ -27,35 +31,35 @@ mov r10, 0xe8000000
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movzx r12, word [r10 + 0]
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add r11, r12
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movzx r12, word [r10 + 1]
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add r11, r12
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movzx r12, word [r10 + 2]
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add r11, r12
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movzx r12, word [r10 + 3]
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add r11, r12
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movzx r12, word [r10 + 4]
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add r11, r12
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movzx r12, word [r10 + 5]
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add r11, r12
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movzx r12, word [r10 + 6]
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add r11, r12
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movzx r12, word [r10 + 7]
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add r11, r12
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movzx r12, word [r10 + 8]
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add r11, r12
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movzx r12, word [r10 + 9]
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add r11, r12
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movzx r12, word [r10 + 10]
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add r11, r12
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movzx r12, word [r10 + 11]
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add r11, r12
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movzx r12, word [r10 + 12]
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add r11, r12
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movzx r12, word [r10 + 13]
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add r11, r12
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movzx r12, word [r10 + 14]
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add r11, r12
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movzx r12, word [r10 + 15]
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movzx r12, word [r10 + 16]
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add r11, r12
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movzx r12, word [r10 + 18]
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add r11, r12
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movzx r12, word [r10 + 20]
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add r11, r12
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movzx r12, word [r10 + 22]
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add r11, r12
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movzx r12, word [r10 + 24]
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add r11, r12
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movzx r12, word [r10 + 26]
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add r11, r12
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movzx r12, word [r10 + 28]
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add r11, r12
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movzx r12, word [r10 + 30]
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add r11, r12
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hlt
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@@ -4,7 +4,8 @@
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"RegData": {
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"RAX": "0",
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"RCX": "0",
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"RDI": "0xE8000100"
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"RDI": "0xE8000100",
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"R11": "0"
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},
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"MemoryRegions": {
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@@ -4,7 +4,8 @@
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"RegData": {
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"RAX": "0",
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"RCX": "0",
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"RDI": "0xE8000100"
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"RDI": "0xE8000100",
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"R11": "0"
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},
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"MemoryRegions": {
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@@ -1,6 +1,10 @@
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%ifdef CONFIG
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{
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"Match": "All",
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"RegData": {
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"RDI": "0xE8000020",
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"R11": "0xDAD10"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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@@ -14,7 +18,7 @@ mov rax, 0xDEADBEEFBAD0DAD1
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mov rdi, 0xe8000000
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; How many elements we want to store
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mov rcx, 0x0
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mov rcx, 0x10
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; Direction to increment (Increment when cleared)
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cld
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@@ -27,35 +31,35 @@ mov r10, 0xe8000000
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movzx r12, word [r10 + 0]
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add r11, r12
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movzx r12, word [r10 + 1]
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add r11, r12
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movzx r12, word [r10 + 2]
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add r11, r12
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movzx r12, word [r10 + 3]
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add r11, r12
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movzx r12, word [r10 + 4]
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add r11, r12
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movzx r12, word [r10 + 5]
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add r11, r12
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movzx r12, word [r10 + 6]
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add r11, r12
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movzx r12, word [r10 + 7]
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add r11, r12
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movzx r12, word [r10 + 8]
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add r11, r12
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movzx r12, word [r10 + 9]
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add r11, r12
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movzx r12, word [r10 + 10]
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add r11, r12
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movzx r12, word [r10 + 11]
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add r11, r12
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movzx r12, word [r10 + 12]
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add r11, r12
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movzx r12, word [r10 + 13]
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add r11, r12
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movzx r12, word [r10 + 14]
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add r11, r12
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movzx r12, word [r10 + 15]
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movzx r12, word [r10 + 16]
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add r11, r12
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movzx r12, word [r10 + 18]
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add r11, r12
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movzx r12, word [r10 + 20]
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add r11, r12
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movzx r12, word [r10 + 22]
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add r11, r12
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movzx r12, word [r10 + 24]
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add r11, r12
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movzx r12, word [r10 + 26]
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add r11, r12
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movzx r12, word [r10 + 28]
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add r11, r12
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movzx r12, word [r10 + 30]
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add r11, r12
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hlt
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