IR: Add ccmn

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -240,6 +240,26 @@ ARMEmitter::Condition MapSelectCC(IR::CondClassType Cond) {
   }
 }
 
+DEF_OP(CondAddNZCV) {
+  auto Op = IROp->C<IR::IROp_CondAddNZCV>();
+  const IR::OpSize OpSize = Op->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  ARMEmitter::StatusFlags Flags = (ARMEmitter::StatusFlags)Op->FalseNZCV;
+  uint64_t Const = 0;
+  auto Src1 = IsInlineConstant(Op->Src1, &Const) ? ARMEmitter::Reg::zr :
+                                                   GetReg(Op->Src1.ID());
+  LOGMAN_THROW_A_FMT(Const == 0, "Unsupported inline constant");
+
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    ccmn(EmitSize, Src1, Const, Flags, MapSelectCC(Op->Cond));
+  } else {
+    ccmn(EmitSize, Src1, GetReg(Op->Src2.ID()), Flags, MapSelectCC(Op->Cond));
+  }
+}
+
 DEF_OP(Neg) {
   auto Op = IROp->C<IR::IROp_Neg>();
   const uint8_t OpSize = IROp->Size;

FEXCore/Source/Interface/IR/IR.json

@@ -968,6 +968,13 @@
         "Desc": ["Rotate, mask, and insert into NZCV on FlagM platforms"],
         "HasSideEffects": true
       },
+      "CondAddNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": {
+        "Desc": ["If condition is true, set NZCV per sum of GPRs, else force NZCV to a constant."],
+        "HasSideEffects": true,
+        "EmitValidation": [
+          "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
       "AdcNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2": {
         "Desc": ["Set NZCV for the sum of two GPRs and carry-in given as NZCV"],
         "HasSideEffects": true,

FEXCore/Source/Interface/IR/Passes/ConstProp.cpp

@@ -1010,6 +1010,31 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
 
         break;
       }
+      case OP_CONDADDNZCV:
+      {
+        auto Op = IROp->C<IR::IROp_CondAddNZCV>();
+
+        uint64_t Constant2{};
+        if (IREmit->IsValueConstant(Op->Header.Args[1], &Constant2)) {
+          if (IsImmAddSub(Constant2)) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[1]));
+
+            IREmit->ReplaceNodeArgument(CodeNode, 1, CreateInlineConstant(IREmit, Constant2));
+
+            Changed = true;
+          }
+        }
+
+        uint64_t Constant1{};
+        if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
+          if (Constant1 == 0) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[0]));
+            IREmit->ReplaceNodeArgument(CodeNode, 0, CreateInlineConstant(IREmit, 0));
+            Changed = true;
+          }
+        }
+        break;
+      }
       case OP_TESTNZ:
       {
         auto Op = IROp->C<IR::IROp_TestNZ>();