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Merge pull request #4820 from bylaws/neg

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AtomicOps: Reimplement AtomicNeg using 8.1 CAS atomics
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Ryan Houdek authored and GitHub committed 2025-09-03 15:23:40 -07:00
2 parents e126cecb16 7c9c97f2b9
commit 8009f4a6ee
3 files changed
+68 -39
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FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp
+20 -7
View File
@@ -322,13 +322,26 @@ DEF_OP(AtomicFetchNeg) {
auto MemSrc = GetReg(Op->Addr);
ARMEmitter::BackwardLabel LoopTop;
Bind(&LoopTop);
ldaxr(SubEmitSize, TMP2, MemSrc);
neg(EmitSize, TMP3, TMP2);
stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
cbnz(EmitSize, TMP4, &LoopTop);
mov(EmitSize, GetReg(Node), TMP2.R());
if (CTX->HostFeatures.SupportsAtomics) {
// Use a CAS loop to avoid needing to emulate unaligned LLSC atomics
ldr(SubEmitSize, TMP2, MemSrc);
ARMEmitter::BackwardLabel LoopTop;
Bind(&LoopTop);
mov(EmitSize, TMP4, TMP2);
neg(EmitSize, TMP3, TMP2);
casal(SubEmitSize, TMP2, TMP3, MemSrc);
sub(EmitSize, TMP3, TMP2, TMP4);
cbnz(EmitSize, TMP3, &LoopTop);
mov(EmitSize, GetReg(Node), TMP2.R());
} else {
ARMEmitter::BackwardLabel LoopTop;
Bind(&LoopTop);
ldaxr(SubEmitSize, TMP2, MemSrc);
neg(EmitSize, TMP3, TMP2);
stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
cbnz(EmitSize, TMP4, &LoopTop);
mov(EmitSize, GetReg(Node), TMP2.R());
}
}
DEF_OP(TelemetrySetValue) {
unittests/InstructionCountCI/Atomics.json
+24 -16
View File
@@ -1519,51 +1519,59 @@
]
},
"lock neg byte [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"ldaxrb w1, [x4]",
"ldrb w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxrb w3, w2, [x4]",
"cbnz w3, #-0xc",
"casalb w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #24",
"neg w26, w27"
]
},
"lock neg word [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxrh w1, [x4]",
"ldrh w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxrh w3, w2, [x4]",
"cbnz w3, #-0xc",
"casalh w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #16",
"neg w26, w27"
]
},
"lock neg dword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr w1, [x4]",
"ldr w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxr w3, w2, [x4]",
"cbnz w3, #-0xc",
"casal w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"negs w26, w27"
]
},
"lock neg qword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr x1, [x4]",
"ldr x1, [x4]",
"mov x3, x1",
"neg x2, x1",
"stlxr w3, x2, [x4]",
"cbnz x3, #-0xc",
"casal x1, x2, [x4]",
"sub x2, x1, x3",
"cbnz x2, #-0x10",
"mov x27, x1",
"negs x26, x27"
]
unittests/InstructionCountCI/FlagM/Atomics.json
+24 -16
View File
@@ -1322,51 +1322,59 @@
]
},
"lock neg byte [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"ldaxrb w1, [x4]",
"ldrb w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxrb w3, w2, [x4]",
"cbnz w3, #-0xc",
"casalb w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #24",
"neg w26, w27"
]
},
"lock neg word [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxrh w1, [x4]",
"ldrh w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxrh w3, w2, [x4]",
"cbnz w3, #-0xc",
"casalh w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #16",
"neg w26, w27"
]
},
"lock neg dword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr w1, [x4]",
"ldr w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"stlxr w3, w2, [x4]",
"cbnz w3, #-0xc",
"casal w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"negs w26, w27"
]
},
"lock neg qword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr x1, [x4]",
"ldr x1, [x4]",
"mov x3, x1",
"neg x2, x1",
"stlxr w3, x2, [x4]",
"cbnz x3, #-0xc",
"casal x1, x2, [x4]",
"sub x2, x1, x3",
"cbnz x2, #-0x10",
"mov x27, x1",
"negs x26, x27"
]