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https://github.com/FEX-Emu/FEX.git
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InstcountCI: Update
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8 files changed
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@@ -17,7 +17,7 @@
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"Instructions": {
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"The Sims 1 hot block": {
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"x86InstructionCount": 47,
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"ExpectedInstructionCount": 106,
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"ExpectedInstructionCount": 105,
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"Comment": [
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"Hottest in-game block from The Sims 1, Legacy Collection",
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"Consumed 6.13% of a CPU core on Oryon-1",
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@@ -88,26 +88,25 @@
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"ldapur w4, [x20]",
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"nop",
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"eor w4, w4, w9",
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"mov w20, #0x0",
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"sub w21, w9, #0x4 (4)",
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"sub w20, w9, #0x4 (4)",
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"nop",
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"stlur w4, [x21]",
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"add w21, w9, #0x8 (8)",
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"ldapur w5, [x21]",
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"stlur w4, [x20]",
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"add w20, w9, #0x8 (8)",
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"ldapur w5, [x20]",
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"nop",
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"str w6, [x8, #-4]!",
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"str w10, [x8, #-4]!",
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"add w21, w9, #0x18 (24)",
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"ldapur w10, [x21]",
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"add w20, w9, #0x18 (24)",
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"ldapur w10, [x20]",
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"nop",
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"str w11, [x8, #-4]!",
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"mov x11, x7",
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"sub w21, w9, #0x184 (388)",
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"sub w20, w9, #0x184 (388)",
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"nop",
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"stlur w5, [x21]",
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"sub w21, w9, #0x180 (384)",
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"stlur w5, [x20]",
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"sub w20, w9, #0x180 (384)",
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"nop",
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"stlur w20, [x21]",
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"stlur wzr, [x20]",
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"sub w7, w9, #0x16c (364)",
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"add w10, w10, #0x28 (40)",
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"mov w5, #0x6",
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@@ -14,11 +14,10 @@
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},
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"Instructions": {
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"sgdt [rax]": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP7 0x0F 0x1 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"strh w20, [x4]",
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"strh wzr, [x4]",
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"mov x20, #0xfffffffffffe0000",
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"stur x20, [x4, #2]"
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]
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@@ -3994,13 +3994,13 @@
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"lsr w21, w21, #7",
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"and w21, w21, #0x1",
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"cmp x21, #0x0 (0)",
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"csel x21, x23, x20, eq",
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"orr w21, w22, w21, lsl #14",
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"str w21, [x4, #8]",
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"str w20, [x4, #12]",
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"str w20, [x4, #16]",
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"str w20, [x4, #20]",
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"str w20, [x4, #24]",
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"csel x20, x23, x20, eq",
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"orr w20, w22, w20, lsl #14",
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"str w20, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"msr nzcv, x24"
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]
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},
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@@ -11600,13 +11600,13 @@
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"lsr w22, w22, #7",
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"and w22, w22, #0x1",
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"cmp x22, #0x0 (0)",
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"csel x22, x24, x21, eq",
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"orr w22, w23, w22, lsl #14",
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"str w22, [x4, #8]",
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"str w21, [x4, #12]",
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"str w21, [x4, #16]",
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"str w21, [x4, #20]",
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"str w21, [x4, #24]",
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"csel x21, x24, x21, eq",
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"orr w21, w23, w21, lsl #14",
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"str w21, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"stur q2, [x4, #28]",
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@@ -1656,13 +1656,13 @@
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"lsr w21, w21, #7",
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"and w21, w21, #0x1",
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"cmp x21, #0x0 (0)",
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"csel x21, x23, x20, eq",
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"orr w21, w22, w21, lsl #14",
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"str w21, [x4, #8]",
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"str w20, [x4, #12]",
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"str w20, [x4, #16]",
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"str w20, [x4, #20]",
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"str w20, [x4, #24]",
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"csel x20, x23, x20, eq",
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"orr w20, w22, w20, lsl #14",
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"str w20, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"msr nzcv, x24"
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]
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},
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@@ -6634,10 +6634,10 @@
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"csel x22, x24, x21, eq",
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"orr w22, w23, w22, lsl #14",
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"str w22, [x4, #8]",
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"str w21, [x4, #12]",
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"str w21, [x4, #16]",
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"str w21, [x4, #20]",
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"str w21, [x4, #24]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"add x0, x28, x20, lsl #4",
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"ldr d2, [x0, #1040]",
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"mrs x0, nzcv",
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@@ -3049,35 +3049,31 @@
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]
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},
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"mov byte [rax], 0": {
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"ExpectedInstructionCount": 2,
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"ExpectedInstructionCount": 1,
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"Comment": "GROUP11 0xc6 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"strb w20, [x4]"
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"strb wzr, [x4]"
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]
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},
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"mov word [rax], 0": {
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"ExpectedInstructionCount": 2,
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"ExpectedInstructionCount": 1,
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"Comment": "GROUP11 0xc7 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"strh w20, [x4]"
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"strh wzr, [x4]"
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]
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},
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"mov dword [rax], 0": {
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"ExpectedInstructionCount": 2,
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"ExpectedInstructionCount": 1,
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"Comment": "GROUP11 0xc7 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"str w20, [x4]"
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"str wzr, [x4]"
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]
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},
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"mov qword [rax], 0": {
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"ExpectedInstructionCount": 2,
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"ExpectedInstructionCount": 1,
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"Comment": "GROUP11 0xc7 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"str x20, [x4]"
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"str xzr, [x4]"
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]
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},
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"mov byte [rax], 1": {
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@@ -14,11 +14,10 @@
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},
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"Instructions": {
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"sgdt [rax]": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP7 0x0F 0x1 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x0",
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"strh w20, [x4]",
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"strh wzr, [x4]",
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"mov x20, #0xfffffffffffe0000",
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"stur x20, [x4, #2]"
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]
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@@ -3993,13 +3993,13 @@
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"lsr w21, w21, #7",
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"and w21, w21, #0x1",
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"cmp x21, #0x0 (0)",
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"csel x21, x23, x20, eq",
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"orr w21, w22, w21, lsl #14",
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"str w21, [x4, #8]",
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"str w20, [x4, #12]",
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"str w20, [x4, #16]",
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"str w20, [x4, #20]",
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"str w20, [x4, #24]",
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"csel x20, x23, x20, eq",
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"orr w20, w22, w20, lsl #14",
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"str w20, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"msr nzcv, x24"
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]
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},
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@@ -11631,13 +11631,13 @@
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"lsr w22, w22, #7",
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"and w22, w22, #0x1",
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"cmp x22, #0x0 (0)",
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"csel x22, x24, x21, eq",
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"orr w22, w23, w22, lsl #14",
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"str w22, [x4, #8]",
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"str w21, [x4, #12]",
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"str w21, [x4, #16]",
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"str w21, [x4, #20]",
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"str w21, [x4, #24]",
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"csel x21, x24, x21, eq",
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"orr w21, w23, w21, lsl #14",
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"str w21, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"stur q2, [x4, #28]",
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@@ -1673,13 +1673,13 @@
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"lsr w21, w21, #7",
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"and w21, w21, #0x1",
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"cmp x21, #0x0 (0)",
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"csel x21, x23, x20, eq",
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"orr w21, w22, w21, lsl #14",
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"str w21, [x4, #8]",
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"str w20, [x4, #12]",
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"str w20, [x4, #16]",
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"str w20, [x4, #20]",
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"str w20, [x4, #24]",
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"csel x20, x23, x20, eq",
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"orr w20, w22, w20, lsl #14",
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"str w20, [x4, #8]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"msr nzcv, x24"
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]
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},
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@@ -6673,10 +6673,10 @@
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"csel x22, x24, x21, eq",
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"orr w22, w23, w22, lsl #14",
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"str w22, [x4, #8]",
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"str w21, [x4, #12]",
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"str w21, [x4, #16]",
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"str w21, [x4, #20]",
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"str w21, [x4, #24]",
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"str wzr, [x4, #12]",
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"str wzr, [x4, #16]",
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"str wzr, [x4, #20]",
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"str wzr, [x4, #24]",
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"add x0, x28, x20, lsl #4",
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"ldr d2, [x0, #1040]",
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"mrs x0, nzcv",
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