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Merge pull request #1694 from Sonicadvance1/fix_RCPC

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Arm64: Fixes AtomicSwap
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Ryan Houdek authored and GitHub committed 2022-05-09 23:30:34 -07:00
2 parents b5ae9e4c97 e90164b519
commit 70988ccfee
2 files changed
+5 -9
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External/FEXCore/Source/Interface/Core/HostFeatures.cpp
Vendored
+1 -5
View File
@@ -59,11 +59,7 @@ HostFeatures::HostFeatures() {
// Only supported when FEAT_AFP is supported
SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
// RCPC is bugged on Snapdragon 865
// Causes glibc cond16 test to immediately throw assert
// __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
// We need to get the CPU's cache line size
// We expect sane targets that have correct cacheline sizes across clusters
External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
Vendored
+4 -4
View File
@@ -509,10 +509,10 @@ DEF_OP(AtomicSwap) {
if (CTX->HostFeatures.SupportsAtomics) {
mov(TMP2, GetReg<RA_64>(Op->Value.ID()));
switch (IROp->Size) {
case 1: swplb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 4: swpl(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 8: swpl(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
case 1: swpalb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 2: swpalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 4: swpal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
case 8: swpal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
default: LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
}
}