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InstcountCI: Update

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Ryan Houdek committed 2025-10-04 02:46:27 -07:00
1 parent f52bcb49ab
commit 6f83b10af6
2 files changed
+54 -22
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unittests/InstructionCountCI/Secondary_OpSize.json
+25 -11
View File
@@ -799,51 +799,65 @@
]
},
"extrq xmm0, 64, 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"fmov d2, x20",
"and v16.16b, v16.16b, v2.16b"
]
},
"extrq xmm0, 32, 32": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"ushr v2.2d, v16.2d, #32",
"movi v3.2d, #0x0",
"mov w20, #0xffffffff",
"mov v3.d[0], x20",
"fmov d3, x20",
"and v16.16b, v2.16b, v3.16b"
]
},
"extrq xmm0, 0, 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"SSE4a",
"0x66 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"fmov d2, x20",
"and v16.16b, v16.16b, v2.16b"
]
},
"extrq xmm0, xmm1": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 16,
"Comment": [
"SSE4a",
"0x66 0x0f 0x79"
],
"ExpectedArm64ASM": [
"mov w0, #0x3f",
"dup v2.2d, x0",
"and v3.8b, v17.8b, v2.8b",
"ushr v4.2d, v17.2d, #8",
"and v2.8b, v4.8b, v2.8b",
"neg v0.2d, v2.2d",
"ushl v2.2d, v16.2d, v0.2d",
"mov x20, v3.d[0]",
"mrs x21, nzcv",
"mov x0, #0xffffffffffffffff",
"cmp x20, #0x0 (0)",
"lsl x1, x0, x20",
"csinv x20, x0, x1, eq",
"fmov d3, x20",
"and v16.16b, v2.16b, v3.16b",
"msr nzcv, x21"
]
},
"haddpd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+29 -11
View File
@@ -320,15 +320,14 @@
]
},
"insertq xmm0, xmm1, 0, 0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"fmov d2, x20",
"and v3.8b, v17.8b, v2.8b",
"mvn v2.16b, v2.16b",
"and v2.8b, v16.8b, v2.8b",
@@ -336,15 +335,14 @@
]
},
"insertq xmm0, xmm1, 64, 0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov x20, #0xffffffffffffffff",
"mov v2.d[0], x20",
"fmov d2, x20",
"and v3.8b, v17.8b, v2.8b",
"mvn v2.16b, v2.16b",
"and v2.8b, v16.8b, v2.8b",
@@ -352,15 +350,14 @@
]
},
"insertq xmm0, xmm1, 32, 32": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": [
"SSE4a",
"0xf2 0x0f 0x78"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov w20, #0xffffffff",
"mov v2.d[0], x20",
"fmov d2, x20",
"and v3.8b, v17.8b, v2.8b",
"shl v3.2d, v3.2d, #32",
"shl v2.2d, v2.2d, #32",
@@ -370,11 +367,32 @@
]
},
"insertq xmm0, xmm1": {
"ExpectedInstructionCount": 7,
"Skip": "Yes",
"ExpectedInstructionCount": 20,
"Comment": [
"SSE4a",
"0xf2 0x0f 0x79"
],
"ExpectedArm64ASM": [
"dup v2.2d, v17.d[1]",
"mov w0, #0x3f",
"dup v3.2d, x0",
"and v4.8b, v2.8b, v3.8b",
"ushr v2.2d, v2.2d, #8",
"and v2.8b, v2.8b, v3.8b",
"mov x20, v4.d[0]",
"mrs x21, nzcv",
"mov x0, #0xffffffffffffffff",
"cmp x20, #0x0 (0)",
"lsl x1, x0, x20",
"csinv x20, x0, x1, eq",
"fmov d3, x20",
"and v4.16b, v17.16b, v3.16b",
"ushl v4.2d, v4.2d, v2.2d",
"ushl v3.2d, v3.2d, v2.2d",
"mvn v2.16b, v3.16b",
"and v2.8b, v16.8b, v2.8b",
"orr v16.8b, v2.8b, v4.8b",
"msr nzcv, x21"
]
},
"haddps xmm0, xmm1": {