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InstcountCI: Remove sha

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Ryan Houdek committed 2025-07-25 12:22:13 -07:00
1 parent 0d69e88d53
commit 6d83a195c6
2 files changed
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unittests/InstructionCountCI/H0F38.json
-193
View File
@@ -693,199 +693,6 @@
"rev32 v16.8h, v2.8h"
]
},
"sha1nexte xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Comment": [
"0x66 0x0f 0x38 0xc8"
],
"ExpectedArm64ASM": [
"shl v2.4s, v16.4s, #30",
"usra v2.4s, v16.4s, #2",
"add v2.4s, v17.4s, v2.4s",
"mov v16.16b, v17.16b",
"mov v16.s[3], v2.s[3]"
]
},
"sha1msg1 xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x38 0xc9"
],
"ExpectedArm64ASM": [
"ext v2.16b, v17.16b, v16.16b, #8",
"eor v16.16b, v16.16b, v2.16b"
]
},
"sha1msg2 xmm0, xmm1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0x66 0x0f 0x38 0xca"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v2.16b, v2.16b, v17.16b, #12",
"eor v2.16b, v16.16b, v2.16b",
"shl v3.4s, v2.4s, #1",
"usra v3.4s, v2.4s, #31",
"dup v2.4s, v3.s[3]",
"eor v2.16b, v16.16b, v2.16b",
"shl v4.4s, v2.4s, #1",
"usra v4.4s, v2.4s, #31",
"mov v16.16b, v3.16b",
"mov v16.s[0], v4.s[0]"
]
},
"sha256rnds2 xmm0, xmm1": {
"ExpectedInstructionCount": 56,
"Comment": [
"0x66 0x0f 0x38 0xcb"
],
"ExpectedArm64ASM": [
"mov w20, v17.s[1]",
"mov w21, v17.s[0]",
"mov w22, v16.s[1]",
"and w23, w20, w21",
"bic w22, w22, w20",
"eor w22, w23, w22",
"ror w23, w20, #6",
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v16.s[0]",
"add w22, w22, w23",
"mov w23, v16.s[0]",
"add w22, w22, w23",
"mov w23, v17.s[3]",
"mov w24, v17.s[2]",
"mov w30, v16.s[3]",
"and w18, w24, w30",
"orr w30, w24, w30",
"and w30, w23, w30",
"orr w30, w30, w18",
"add w30, w22, w30",
"ror w18, w23, #2",
"eor w18, w18, w23, ror #13",
"eor w18, w18, w23, ror #22",
"add w30, w30, w18",
"mov w18, v16.s[2]",
"add w22, w22, w18",
"and w20, w22, w20",
"bic w21, w21, w22",
"eor w20, w20, w21",
"ror w21, w22, #6",
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v16.s[1]",
"add w20, w20, w21",
"mov w21, v16.s[1]",
"add w20, w20, w21",
"and w21, w23, w24",
"orr w23, w23, w24",
"and w23, w30, w23",
"orr w21, w23, w21",
"add w21, w20, w21",
"ror w23, w30, #2",
"eor w23, w23, w30, ror #13",
"eor w23, w23, w30, ror #22",
"add w21, w21, w23",
"mov w23, v16.s[3]",
"add w20, w20, w23",
"mov v2.16b, v16.16b",
"mov v2.s[3], w21",
"mov v2.s[2], w30",
"mov v2.s[1], w20",
"mov v16.16b, v2.16b",
"mov v16.s[0], w22"
]
},
"sha256msg1 xmm0, xmm1": {
"ExpectedInstructionCount": 35,
"Comment": [
"0x66 0x0f 0x38 0xcc"
],
"ExpectedArm64ASM": [
"mov w20, v17.s[0]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"ror w30, w20, #7",
"ror w18, w20, #18",
"eor w30, w30, w18",
"lsr w20, w20, #3",
"eor w20, w30, w20",
"add w20, w21, w20",
"ror w30, w21, #7",
"ror w18, w21, #18",
"eor w30, w30, w18",
"lsr w21, w21, #3",
"eor w21, w30, w21",
"add w21, w22, w21",
"ror w30, w22, #7",
"ror w18, w22, #18",
"eor w30, w30, w18",
"lsr w22, w22, #3",
"eor w22, w30, w22",
"add w22, w23, w22",
"ror w30, w23, #7",
"ror w18, w23, #18",
"eor w30, w30, w18",
"lsr w23, w23, #3",
"eor w23, w30, w23",
"add w23, w24, w23",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w21",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w23"
]
},
"sha256msg2 xmm0, xmm1": {
"ExpectedInstructionCount": 36,
"Comment": [
"0x66 0x0f 0x38 0xcd"
],
"ExpectedArm64ASM": [
"mov w20, v17.s[2]",
"mov w21, v17.s[3]",
"mov w22, v16.s[0]",
"ror w23, w20, #17",
"ror w24, w20, #19",
"eor w23, w23, w24",
"lsr w20, w20, #10",
"eor w20, w23, w20",
"add w20, w22, w20",
"mov w22, v16.s[1]",
"ror w23, w21, #17",
"ror w24, w21, #19",
"eor w23, w23, w24",
"lsr w21, w21, #10",
"eor w21, w23, w21",
"add w21, w22, w21",
"mov w22, v16.s[2]",
"ror w23, w20, #17",
"ror w24, w20, #19",
"eor w23, w23, w24",
"lsr w24, w20, #10",
"eor w23, w23, w24",
"add w22, w22, w23",
"mov w23, v16.s[3]",
"ror w24, w21, #17",
"ror w30, w21, #19",
"eor w24, w24, w30",
"lsr w30, w21, #10",
"eor w24, w24, w30",
"add w23, w23, w24",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
},
"movbe ax, word [rbx]": {
"ExpectedInstructionCount": 3,
"Comment": [
unittests/InstructionCountCI/H0F3A.json
-256
View File
@@ -1348,262 +1348,6 @@
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"sha1rnds4 xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 57,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"mov w20, #0x7999",
"movk w20, #0x5a82, lsl #16",
"mov w21, v17.s[3]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w30, v16.s[0]",
"and w18, w23, w24",
"bic w20, w30, w23",
"eor w20, w18, w20",
"ror w18, w22, #27",
"add w20, w20, w18",
"add w20, w20, w21",
"mov w21, #0x7999",
"movk w21, #0x5a82, lsl #16",
"add w20, w20, w21",
"ror w23, w23, #2",
"mov w18, v17.s[2]",
"add w30, w18, w30",
"and w18, w22, w23",
"bic w21, w24, w22",
"eor w21, w18, w21",
"ror w18, w20, #27",
"add w21, w21, w18",
"add w21, w21, w30",
"mov w30, #0x7999",
"movk w30, #0x5a82, lsl #16",
"add w21, w21, w30",
"ror w22, w22, #2",
"mov w18, v17.s[1]",
"add w24, w18, w24",
"and w18, w20, w22",
"bic w30, w23, w20",
"eor w30, w18, w30",
"ror w18, w21, #27",
"add w30, w30, w18",
"add w24, w30, w24",
"mov w30, #0x7999",
"movk w30, #0x5a82, lsl #16",
"add w24, w24, w30",
"ror w20, w20, #2",
"mov w18, v17.s[0]",
"add w23, w18, w23",
"and w18, w21, w20",
"bic w22, w22, w21",
"eor w22, w18, w22",
"ror w18, w24, #27",
"add w22, w22, w18",
"add w22, w22, w23",
"add w22, w22, w30",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
},
"sha1rnds4 xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 53,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"mov w20, #0xeba1",
"movk w20, #0x6ed9, lsl #16",
"mov w21, v17.s[3]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w30, v16.s[0]",
"eor w18, w23, w24",
"eor w18, w18, w30",
"ror w20, w22, #27",
"add w20, w18, w20",
"add w20, w20, w21",
"mov w21, #0xeba1",
"movk w21, #0x6ed9, lsl #16",
"add w20, w20, w21",
"ror w23, w23, #2",
"mov w18, v17.s[2]",
"add w30, w18, w30",
"eor w18, w22, w23",
"eor w18, w18, w24",
"ror w21, w20, #27",
"add w21, w18, w21",
"add w21, w21, w30",
"mov w30, #0xeba1",
"movk w30, #0x6ed9, lsl #16",
"add w21, w21, w30",
"ror w22, w22, #2",
"mov w18, v17.s[1]",
"add w24, w18, w24",
"eor w18, w20, w22",
"eor w18, w18, w23",
"ror w30, w21, #27",
"add w30, w18, w30",
"add w24, w30, w24",
"mov w30, #0xeba1",
"movk w30, #0x6ed9, lsl #16",
"add w24, w24, w30",
"ror w20, w20, #2",
"mov w18, v17.s[0]",
"add w23, w18, w23",
"eor w18, w21, w20",
"eor w22, w18, w22",
"ror w18, w24, #27",
"add w22, w22, w18",
"add w22, w22, w23",
"add w22, w22, w30",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
},
"sha1rnds4 xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"mov w20, #0xbcdc",
"movk w20, #0x8f1b, lsl #16",
"mov w21, v17.s[3]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w30, v16.s[0]",
"and w18, w24, w30",
"orr w20, w24, w30",
"and w20, w23, w20",
"orr w20, w20, w18",
"ror w18, w22, #27",
"add w20, w20, w18",
"add w20, w20, w21",
"mov w21, #0xbcdc",
"movk w21, #0x8f1b, lsl #16",
"add w20, w20, w21",
"ror w23, w23, #2",
"mov w18, v17.s[2]",
"add w30, w18, w30",
"and w18, w23, w24",
"orr w21, w23, w24",
"and w21, w22, w21",
"orr w21, w21, w18",
"ror w18, w20, #27",
"add w21, w21, w18",
"add w21, w21, w30",
"mov w30, #0xbcdc",
"movk w30, #0x8f1b, lsl #16",
"add w21, w21, w30",
"ror w22, w22, #2",
"mov w18, v17.s[1]",
"add w24, w18, w24",
"and w18, w22, w23",
"orr w30, w22, w23",
"and w30, w20, w30",
"orr w30, w30, w18",
"ror w18, w21, #27",
"add w30, w30, w18",
"add w24, w30, w24",
"mov w30, #0xbcdc",
"movk w30, #0x8f1b, lsl #16",
"add w24, w24, w30",
"ror w20, w20, #2",
"mov w18, v17.s[0]",
"add w23, w18, w23",
"and w18, w20, w22",
"orr w22, w20, w22",
"and w22, w21, w22",
"orr w22, w22, w18",
"ror w18, w24, #27",
"add w22, w22, w18",
"add w22, w22, w23",
"add w22, w22, w30",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
},
"sha1rnds4 xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 53,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"mov w20, #0xc1d6",
"movk w20, #0xca62, lsl #16",
"mov w21, v17.s[3]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w30, v16.s[0]",
"eor w18, w23, w24",
"eor w18, w18, w30",
"ror w20, w22, #27",
"add w20, w18, w20",
"add w20, w20, w21",
"mov w21, #0xc1d6",
"movk w21, #0xca62, lsl #16",
"add w20, w20, w21",
"ror w23, w23, #2",
"mov w18, v17.s[2]",
"add w30, w18, w30",
"eor w18, w22, w23",
"eor w18, w18, w24",
"ror w21, w20, #27",
"add w21, w18, w21",
"add w21, w21, w30",
"mov w30, #0xc1d6",
"movk w30, #0xca62, lsl #16",
"add w21, w21, w30",
"ror w22, w22, #2",
"mov w18, v17.s[1]",
"add w24, w18, w24",
"eor w18, w20, w22",
"eor w18, w18, w23",
"ror w30, w21, #27",
"add w30, w18, w30",
"add w24, w30, w24",
"mov w30, #0xc1d6",
"movk w30, #0xca62, lsl #16",
"add w24, w24, w30",
"ror w20, w20, #2",
"mov w18, v17.s[0]",
"add w23, w18, w23",
"eor w18, w21, w20",
"eor w22, w18, w22",
"ror w18, w24, #27",
"add w22, w22, w18",
"add w22, w22, w23",
"add w22, w22, w30",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20"
]
}
}
}