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InstcountCI: Update

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Ryan Houdek committed 2025-01-03 13:49:40 -08:00
1 parent a47ed105e7
commit 686294f1c4
26 files changed
+7055 -7136
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unittests/InstructionCountCI/AVX128/VEX_map1.json
+56 -56
View File
@@ -505,7 +505,7 @@
],
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2512]",
"ldr q3, [x28, #2528]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -519,7 +519,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #16]",
"ushr v3.4s, v16.4s, #31",
"ldr q4, [x28, #2512]",
"ldr q4, [x28, #2528]",
"ushl v3.4s, v3.4s, v4.4s",
"addv s3, v3.4s",
"mov w20, v3.s[0]",
@@ -1168,7 +1168,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"str q2, [x28, #16]"
@@ -1181,7 +1181,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"str q2, [x28, #16]"
@@ -1194,7 +1194,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"str q2, [x28, #16]"
@@ -1219,7 +1219,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1233,7 +1233,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1247,7 +1247,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1272,7 +1272,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1285,7 +1285,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1298,7 +1298,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1326,7 +1326,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1340,7 +1340,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1354,7 +1354,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1379,7 +1379,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1392,7 +1392,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1405,7 +1405,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -1433,7 +1433,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1447,7 +1447,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1461,7 +1461,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -2384,7 +2384,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -2399,7 +2399,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2412,7 +2412,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -2427,7 +2427,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q4, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2440,7 +2440,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"movi v2.2d, #0x0",
@@ -2455,7 +2455,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q4, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2732,7 +2732,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2768]",
"ldr s2, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
@@ -2747,7 +2747,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2800]",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
@@ -2762,7 +2762,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2816]",
"ldr d2, [x28, #2832]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
@@ -2777,7 +2777,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2848]",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
@@ -2793,7 +2793,7 @@
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2768]",
"ldr s3, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -2809,7 +2809,7 @@
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2800]",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -2825,7 +2825,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -2841,7 +2841,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -3153,8 +3153,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2768]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2784]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
@@ -3171,8 +3171,8 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"frinti v3.4s, v17.4s",
"ldr q4, [x28, #2864]",
"ldr q5, [x28, #2768]",
"ldr q4, [x28, #2880]",
"ldr q5, [x28, #2784]",
"fcvtzs v6.4s, v3.4s",
"fcmgt v3.4s, v5.4s, v3.4s",
"mov v16.16b, v3.16b",
@@ -3190,8 +3190,8 @@
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2864]",
"ldr q3, [x28, #2768]",
"ldr q2, [x28, #2880]",
"ldr q3, [x28, #2784]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
@@ -3207,8 +3207,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2768]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2784]",
"fcvtzs v5.4s, v17.4s",
"fcmgt v6.4s, v4.4s, v17.4s",
"mov v16.16b, v6.16b",
@@ -3984,7 +3984,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d",
"movi v2.2d, #0x0",
@@ -3999,7 +3999,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #2416]",
"ldr q4, [x28, #2432]",
"eor v5.16b, v18.16b, v4.16b",
"fadd v16.2d, v17.2d, v5.2d",
"eor v3.16b, v3.16b, v4.16b",
@@ -4013,7 +4013,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s",
"movi v2.2d, #0x0",
@@ -4028,7 +4028,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #2384]",
"ldr q4, [x28, #2400]",
"eor v5.16b, v18.16b, v4.16b",
"fadd v16.4s, v17.4s, v5.4s",
"eor v3.16b, v3.16b, v4.16b",
@@ -4204,7 +4204,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2656]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -4220,7 +4220,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #16]",
"ldr q3, [x28, #2640]",
"ldr q3, [x28, #2656]",
"cmlt v4.16b, v16.16b, #0",
"and v4.16b, v4.16b, v3.16b",
"addp v4.16b, v4.16b, v4.16b",
@@ -4726,8 +4726,8 @@
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #2864]",
"ldr q3, [x28, #2816]",
"ldr d2, [x28, #2880]",
"ldr q3, [x28, #2832]",
"frintz v4.2d, v17.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
@@ -4746,8 +4746,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"frintz v5.2d, v17.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
@@ -4797,8 +4797,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr d3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
@@ -4818,8 +4818,8 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"frinti v3.2d, v17.2d",
"ldr q4, [x28, #2864]",
"ldr q5, [x28, #2816]",
"ldr q4, [x28, #2880]",
"ldr q5, [x28, #2832]",
"frintz v6.2d, v3.2d",
"fcvtn v6.2s, v6.2d",
"fcvtzs v6.2s, v6.2s",
unittests/InstructionCountCI/AVX128/VEX_map2.json
+25 -25
View File
@@ -1964,7 +1964,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2352]",
"ldr q2, [x28, #2368]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -4548,7 +4548,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4566,7 +4566,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4582,7 +4582,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4600,7 +4600,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4616,7 +4616,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4634,7 +4634,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4650,7 +4650,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4668,7 +4668,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -5656,7 +5656,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5674,7 +5674,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5690,7 +5690,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5708,7 +5708,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5724,7 +5724,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5742,7 +5742,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5758,7 +5758,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5776,7 +5776,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5792,7 +5792,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5809,7 +5809,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5824,7 +5824,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5841,7 +5841,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5856,7 +5856,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5873,7 +5873,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5888,7 +5888,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5905,7 +5905,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+24 -24
View File
@@ -2850,7 +2850,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2868,7 +2868,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2884,7 +2884,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2902,7 +2902,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2918,7 +2918,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2936,7 +2936,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2952,7 +2952,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2970,7 +2970,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -3938,7 +3938,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3956,7 +3956,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3972,7 +3972,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -3990,7 +3990,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -4006,7 +4006,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -4024,7 +4024,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -4040,7 +4040,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -4058,7 +4058,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -4074,7 +4074,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4091,7 +4091,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2384]",
"ldr q5, [x28, #2400]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4106,7 +4106,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4123,7 +4123,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2416]",
"ldr q5, [x28, #2432]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4138,7 +4138,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4155,7 +4155,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2448]",
"ldr q5, [x28, #2464]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4170,7 +4170,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4187,7 +4187,7 @@
"ldr q2, [x28, #16]",
"ldr q3, [x28, #32]",
"ldr q4, [x28, #48]",
"ldr q5, [x28, #2480]",
"ldr q5, [x28, #2496]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
unittests/InstructionCountCI/AVX128/VEX_map3.json
+38 -38
View File
@@ -343,7 +343,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2544]",
"ldr q2, [x28, #2560]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -355,7 +355,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2560]",
"ldr q2, [x28, #2576]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -378,7 +378,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2592]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -402,7 +402,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2592]",
"ldr q2, [x28, #2608]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -425,7 +425,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2608]",
"ldr q2, [x28, #2624]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -437,7 +437,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2624]",
"ldr q2, [x28, #2640]",
"tbx v16.16b, {v17.16b}, v2.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
@@ -3576,7 +3576,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3591,7 +3591,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3606,7 +3606,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3621,7 +3621,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3636,7 +3636,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3651,7 +3651,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3666,7 +3666,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3681,7 +3681,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3696,7 +3696,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3711,7 +3711,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3726,7 +3726,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3741,7 +3741,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3756,7 +3756,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3771,7 +3771,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3786,7 +3786,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3801,7 +3801,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3816,7 +3816,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3831,7 +3831,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3846,7 +3846,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3861,7 +3861,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3876,7 +3876,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3891,7 +3891,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3906,7 +3906,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3921,7 +3921,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3936,7 +3936,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3951,7 +3951,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3966,7 +3966,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3981,7 +3981,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -3996,7 +3996,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -4011,7 +4011,7 @@
"str x20, [x28, #272]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2296]",
"ldr x0, [x28, #2304]",
"br x0"
]
},
@@ -4022,7 +4022,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #2528]",
"ldr q3, [x28, #2544]",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v3.16b",
@@ -4036,7 +4036,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #2528]",
"ldr q3, [x28, #2544]",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v3.16b",
unittests/InstructionCountCI/Crypto/H0F3A.json
+2 -2
View File
@@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2544]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2544]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/DDD.json
+2 -2
View File
@@ -65,8 +65,8 @@
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #2864]",
"ldr d4, [x28, #2768]",
"ldr d3, [x28, #2880]",
"ldr d4, [x28, #2784]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
unittests/InstructionCountCI/FEXOpt/libnss.json
+3 -3
View File
@@ -198,10 +198,10 @@
"ldr q19, [x11, #272]",
"ldr q24, [x11]",
"ldr q23, [x11, #16]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q2, [x0, #2832]",
"tbl v16.16b, {v18.16b}, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #432]",
"tbl v18.16b, {v19.16b}, v3.16b",
"ldr q22, [x11, #32]",
@@ -285,7 +285,7 @@
"mov v4.s[1], w21",
"mov v20.16b, v4.16b",
"mov v20.s[0], w23",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q4, [x0, #224]",
"tbl v16.16b, {v16.16b}, v4.16b",
"mov w21, v20.s[1]",
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -1608,7 +1608,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #2640]",
"ldr d3, [x28, #2656]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+1 -1
View File
@@ -37,7 +37,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2656]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/FlagM/VEX_map1.json
+1 -1
View File
@@ -68,7 +68,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2656]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+80 -88
View File
@@ -1461,7 +1461,7 @@
},
"Block2": {
"x86InstructionCount": 37,
"ExpectedInstructionCount": 552,
"ExpectedInstructionCount": 544,
"x86Insts": [
"sub esp,0x1c",
"mov edx,dword [esp + 0x20]",
@@ -1534,11 +1534,8 @@
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"mov x20, #0xffffffffffffffff",
"mov w21, #0x7fff",
"fmov d3, x20",
"mov v3.d[1], x21",
"and v2.16b, v2.16b, v3.16b",
"ldr q3, [x28, #2912]",
"bic v2.16b, v2.16b, v3.16b",
"ldr s3, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1567,9 +1564,8 @@
"eor v3.16b, v3.16b, v3.16b",
"mov v3.d[0], x0",
"mov v3.h[4], w1",
"fmov d4, x20",
"mov v4.d[1], x21",
"and v3.16b, v3.16b, v4.16b",
"ldr q4, [x28, #2912]",
"bic v3.16b, v3.16b, v4.16b",
"strb wzr, [x28, #1017]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1598,18 +1594,18 @@
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x16, [sp], #16",
"ldp x17, x30, [sp], #16",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w22, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x22, #62, #nZcv",
"mov w22, #0x1",
"csetm x23, ls",
"dup v4.2d, x23",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w20, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x20, #62, #nZcv",
"mov w20, #0x1",
"csetm x21, ls",
"dup v4.2d, x21",
"bit v2.16b, v3.16b, v4.16b",
"ldr s3, [x5, #4]",
"mrs x0, nzcv",
@@ -1639,9 +1635,8 @@
"eor v3.16b, v3.16b, v3.16b",
"mov v3.d[0], x0",
"mov v3.h[4], w1",
"fmov d4, x20",
"mov v4.d[1], x21",
"and v3.16b, v3.16b, v4.16b",
"ldr q4, [x28, #2912]",
"bic v3.16b, v3.16b, v4.16b",
"ldr s4, [x4, #4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1670,9 +1665,8 @@
"eor v4.16b, v4.16b, v4.16b",
"mov v4.d[0], x0",
"mov v4.h[4], w1",
"fmov d5, x20",
"mov v5.d[1], x21",
"and v4.16b, v4.16b, v5.16b",
"ldr q5, [x28, #2912]",
"bic v4.16b, v4.16b, v5.16b",
"strb wzr, [x28, #1017]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1701,19 +1695,19 @@
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x16, [sp], #16",
"ldp x17, x30, [sp], #16",
"mov x23, x0",
"ubfx x24, x23, #1, #1",
"ubfx x25, x23, #0, #1",
"ubfx x23, x23, #2, #1",
"orr w24, w24, w23",
"orr w23, w25, w23",
"eor x24, x24, #0x1",
"rmif x24, #63, #nzCv",
"rmif x23, #62, #nZcv",
"csetm x23, ls",
"dup v5.2d, x23",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w21, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x21, #62, #nZcv",
"csetm x21, ls",
"dup v5.2d, x21",
"bit v3.16b, v4.16b, v5.16b",
"mov w23, #0x8",
"mov w21, #0x8",
"ldr s4, [x5, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1742,9 +1736,8 @@
"eor v4.16b, v4.16b, v4.16b",
"mov v4.d[0], x0",
"mov v4.h[4], w1",
"fmov d5, x20",
"mov v5.d[1], x21",
"and v4.16b, v4.16b, v5.16b",
"ldr q5, [x28, #2912]",
"bic v4.16b, v4.16b, v5.16b",
"ldr s5, [x4, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1773,9 +1766,8 @@
"eor v5.16b, v5.16b, v5.16b",
"mov v5.d[0], x0",
"mov v5.h[4], w1",
"fmov d6, x20",
"mov v6.d[1], x21",
"and v5.16b, v5.16b, v6.16b",
"ldr q6, [x28, #2912]",
"bic v5.16b, v5.16b, v6.16b",
"strb wzr, [x28, #1017]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -1804,17 +1796,17 @@
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x16, [sp], #16",
"ldp x17, x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x24, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w20, w24, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x20, #62, #nZcv",
"csetm x20, ls",
"dup v6.2d, x20",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w22, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x22, #62, #nZcv",
"csetm x22, ls",
"dup v6.2d, x22",
"bit v4.16b, v5.16b, v6.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@@ -2022,37 +2014,37 @@
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x16, [sp], #16",
"ldp x17, x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x24, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w24, w24, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x24, #62, #nZcv",
"eor w26, w20, #0x1",
"ldrb w20, [x28, #1019]",
"sub w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"eor w26, w22, #0x1",
"ldrb w22, [x28, #1019]",
"sub w22, w22, #0x2 (2)",
"and w22, w22, #0x7",
"strb w22, [x28, #1019]",
"add x0, x28, x22, lsl #4",
"str q3, [x0, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x0, x28, x21, lsl #4",
"add w23, w22, #0x1 (1)",
"and w23, w23, #0x7",
"add x0, x28, x23, lsl #4",
"str q2, [x0, #1040]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"sub w20, w23, w20",
"ldrb w23, [x28, #1298]",
"add w23, w22, #0x6 (6)",
"and w23, w23, #0x7",
"sub w21, w21, w22",
"ldrb w22, [x28, #1298]",
"mov w24, #0x303",
"lsr w20, w24, w20",
"orr w20, w23, w20",
"strb w20, [x28, #1298]",
"ldrb w20, [x28, #1298]",
"lsl w21, w22, w21",
"bic w20, w20, w21",
"lsr w21, w24, w21",
"orr w21, w22, w21",
"strb w21, [x28, #1298]",
"ldrb w21, [x28, #1298]",
"lsl w20, w20, w23",
"bic w20, w21, w20",
"strb w20, [x28, #1298]"
]
},
@@ -3164,7 +3156,7 @@
"lsl w20, w23, w20",
"bic w20, w22, w20",
"strb w20, [x28, #1298]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2344]",
"ubfiz x3, x21, #4, #20",
"add x0, x0, x3",
"ldp x1, x0, [x0]"
@@ -4191,7 +4183,7 @@
"lsl w20, w21, w20",
"bic w20, w23, w20",
"strb w20, [x28, #1298]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2344]",
"ubfiz x3, x22, #4, #20",
"add x0, x0, x3",
"ldp x1, x0, [x0]"
@@ -6334,7 +6326,7 @@
"movk w21, #0x6, lsl #16",
"add w21, w20, w21",
"str w20, [x8, #-4]!",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2344]",
"ubfiz x3, x21, #4, #20",
"add x0, x0, x3",
"ldp x1, x0, [x0]"
@@ -6621,7 +6613,7 @@
"movk w21, #0x6, lsl #16",
"add w21, w20, w21",
"str w20, [x8, #-4]!",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2344]",
"ubfiz x3, x21, #4, #20",
"add x0, x0, x3",
"ldp x1, x0, [x0]"
@@ -6780,7 +6772,7 @@
"movk w21, #0x1, lsl #16",
"add w21, w20, w21",
"str w20, [x8, #-4]!",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2344]",
"ubfiz x3, x21, #4, #20",
"add x0, x0, x3",
"ldp x1, x0, [x0]"
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+5396 -5438
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+1291 -1310
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+13 -19
View File
@@ -4353,7 +4353,7 @@
"ExpectedArm64ASM": []
},
"fchs": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": [
"0xd9 11b 0xe0 /4"
],
@@ -4361,17 +4361,14 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mov w21, #0x0",
"mov w22, #0x8000",
"fmov d3, x21",
"mov v3.d[1], x22",
"ldr q3, [x28, #2912]",
"eor v2.16b, v2.16b, v3.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]"
]
},
"fabs": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": [
"0xd9 11b 0xe1 /4"
],
@@ -4379,11 +4376,8 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x7fff",
"fmov d3, x21",
"mov v3.d[1], x22",
"and v2.16b, v2.16b, v3.16b",
"ldr q3, [x28, #2912]",
"bic v2.16b, v2.16b, v3.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]"
]
@@ -4468,7 +4462,7 @@
"0xd9 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4488,7 +4482,7 @@
"0xd9 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #2704]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4508,7 +4502,7 @@
"0xd9 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2704]",
"ldr q2, [x28, #2720]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4528,7 +4522,7 @@
"0xd9 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2720]",
"ldr q2, [x28, #2736]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4548,7 +4542,7 @@
"0xd9 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2736]",
"ldr q2, [x28, #2752]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4568,7 +4562,7 @@
"0xd9 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2752]",
"ldr q2, [x28, #2768]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4732,7 +4726,7 @@
"mov v2.h[4], w1",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
@@ -5015,7 +5009,7 @@
"0xd9 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q3, [x0, #1040]",
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -655,7 +655,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2352]",
"ldr q2, [x28, #2368]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
unittests/InstructionCountCI/H0F3A.json
+7 -7
View File
@@ -321,7 +321,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2544]",
"ldr q2, [x28, #2560]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -331,7 +331,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2560]",
"ldr q2, [x28, #2576]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -350,7 +350,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2592]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -370,7 +370,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2592]",
"ldr q2, [x28, #2608]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -389,7 +389,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2608]",
"ldr q2, [x28, #2624]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -399,7 +399,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2624]",
"ldr q2, [x28, #2640]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -468,7 +468,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2096]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/PrimaryGroup.json
+4 -4
View File
@@ -2825,7 +2825,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #2928]",
"ldr x3, [x28, #2960]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2836,7 +2836,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #2944]",
"ldr x3, [x28, #2976]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2894,7 +2894,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #2936]",
"ldr x3, [x28, #2968]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2907,7 +2907,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #2952]",
"ldr x3, [x28, #2984]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
unittests/InstructionCountCI/Secondary.json
+16 -16
View File
@@ -174,8 +174,8 @@
"strb wzr, [x28, #1019]",
"mov w20, #0xffff",
"ldr d2, [x4]",
"ldr d3, [x28, #2864]",
"ldr d4, [x28, #2768]",
"ldr d3, [x28, #2880]",
"ldr d4, [x28, #2784]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
@@ -188,8 +188,8 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2864]",
"ldr d3, [x28, #2768]",
"ldr d2, [x28, #2880]",
"ldr d3, [x28, #2784]",
"fcvtzs v4.2s, v16.2s",
"fcmgt v3.4s, v3.4s, v16.4s",
"bit v2.8b, v4.8b, v3.8b",
@@ -204,8 +204,8 @@
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"frinti v2.4s, v2.4s",
"ldr d3, [x28, #2864]",
"ldr d4, [x28, #2768]",
"ldr d3, [x28, #2880]",
"ldr d4, [x28, #2784]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
@@ -219,8 +219,8 @@
"Comment": "0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti v2.4s, v16.4s",
"ldr d3, [x28, #2864]",
"ldr d4, [x28, #2768]",
"ldr d3, [x28, #2880]",
"ldr d4, [x28, #2784]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
@@ -654,7 +654,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2512]",
"ldr q3, [x28, #2528]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -665,7 +665,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2512]",
"ldr q3, [x28, #2528]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -1108,7 +1108,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1056]",
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #1040]",
@@ -1121,7 +1121,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #1040]",
@@ -3400,7 +3400,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
]
@@ -3409,7 +3409,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #16]",
"mov v0.16b, v17.16b",
"mov v1.16b, v16.16b",
@@ -3421,7 +3421,7 @@
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q3, [x0, #16]",
"mov v0.16b, v16.16b",
"mov v1.16b, v2.16b",
@@ -3529,7 +3529,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #2640]",
"ldr d3, [x28, #2656]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/Secondary_OpSize.json
+15 -15
View File
@@ -126,8 +126,8 @@
"ExpectedInstructionCount": 11,
"Comment": "0x66 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2864]",
"ldr q3, [x28, #2816]",
"ldr d2, [x28, #2880]",
"ldr q3, [x28, #2832]",
"frintz v4.2d, v16.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
@@ -144,8 +144,8 @@
"Comment": "0x66 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti v2.2d, v16.2d",
"ldr d3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr d3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
@@ -230,8 +230,8 @@
"Comment": "0x66 0x0f 0x5b",
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2768]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2784]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
@@ -244,8 +244,8 @@
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"frinti v2.4s, v2.4s",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2768]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2784]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
@@ -537,7 +537,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -551,7 +551,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -665,7 +665,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2056]",
"ldr x0, [x28, #2064]",
"ldr q3, [x0, #2480]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -1206,7 +1206,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
@@ -1262,7 +1262,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2656]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -1385,8 +1385,8 @@
"ExpectedInstructionCount": 9,
"Comment": "0x66 0x0f 0xe6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2864]",
"ldr q3, [x28, #2816]",
"ldr d2, [x28, #2880]",
"ldr q3, [x28, #2832]",
"frintz v4.2d, v17.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
unittests/InstructionCountCI/Secondary_REP.json
+12 -12
View File
@@ -116,7 +116,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2768]",
"ldr s2, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
@@ -130,7 +130,7 @@
"ldr s2, [x6]",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2768]",
"ldr s3, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -143,7 +143,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2800]",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
@@ -157,7 +157,7 @@
"ldr d2, [x6]",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2800]",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -171,7 +171,7 @@
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2768]",
"ldr s3, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -186,7 +186,7 @@
"frinti s2, s2",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2768]",
"ldr s3, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -200,7 +200,7 @@
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2800]",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -215,7 +215,7 @@
"frinti s2, s2",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2800]",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -294,8 +294,8 @@
"ExpectedInstructionCount": 6,
"Comment": "0xf3 0x0f 0x5b",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2864]",
"ldr q3, [x28, #2768]",
"ldr q2, [x28, #2880]",
"ldr q3, [x28, #2784]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
@@ -395,7 +395,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -408,7 +408,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2048]",
"ldr x0, [x28, #2056]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+13 -13
View File
@@ -101,7 +101,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2816]",
"ldr d2, [x28, #2832]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
@@ -115,7 +115,7 @@
"ldr d2, [x6]",
"fcvtzs w20, d2",
"mov w21, #0x80000000",
"ldr d3, [x28, #2816]",
"ldr d3, [x28, #2832]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel w4, w20, w21, gt",
@@ -128,7 +128,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2848]",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
@@ -142,7 +142,7 @@
"ldr d2, [x6]",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -156,7 +156,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -171,7 +171,7 @@
"frinti d2, d2",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -185,7 +185,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -200,7 +200,7 @@
"frinti d2, d2",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -332,7 +332,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -345,7 +345,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2040]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -501,7 +501,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
@@ -520,8 +520,8 @@
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr d3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+2 -2
View File
@@ -16,8 +16,8 @@
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr d3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"fcvtzs z5.s, p6/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
"mov v5.8b, v5.8b",
unittests/InstructionCountCI/VEX_map1.json
+24 -24
View File
@@ -2801,7 +2801,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2870,7 +2870,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2939,7 +2939,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2064]",
"ldr x0, [x28, #2072]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -3284,7 +3284,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2768]",
"ldr s2, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
@@ -3299,7 +3299,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2800]",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
@@ -3314,7 +3314,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2816]",
"ldr d2, [x28, #2832]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
@@ -3329,7 +3329,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2848]",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
@@ -3345,7 +3345,7 @@
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2768]",
"ldr s3, [x28, #2784]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -3361,7 +3361,7 @@
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2800]",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -3377,7 +3377,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -3393,7 +3393,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2848]",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -3656,8 +3656,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2864]",
"ldr q4, [x28, #2768]",
"ldr q3, [x28, #2880]",
"ldr q4, [x28, #2784]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
@@ -3691,8 +3691,8 @@
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2864]",
"ldr q3, [x28, #2768]",
"ldr q2, [x28, #2880]",
"ldr q3, [x28, #2784]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
@@ -4440,7 +4440,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@@ -4463,7 +4463,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@@ -4600,7 +4600,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2656]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -4992,8 +4992,8 @@
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #2864]",
"ldr q3, [x28, #2816]",
"ldr d2, [x28, #2880]",
"ldr q3, [x28, #2832]",
"fcvtzs z4.s, p6/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
"mov v4.8b, v4.8b",
@@ -5009,7 +5009,7 @@
"Map 1 0b01 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2864]",
"ldr q2, [x28, #2880]",
"ldr x0, [x28, #2000]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
@@ -5053,8 +5053,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2864]",
"ldr q4, [x28, #2816]",
"ldr d3, [x28, #2880]",
"ldr q4, [x28, #2832]",
"fcvtzs z5.s, p6/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
"mov v5.8b, v5.8b",
@@ -5071,7 +5071,7 @@
],
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #2864]",
"ldr q3, [x28, #2880]",
"ldr x0, [x28, #2000]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
unittests/InstructionCountCI/VEX_map2.json
+13 -13
View File
@@ -1603,7 +1603,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2352]",
"ldr q2, [x28, #2368]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.4s, v16.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -3683,7 +3683,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.2d, v16.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -3709,7 +3709,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.4s, v16.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -3735,7 +3735,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.2d, v16.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -4609,7 +4609,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.4s, v17.4s, v16.4s",
"mov v16.16b, v2.16b"
@@ -4635,7 +4635,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.2d, v17.2d, v16.2d",
"mov v16.16b, v2.16b"
@@ -4661,7 +4661,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.4s, v17.4s, v16.4s",
"mov v16.16b, v2.16b"
@@ -4687,7 +4687,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.2d, v17.2d, v16.2d",
"mov v16.16b, v2.16b"
@@ -4713,7 +4713,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.4s, v17.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -4738,7 +4738,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2416]",
"ldr q2, [x28, #2432]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.2d, v17.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -4763,7 +4763,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2448]",
"ldr q2, [x28, #2464]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.4s, v17.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -4788,7 +4788,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2480]",
"ldr q2, [x28, #2496]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.2d, v17.2d, v18.2d",
"mov v16.16b, v2.16b"
unittests/InstructionCountCI/VEX_map3.json
+2 -2
View File
@@ -5372,7 +5372,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2544]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -5385,7 +5385,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2544]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/x87.json
+13 -19
View File
@@ -4352,7 +4352,7 @@
"ExpectedArm64ASM": []
},
"fchs": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": [
"0xd9 11b 0xe0 /4"
],
@@ -4360,17 +4360,14 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mov w21, #0x0",
"mov w22, #0x8000",
"fmov d3, x21",
"mov v3.d[1], x22",
"ldr q3, [x28, #2912]",
"eor v2.16b, v2.16b, v3.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]"
]
},
"fabs": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": [
"0xd9 11b 0xe1 /4"
],
@@ -4378,11 +4375,8 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x7fff",
"fmov d3, x21",
"mov v3.d[1], x22",
"and v2.16b, v2.16b, v3.16b",
"ldr q3, [x28, #2912]",
"bic v2.16b, v2.16b, v3.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]"
]
@@ -4467,7 +4461,7 @@
"0xd9 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4487,7 +4481,7 @@
"0xd9 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #2704]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4507,7 +4501,7 @@
"0xd9 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2704]",
"ldr q2, [x28, #2720]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4527,7 +4521,7 @@
"0xd9 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2720]",
"ldr q2, [x28, #2736]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4547,7 +4541,7 @@
"0xd9 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2736]",
"ldr q2, [x28, #2752]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4567,7 +4561,7 @@
"0xd9 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2752]",
"ldr q2, [x28, #2768]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
@@ -4731,7 +4725,7 @@
"mov v2.h[4], w1",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
@@ -5014,7 +5008,7 @@
"0xd9 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #2688]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q3, [x0, #1040]",