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x87: complete FXAM implementation
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Justin Becker committed
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@@ -860,22 +860,103 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
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void OpDispatchBuilder::X87FXAM(OpcodeArgs) {
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auto a = _ReadStackValue(0);
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Ref Result =
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ReducedPrecisionMode ? _VExtractToGPR(OpSize::i64Bit, OpSize::i64Bit, a, 0) : _VExtractToGPR(OpSize::i128Bit, OpSize::i64Bit, a, 1);
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Ref Value = ReducedPrecisionMode ? _VExtractToGPR(OpSize::i64Bit, OpSize::i64Bit, a, 0) : _VExtractToGPR(OpSize::i128Bit, OpSize::i64Bit, a, 1);
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// Extract the sign bit
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Result = ReducedPrecisionMode ? _Bfe(OpSize::i64Bit, 1, 63, Result) : _Bfe(OpSize::i64Bit, 1, 15, Result);
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// Extract the sign bit, which goes in C1
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Ref Result = ReducedPrecisionMode ? _Bfe(OpSize::i64Bit, 1, 63, Value) : _Bfe(OpSize::i64Bit, 1, 15, Value);
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SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Result);
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// Claim this is a normal number
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// We don't support anything else
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auto TopValid = _StackValidTag(0);
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auto NotEmpty = _StackValidTag(0);
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Ref IsEmpty = _Xor(OpSize::i64Bit, NotEmpty, Constant(1));
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Ref IsNaN {};
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Ref IsDenormal {};
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Ref IsInf {};
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Ref IsZero {};
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Ref IsUnsupported {};
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Ref NoSignBit {};
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// In the case of top being invalid then C3:C2:C0 is 0b101
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auto C3 = Select01(OpSize::i32Bit, CondClass::NEQ, TopValid, Constant(1));
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// TODO: The codegen for this is not optimal, and can probably be improved
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// if FXAM ends up on the hot path for some workload.
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if (ReducedPrecisionMode) {
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constexpr uint64_t ExponentMask = 0x7FF0'0000'0000'0000ULL;
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NoSignBit = _Bfe(OpSize::i64Bit, 63, 0, Value);
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IsInf = Select01(OpSize::i64Bit, CondClass::EQ, NoSignBit, Constant(ExponentMask));
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IsNaN = Select01(OpSize::i64Bit, CondClass::UGT, NoSignBit, Constant(ExponentMask));
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IsZero = Select01(OpSize::i64Bit, CondClass::EQ, NoSignBit, Constant(0));
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// 64 bit floats can't represent an x87 denormal, nor any of the
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// unsupported encodings.
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IsDenormal = Constant(0);
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IsUnsupported = Constant(0);
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} else {
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Ref Mantissa = _VExtractToGPR(OpSize::i128Bit, OpSize::i64Bit, a, 0);
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// "J" is the name given to the msb of the mantissa in the SDM.
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Ref JBit = _Bfe(OpSize::i64Bit, 1, 63, Mantissa);
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Ref Exponent = _Bfe(OpSize::i64Bit, 15, 0, Value);
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Ref IsExponentZero = Select01(OpSize::i64Bit, CondClass::EQ, Exponent, Constant(0));
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Ref IsExponentMax = Select01(OpSize::i64Bit, CondClass::EQ, Exponent, Constant(0x7FFF));
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// Inf is when mantissa only has the J bit set, exponent is all 1's.
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Ref IsOnlyJBit = Select01(OpSize::i64Bit, CondClass::EQ, Mantissa, Constant(1ULL << 63));
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IsInf = _And(OpSize::i64Bit, IsExponentMax, IsOnlyJBit);
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// NaN is when the low 63 bits of the mantissa are non-zero
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// and exponent is max, and the J bit is set.
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Ref Fraction = _Bfe(OpSize::i64Bit, 63, 0, Mantissa);
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Ref FractionNonZero = Select01(OpSize::i64Bit, CondClass::NEQ, Fraction, Constant(0));
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Ref IsExponentMaxWithJBit = _And(OpSize::i64Bit, IsExponentMax, JBit);
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IsNaN = _And(OpSize::i64Bit, IsExponentMaxWithJBit, FractionNonZero);
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// Zero and Denormal are basically the same as the 64-bit case.
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Ref MantissaNonZero = Select01(OpSize::i64Bit, CondClass::NEQ, Mantissa, Constant(0));
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Ref MantissaZero = _Xor(OpSize::i64Bit, MantissaNonZero, Constant(1));
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IsZero = _And(OpSize::i64Bit, IsExponentZero, MantissaZero);
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IsDenormal = _And(OpSize::i64Bit, IsExponentZero, MantissaNonZero);
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// This is where things are weird. If the J bit is not set
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// and the exponent is non-zero, then this is an "unsupported"
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// encoding, which I believe is left in for legacy reasons.
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Ref IsSupported = _Or(OpSize::i64Bit, IsExponentZero, JBit);
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IsUnsupported = _Xor(OpSize::i64Bit, IsSupported, Constant(1));
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}
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// NormalFiniteNumber = !Zero && !Denormal && !Inf && !NaN && !Empty && !Unsupported
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Ref temp1 = _Or(OpSize::i64Bit, IsZero, IsDenormal);
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Ref temp2 = _Or(OpSize::i64Bit, IsInf, IsNaN);
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Ref temp3 = _Or(OpSize::i64Bit, IsUnsupported, IsEmpty);
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temp1 = _Or(OpSize::i64Bit, temp1, temp2);
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temp2 = _Or(OpSize::i64Bit, temp1, temp3);
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Ref NormalFiniteNumber = _Xor(OpSize::i64Bit, temp2, Constant(1));
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// Set C3, C2, C0 based on the class of the FP value in ST(0)
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// Table is from "FXAM" page in the SDM.
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// +----------------------+----+----+----+
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// | Class | C3 | C2 | C0 |
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// +----------------------+----+----+----+
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// | Unsupported | 0 | 0 | 0 |
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// | NaN | 0 | 0 | 1 |
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// | Normal finite number | 0 | 1 | 0 |
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// | Infinity | 0 | 1 | 1 |
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// | Zero | 1 | 0 | 0 |
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// | Empty | 1 | 0 | 1 |
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// | Denormal number | 1 | 1 | 0 |
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// +----------------------+----+----+----+
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// c0 = IsNaN || IsInf || IsEmpty
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// c2 = (IsInf || Denormal || NormalFiniteNumber) && !IsEmpty
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// c3 = Zero || IsEmpty || Denormal
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Ref C0 = _Or(OpSize::i64Bit, IsNaN, IsInf);
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C0 = _Or(OpSize::i64Bit, C0, IsEmpty);
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Ref C2 = _Or(OpSize::i64Bit, IsInf, IsDenormal);
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C2 = _Or(OpSize::i64Bit, C2, NormalFiniteNumber);
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C2 = _And(OpSize::i64Bit, C2, NotEmpty);
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Ref C3 = _Or(OpSize::i64Bit, IsZero, IsEmpty);
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C3 = _Or(OpSize::i64Bit, C3, IsDenormal);
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auto C2 = TopValid;
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auto C0 = C3; // Mirror C3 until something other than zero is supported
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SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(C0);
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SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(C2);
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SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(C3);
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@@ -1,3 +1,2 @@
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Test_X87/FXAM_Simple.asm
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## Tag bits not completely modelled
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Test_X87/X87MMXInteraction.asm
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@@ -1,13 +1,15 @@
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;; Simpler versions of FXAM_Push* tests.
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;; In hostrunner tests this will fail because we mentioned below there's no support
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;; for the zero flag. In hostrunner RCX should contain 0x4000 instead of 0x400.
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0x6",
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"RBX": "0x0400",
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"RCX": "0x0400",
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"RDX": "0x4100"
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"RCX": "0x4000",
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"RDX": "0x4100",
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"R8": "0x4200440044000700",
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"R9": "0x0100030000000000",
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"R10": "0x0000000004000400",
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"R11": "0x0000050006004400"
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}
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}
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%endif
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@@ -21,15 +23,51 @@ fxam
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fwait
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fnstsw ax
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and ax, 0x4500 ; should be 0x4100 for zero
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and ax, 0x4500 ; should be 0x4100 for empty
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mov edx, eax
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;; Get the C0 - C3 flags and
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;; pack up to 4 results into a GPR
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%macro examine_packed 2
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fld tword [rel %2]
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fxam
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fwait
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fnstsw ax
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and eax, 0x4700
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shl %1, 16
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or %1, rax
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fstp st0
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%endmacro
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xor r8d, r8d
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examine_packed r8, .data_neg_zero
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examine_packed r8, .data_denormal
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examine_packed r8, .data_pseudo_denormal
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examine_packed r8, .data_neg_infinity
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xor r9d, r9d
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examine_packed r9, .data_qnan
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examine_packed r9, .data_neg_snan
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examine_packed r9, .data_unnormal
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examine_packed r9, .data_pseudo_infinity
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xor r10d, r10d
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examine_packed r10, .data_pseudo_nan
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examine_packed r10, .data_pseudo_zero
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examine_packed r10, .data_min_exponent
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examine_packed r10, .data_max_exponent
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xor r11d, r11d
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examine_packed r11, .data_infinity
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examine_packed r11, .data_neg_one
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examine_packed r11, .data_pseudo_denormal_fraction
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fldz
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fxam
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fwait
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fnstsw ax
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and ax, 0x4500 ; should be 0x4000 for zero, but there's no support for it at the moment, so it'll return 0x0400 as it does for a normal number.
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and ax, 0x4500 ; should be 0x4000 for zero
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mov ecx, eax
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fld1
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@@ -47,3 +85,64 @@ and eax, 0x7
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hlt
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align 16
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.data_neg_zero:
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dq 0
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dw 0x8000
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.data_denormal:
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dq 1
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dw 0x0000
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.data_pseudo_denormal:
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dq (1 << 63)
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dw 0x0000
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.data_neg_infinity:
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dq (1 << 63)
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dw 0xFFFF
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.data_qnan:
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dq (11b << 62)
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dw 0x7FFF
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.data_neg_snan:
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dq (10b << 62) | 1
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dw 0xFFFF
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.data_unnormal:
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dq (1 << 62)
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dw 0x3FFF
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.data_pseudo_infinity:
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dq 0
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dw 0x7FFF
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.data_pseudo_nan:
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dq (1 << 62)
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dw 0x7FFF
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.data_pseudo_zero:
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dq 0
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dw 0x3FFF
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.data_min_exponent:
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dq (1 << 63)
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dw 0x0001
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.data_max_exponent:
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dq (1 << 63)
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dw 0x7FFE
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.data_infinity:
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dq (1 << 63)
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dw 0x7FFF
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.data_neg_one:
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dq (1 << 63)
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dw 0xBFFF
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.data_pseudo_denormal_fraction:
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dq (1 << 63) | 1
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dw 0x0000
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