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Merge pull request #5540 from Sonicadvance1/163

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arm64ec: Single instruction optimization in EC map lookup
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LC authored and GitHub committed 2026-06-01 05:41:34 -04:00
2 parents f5fafa5b96 fd3546a999
commit 65b05fa8c1
2 files changed
+4 -6
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FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
+2 -3
View File
@@ -153,9 +153,8 @@ void Dispatcher::EmitDispatcher() {
ldr(TMP1, ARMEmitter::XReg::x18, TEB_PEB_OFFSET);
ldr(TMP1, TMP1, PEB_EC_CODE_BITMAP_OFFSET);
lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 15);
and_(ARMEmitter::Size::i64Bit, TMP2, TMP2, 0x1fffffffffff8);
ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 18);
ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 3);
lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
(void)tbz(TMP1, 0, &l_NotECCode);
Source/Windows/ARM64EC/Module.S
+2 -3
View File
@@ -18,9 +18,8 @@ check_target_ec:
// Check if target is in fact x86 code
ldr x16, [x18, #0x60] // TEB->PEB
ldr x16, [x16, #0x368] // PEB->EcCodeBitMap
lsr x17, x9, #15
and x17, x17, #0x1fffffffffff8
ldr x16, [x16, x17]
lsr x17, x9, #18
ldr x16, [x16, x17, lsl #3]
lsr x17, x9, #12
lsr x16, x16, x17
tbnz x16, #0, ExitFunctionEC