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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2025-05-28 13:53:38 -04:00
1 parent 0fbe69ebcf
commit 656bb928cf
10 files changed
+281 -366
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unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+6 -8
View File
@@ -612,25 +612,23 @@
]
},
"andn eax, ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"bic w4, w7, w6",
"subs w26, w4, #0x0 (0)"
]
},
"andn rax, rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"bic x4, x7, x6",
"subs x26, x4, #0x0 (0)"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/Atomics.json
+28 -28
View File
@@ -80,8 +80,8 @@
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w7, w20, [x4]",
"orr w26, w20, w7",
"cmp w26, #0x0 (0)"
"orr w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock adc byte [rax], cl": {
@@ -312,8 +312,8 @@
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w7, w20, [x4]",
"eor w26, w20, w7",
"cmp w26, #0x0 (0)"
"eor w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock add qword [rax], rcx": {
@@ -619,8 +619,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x100",
"cmp w26, #0x0 (0)"
"orr w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
@@ -629,8 +629,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w26, w21, w20",
"cmp w26, #0x0 (0)"
"orr w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 0x100": {
@@ -639,8 +639,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x100",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock or qword [rax], -2147483647": {
@@ -649,8 +649,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0xffffffff80000001",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock or word [rax], 1": {
@@ -672,8 +672,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmp w26, #0x0 (0)"
"orr w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 1": {
@@ -682,8 +682,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x1",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock adc byte [rax], 1": {
@@ -1423,8 +1423,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x100",
"cmp w26, #0x0 (0)"
"eor w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
@@ -1433,8 +1433,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w20, [x4]",
"mvn w26, w20",
"cmp w26, #0x0 (0)"
"mvn w20, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 0x100": {
@@ -1443,8 +1443,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x100",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor qword [rax], -2147483647": {
@@ -1453,8 +1453,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0xffffffff80000001",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor word [rax], 1": {
@@ -1476,8 +1476,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmp w26, #0x0 (0)"
"eor w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 1": {
@@ -1486,8 +1486,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x1",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock dec byte [rax]": {
unittests/InstructionCountCI/FlagM/Atomics.json
+28 -28
View File
@@ -71,8 +71,8 @@
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w7, w20, [x4]",
"orr w26, w20, w7",
"cmp w26, #0x0 (0)"
"orr w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock adc byte [rax], cl": {
@@ -277,8 +277,8 @@
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w7, w20, [x4]",
"eor w26, w20, w7",
"cmp w26, #0x0 (0)"
"eor w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock add qword [rax], rcx": {
@@ -514,8 +514,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x100",
"cmp w26, #0x0 (0)"
"orr w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
@@ -524,8 +524,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w26, w21, w20",
"cmp w26, #0x0 (0)"
"orr w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 0x100": {
@@ -534,8 +534,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x100",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock or qword [rax], -2147483647": {
@@ -544,8 +544,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0xffffffff80000001",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock or word [rax], 1": {
@@ -565,8 +565,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmp w26, #0x0 (0)"
"orr w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 1": {
@@ -575,8 +575,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x1",
"cmp x26, #0x0 (0)"
"orr x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock adc byte [rax], 1": {
@@ -1232,8 +1232,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x100",
"cmp w26, #0x0 (0)"
"eor w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
@@ -1242,8 +1242,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w20, [x4]",
"mvn w26, w20",
"cmp w26, #0x0 (0)"
"mvn w20, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 0x100": {
@@ -1252,8 +1252,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x100",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor qword [rax], -2147483647": {
@@ -1262,8 +1262,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0xffffffff80000001",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor word [rax], 1": {
@@ -1283,8 +1283,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmp w26, #0x0 (0)"
"eor w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 1": {
@@ -1293,8 +1293,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x1",
"cmp x26, #0x0 (0)"
"eor x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock dec byte [rax]": {
unittests/InstructionCountCI/FlagM/Primary.json
+48 -64
View File
@@ -240,21 +240,19 @@
]
},
"or ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w26, w6, w7",
"cmp w26, #0x0 (0)",
"mov x6, x26"
"orr w6, w6, w7",
"subs w26, w6, #0x0 (0)"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x26, x6, x7",
"cmp x26, #0x0 (0)",
"mov x6, x26"
"orr x6, x6, x7",
"subs x26, x6, #0x0 (0)"
]
},
"db 0x0A, 0xcb": {
@@ -284,27 +282,25 @@
]
},
"db 0x0B, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x0B",
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x7, x26"
"orr w7, w7, w6",
"subs w26, w7, #0x0 (0)"
]
},
"db 0x48, 0x0B, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x0B",
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x7, x26"
"orr x7, x7, x6",
"subs x26, x7, #0x0 (0)"
]
},
"or al, 1": {
@@ -328,21 +324,19 @@
]
},
"or eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"or al, -1": {
@@ -366,23 +360,21 @@
]
},
"or eax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, w20",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, x20",
"subs x26, x4, #0x0 (0)"
]
},
"adc bl, cl": {
@@ -1278,21 +1270,19 @@
]
},
"xor ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w26, w6, w7",
"cmp w26, #0x0 (0)",
"mov x6, x26"
"eor w6, w6, w7",
"subs w26, w6, #0x0 (0)"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x26, x6, x7",
"cmp x26, #0x0 (0)",
"mov x6, x26"
"eor x6, x6, x7",
"subs x26, x6, #0x0 (0)"
]
},
"db 0x32, 0xcb": {
@@ -1322,27 +1312,25 @@
]
},
"db 0x33, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x33",
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x7, x26"
"eor w7, w7, w6",
"subs w26, w7, #0x0 (0)"
]
},
"db 0x48, 0x33, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x33",
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x7, x26"
"eor x7, x7, x6",
"subs x26, x7, #0x0 (0)"
]
},
"xor al, 1": {
@@ -1366,21 +1354,19 @@
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"cmp bl, cl": {
@@ -1414,21 +1400,19 @@
]
},
"xor eax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"mvn w26, w4",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"mvn w4, w4",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"mvn x26, x4",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"mvn x4, x4",
"subs x26, x4, #0x0 (0)"
]
},
"cmp bx, cx": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+48 -64
View File
@@ -269,21 +269,19 @@
]
},
"or eax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x100",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x100",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x100",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x100",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, 256": {
@@ -367,21 +365,19 @@
]
},
"xor eax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x100",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x100",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x100",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x100",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, 256": {
@@ -436,21 +432,19 @@
]
},
"or eax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0xffffff00",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0xffffff00",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0xffffffffffffff00",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0xffffffffffffff00",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, -256": {
@@ -534,21 +528,19 @@
]
},
"xor eax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0xffffff00",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0xffffff00",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0xffffffffffffff00",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0xffffffffffffff00",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, -256": {
@@ -603,21 +595,19 @@
]
},
"or eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, 1": {
@@ -701,21 +691,19 @@
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, 1": {
@@ -768,23 +756,21 @@
]
},
"or eax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, w20",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, x20",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, -1": {
@@ -870,21 +856,19 @@
]
},
"xor eax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mvn w26, w4",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"mvn w4, w4",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mvn x26, x4",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"mvn x4, x4",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, -1": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+6 -8
View File
@@ -345,25 +345,23 @@
]
},
"andn eax, ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"bic w4, w7, w6",
"subs w26, w4, #0x0 (0)"
]
},
"andn rax, rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"bic x4, x7, x6",
"subs x26, x4, #0x0 (0)"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+3 -4
View File
@@ -2607,7 +2607,7 @@
},
"Block10": {
"x86InstructionCount": 125,
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"x86Insts": [
"push esi",
"push ebx",
@@ -2743,9 +2743,8 @@
"ldr w20, [x28, #960]",
"ldr w4, [x20, #20]",
"str w4, [x8, #156]",
"mov w26, #0x0",
"cmp w26, #0x0 (0)",
"mov x4, x26",
"mov w4, #0x0",
"subs w26, w4, #0x0 (0)",
"mov w20, #0x869c",
"movk w20, #0x5, lsl #16",
"add w20, w6, w20",
unittests/InstructionCountCI/Primary.json
+60 -90
View File
@@ -277,21 +277,19 @@
]
},
"or ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w26, w6, w7",
"cmp w26, #0x0 (0)",
"mov x6, x26"
"orr w6, w6, w7",
"subs w26, w6, #0x0 (0)"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x26, x6, x7",
"cmp x26, #0x0 (0)",
"mov x6, x26"
"orr x6, x6, x7",
"subs x26, x6, #0x0 (0)"
]
},
"db 0x0A, 0xcb": {
@@ -325,27 +323,25 @@
]
},
"db 0x0B, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x0B",
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x7, x26"
"orr w7, w7, w6",
"subs w26, w7, #0x0 (0)"
]
},
"db 0x48, 0x0B, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x0B",
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x7, x26"
"orr x7, x7, x6",
"subs x26, x7, #0x0 (0)"
]
},
"or al, 1": {
@@ -373,21 +369,19 @@
]
},
"or eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"or al, -1": {
@@ -415,23 +409,21 @@
]
},
"or eax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, w20",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, x20",
"subs x26, x4, #0x0 (0)"
]
},
"adc bl, cl": {
@@ -1443,21 +1435,19 @@
]
},
"xor ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w26, w6, w7",
"cmp w26, #0x0 (0)",
"mov x6, x26"
"eor w6, w6, w7",
"subs w26, w6, #0x0 (0)"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x26, x6, x7",
"cmp x26, #0x0 (0)",
"mov x6, x26"
"eor x6, x6, x7",
"subs x26, x6, #0x0 (0)"
]
},
"db 0x32, 0xcb": {
@@ -1491,27 +1481,25 @@
]
},
"db 0x33, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x33",
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x7, x26"
"eor w7, w7, w6",
"subs w26, w7, #0x0 (0)"
]
},
"db 0x48, 0x33, 0xcb": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"0x33",
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x7, x26"
"eor x7, x7, x6",
"subs x26, x7, #0x0 (0)"
]
},
"xor al, 1": {
@@ -1539,21 +1527,19 @@
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"cmp bl, cl": {
@@ -1591,21 +1577,19 @@
]
},
"xor eax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"mvn w26, w4",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"mvn w4, w4",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0x35",
"ExpectedArm64ASM": [
"mvn x26, x4",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"mvn x4, x4",
"subs x26, x4, #0x0 (0)"
]
},
"cmp bx, cx": {
@@ -4356,14 +4340,10 @@
]
},
"xor al, al": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w26, #0x0",
"and x4, x4, #0xffffffffffffff00",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w4, w4"
]
},
"mov ah, 0x0": {
@@ -4373,14 +4353,10 @@
]
},
"xor ah, ah": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w26, #0x0",
"and x4, x4, #0xffffffffffff00ff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w4, w4"
]
},
"mov al, 0xff": {
@@ -4426,14 +4402,10 @@
]
},
"xor ax, ax": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w26, #0x0",
"and x4, x4, #0xffffffffffff0000",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w4, w4"
]
},
"mov eax, 0x0": {
@@ -4443,11 +4415,10 @@
]
},
"xor eax, eax": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w26, #0x0",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"mov w4, #0x0",
"subs w26, w4, #0x0 (0)"
]
},
"mov eax, 0xffffffff": {
@@ -4476,12 +4447,11 @@
]
},
"xor rax, rax": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "0xb0",
"ExpectedArm64ASM": [
"mov w26, #0x0",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"mov w4, #0x0",
"subs w26, w4, #0x0 (0)"
]
},
"mov rax, 0xffffffffffffffff": {
unittests/InstructionCountCI/PrimaryGroup.json
+48 -64
View File
@@ -306,21 +306,19 @@
]
},
"or eax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x100",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x100",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x100",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x100",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, 256": {
@@ -416,21 +414,19 @@
]
},
"xor eax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x100",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x100",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x100",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x100",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, 256": {
@@ -491,21 +487,19 @@
]
},
"or eax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0xffffff00",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0xffffff00",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0xffffffffffffff00",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0xffffffffffffff00",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, -256": {
@@ -601,21 +595,19 @@
]
},
"xor eax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0xffffff00",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0xffffff00",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0xffffffffffffff00",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0xffffffffffffff00",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, -256": {
@@ -676,21 +668,19 @@
]
},
"or eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, 1": {
@@ -786,21 +776,19 @@
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"eor w4, w4, #0x1",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"eor x4, x4, #0x1",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, 1": {
@@ -859,23 +847,21 @@
]
},
"or eax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"orr w4, w4, w20",
"subs w26, w4, #0x0 (0)"
]
},
"or rax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"orr x4, x4, x20",
"subs x26, x4, #0x0 (0)"
]
},
"adc eax, -1": {
@@ -973,21 +959,19 @@
]
},
"xor eax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mvn w26, w4",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"mvn w4, w4",
"subs w26, w4, #0x0 (0)"
]
},
"xor rax, -1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mvn x26, x4",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"mvn x4, x4",
"subs x26, x4, #0x0 (0)"
]
},
"cmp eax, -1": {
unittests/InstructionCountCI/VEX_map2.json
+6 -8
View File
@@ -4895,25 +4895,23 @@
]
},
"andn eax, ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
"bic w4, w7, w6",
"subs w26, w4, #0x0 (0)"
]
},
"andn rax, rbx, rcx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
"bic x4, x7, x6",
"subs x26, x4, #0x0 (0)"
]
},
"bzhi eax, ebx, ecx": {