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Merge pull request #5239 from Sonicadvance1/61

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External/vixl: Rebase on upstream
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Ryan Houdek authored and GitHub committed 2026-01-19 13:38:18 -08:00
2 parents 548dfdc26d e000905aca
commit 6536ccf003
5 files changed
+29 -29
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External/vixl
Vendored
+1 -1
Submodule External/vixl updated: ed690c9eca...da1ad9fb02.
FEXCore/unittests/Emitter/ASIMD_Tests.cpp
+4 -4
View File
@@ -2030,18 +2030,18 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Advanced SIMD modified immed
// XXX: MVNI - Shifted immediate
// XXX: BIC
TEST_SINGLE(movi(SubRegSize::i8Bit, QReg::q30, 0xFE), "movi v30.16b, #0xfe");
TEST_SINGLE(movi(SubRegSize::i16Bit, QReg::q30, 0xFE, 0), "movi v30.8h, #0xfe, lsl #0");
TEST_SINGLE(movi(SubRegSize::i16Bit, QReg::q30, 0xFE, 0), "movi v30.8h, #0xfe");
TEST_SINGLE(movi(SubRegSize::i16Bit, QReg::q30, 0xFE, 8), "movi v30.8h, #0xfe, lsl #8");
TEST_SINGLE(movi(SubRegSize::i32Bit, QReg::q30, 0xFE, 0), "movi v30.4s, #0xfe, lsl #0");
TEST_SINGLE(movi(SubRegSize::i32Bit, QReg::q30, 0xFE, 0), "movi v30.4s, #0xfe");
TEST_SINGLE(movi(SubRegSize::i32Bit, QReg::q30, 0xFE, 8), "movi v30.4s, #0xfe, lsl #8");
TEST_SINGLE(movi(SubRegSize::i32Bit, QReg::q30, 0xFE, 16), "movi v30.4s, #0xfe, lsl #16");
TEST_SINGLE(movi(SubRegSize::i32Bit, QReg::q30, 0xFE, 24), "movi v30.4s, #0xfe, lsl #24");
TEST_SINGLE(movi(SubRegSize::i64Bit, QReg::q30, 0xFF00FF), "movi v30.2d, #0xff00ff");
TEST_SINGLE(movi(SubRegSize::i8Bit, DReg::d30, 0xFE), "movi v30.8b, #0xfe");
TEST_SINGLE(movi(SubRegSize::i16Bit, DReg::d30, 0xFE, 0), "movi v30.4h, #0xfe, lsl #0");
TEST_SINGLE(movi(SubRegSize::i16Bit, DReg::d30, 0xFE, 0), "movi v30.4h, #0xfe");
TEST_SINGLE(movi(SubRegSize::i16Bit, DReg::d30, 0xFE, 8), "movi v30.4h, #0xfe, lsl #8");
TEST_SINGLE(movi(SubRegSize::i32Bit, DReg::d30, 0xFE, 0), "movi v30.2s, #0xfe, lsl #0");
TEST_SINGLE(movi(SubRegSize::i32Bit, DReg::d30, 0xFE, 0), "movi v30.2s, #0xfe");
TEST_SINGLE(movi(SubRegSize::i32Bit, DReg::d30, 0xFE, 8), "movi v30.2s, #0xfe, lsl #8");
TEST_SINGLE(movi(SubRegSize::i32Bit, DReg::d30, 0xFE, 16), "movi v30.2s, #0xfe, lsl #16");
TEST_SINGLE(movi(SubRegSize::i32Bit, DReg::d30, 0xFE, 24), "movi v30.2s, #0xfe, lsl #24");
unittests/InstructionCountCI/AVX128/VEX_map2.json
+17 -17
View File
@@ -345,7 +345,7 @@
"smull2 v3.4s, v17.8h, v18.8h",
"sshr v2.4s, v2.4s, #14",
"sshr v3.4s, v3.4s, #14",
"movi v4.4s, #0x1, lsl #0",
"movi v4.4s, #0x1",
"add v2.4s, v2.4s, v4.4s",
"add v3.4s, v3.4s, v4.4s",
"shrn v2.4h, v2.4s, #1",
@@ -367,7 +367,7 @@
"smull2 v5.4s, v17.8h, v18.8h",
"sshr v4.4s, v4.4s, #14",
"sshr v5.4s, v5.4s, #14",
"movi v6.4s, #0x1, lsl #0",
"movi v6.4s, #0x1",
"add v4.4s, v4.4s, v6.4s",
"add v5.4s, v5.4s, v6.4s",
"shrn v4.4h, v4.4s, #1",
@@ -378,7 +378,7 @@
"smull2 v2.4s, v2.8h, v3.8h",
"sshr v4.4s, v4.4s, #14",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"movi v3.4s, #0x1",
"add v4.4s, v4.4s, v3.4s",
"add v2.4s, v2.4s, v3.4s",
"shrn v4.4h, v4.4s, #1",
@@ -392,7 +392,7 @@
"Map 2 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.4s, #0x3, lsl #0",
"movi v2.4s, #0x3",
"and v2.16b, v18.16b, v2.16b",
"trn1 v2.16b, v2.16b, v2.16b",
"trn1 v2.8h, v2.8h, v2.8h",
@@ -413,7 +413,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v4.4s, #0x3, lsl #0",
"movi v4.4s, #0x3",
"and v4.16b, v18.16b, v4.16b",
"trn1 v4.16b, v4.16b, v4.16b",
"trn1 v4.8h, v4.8h, v4.8h",
@@ -423,7 +423,7 @@
"dup v5.4s, w20",
"add v4.16b, v5.16b, v4.16b",
"tbl v16.16b, {v17.16b}, v4.16b",
"movi v4.4s, #0x3, lsl #0",
"movi v4.4s, #0x3",
"and v3.16b, v3.16b, v4.16b",
"trn1 v3.16b, v3.16b, v3.16b",
"trn1 v3.8h, v3.8h, v3.8h",
@@ -640,7 +640,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v4.4s, #0x7, lsl #0",
"movi v4.4s, #0x7",
"mov w20, #0x100",
"movk w20, #0x302, lsl #16",
"dup v5.4s, w20",
@@ -1436,7 +1436,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v4.4s, #0x7, lsl #0",
"movi v4.4s, #0x7",
"mov w20, #0x100",
"movk w20, #0x302, lsl #16",
"dup v5.4s, w20",
@@ -1932,7 +1932,7 @@
"Map 2 0b01 0x45 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"ushl v16.4s, v17.4s, v0.4s",
@@ -1947,11 +1947,11 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"ushl v16.4s, v17.4s, v0.4s",
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v3.4s",
"neg v0.4s, v0.4s",
"ushl v2.4s, v2.4s, v0.4s",
@@ -2002,7 +2002,7 @@
"Map 2 0b01 0x46 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x1f, lsl #0",
"movi v0.4s, #0x1f",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"sshl v16.4s, v17.4s, v0.4s",
@@ -2017,11 +2017,11 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v0.4s, #0x1f, lsl #0",
"movi v0.4s, #0x1f",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"sshl v16.4s, v17.4s, v0.4s",
"movi v0.4s, #0x1f, lsl #0",
"movi v0.4s, #0x1f",
"umin v0.4s, v0.4s, v3.4s",
"neg v0.4s, v0.4s",
"sshl v2.4s, v2.4s, v0.4s",
@@ -2034,7 +2034,7 @@
"Map 2 0b01 0x47 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"ushl v16.4s, v17.4s, v0.4s",
"stp xzr, xzr, [x28, #32]"
@@ -2048,10 +2048,10 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"ushl v16.4s, v17.4s, v0.4s",
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v3.4s",
"ushl v2.4s, v2.4s, v0.4s",
"str q2, [x28, #32]"
unittests/InstructionCountCI/H0F38.json
+2 -2
View File
@@ -350,7 +350,7 @@
"ldr d3, [x28, #1072]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"movi v3.4s, #0x1",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #1056]",
@@ -368,7 +368,7 @@
"smull2 v3.4s, v16.8h, v17.8h",
"sshr v2.4s, v2.4s, #14",
"sshr v3.4s, v3.4s, #14",
"movi v4.4s, #0x1, lsl #0",
"movi v4.4s, #0x1",
"add v2.4s, v2.4s, v4.4s",
"add v3.4s, v3.4s, v4.4s",
"shrn v2.4h, v2.4s, #1",
unittests/InstructionCountCI/VEX_map2.json
+5 -5
View File
@@ -372,7 +372,7 @@
"smull2 v3.4s, v17.8h, v18.8h",
"sshr v2.4s, v2.4s, #14",
"sshr v3.4s, v3.4s, #14",
"movi v4.4s, #0x1, lsl #0",
"movi v4.4s, #0x1",
"add v2.4s, v2.4s, v4.4s",
"add v3.4s, v3.4s, v4.4s",
"shrn v2.4h, v2.4s, #1",
@@ -412,7 +412,7 @@
"Map 2 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.4s, #0x3, lsl #0",
"movi v2.4s, #0x3",
"and v2.16b, v18.16b, v2.16b",
"trn1 v2.16b, v2.16b, v2.16b",
"trn1 v2.8h, v2.8h, v2.8h",
@@ -1617,7 +1617,7 @@
"Map 2 0b01 0x45 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"ushl v16.4s, v17.4s, v0.4s"
@@ -1667,7 +1667,7 @@
"Map 2 0b01 0x46 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x1f, lsl #0",
"movi v0.4s, #0x1f",
"umin v0.4s, v0.4s, v18.4s",
"neg v0.4s, v0.4s",
"sshl v16.4s, v17.4s, v0.4s"
@@ -1691,7 +1691,7 @@
"Map 2 0b01 0x47 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.4s, #0x20, lsl #0",
"movi v0.4s, #0x20",
"umin v0.4s, v0.4s, v18.4s",
"ushl v16.4s, v17.4s, v0.4s"
]