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InstcountCI: Update

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Ryan Houdek committed 2025-10-08 19:33:58 -07:00
1 parent 673e826e46
commit 601dd1d2b5
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unittests/InstructionCountCI/FEXOpt/MultiInst.json
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@@ -154,129 +154,6 @@
"mov w5, w22"
]
},
"inline syscall": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 108,
"Comment": [
"Simple inline syscall check",
"When the syscall number is a known constant that matches host semantics then it can be inlined",
"InstcountCI is setup that it claims to be a 64-bit Linux syscall handler"
],
"x86Insts": [
"mov rax, 0",
"syscall"
],
"ExpectedArm64ASM": [
"mov w4, #0x0",
"mov w20, #0x5",
"movk w20, #0x1, lsl #16",
"str x20, [x28, #24]",
"cset x20, lo",
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w21, w0, w0, lsr #1",
"orr x21, x21, #0xfffffffffffffffe",
"orn x20, x20, x21, ror #62",
"mrs x21, nzcv",
"and x21, x21, #0xc0000000",
"orr x20, x20, x21, lsr #24",
"orr x15, x20, #0x2",
"mov w7, #0x7",
"movk w7, #0x1, lsl #16",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
"stp x18, x30, [x0], #16",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x25, [x28, #1024]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"stp x8, x9, [x28, #320]",
"stp x10, x11, [x28, #336]",
"stp x12, x13, [x28, #352]",
"stp x14, x15, [x28, #368]",
"stp x16, x17, [x28, #384]",
"stp x19, x29, [x28, #400]",
"stp w26, w27, [x28, #16]",
"add x0, x28, #0x1a0 (416)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"mov w0, #0xffff",
"str x0, [x28, #1456]",
"sub sp, sp, #0x40 (64)",
"str x4, [sp]",
"str x11, [sp, #8]",
"str x10, [sp, #16]",
"str x5, [sp, #24]",
"str x14, [sp, #32]",
"str x12, [sp, #40]",
"str x13, [sp, #48]",
"ldr x0, [x28, #1536]",
"ldr x3, [x28, #1544]",
"mov x1, x28",
"mov x2, sp",
"blr x3",
"add sp, sp, #0x40 (64)",
"ldr x25, [x28, #1024]",
"ldr w1, [x28, #1000]",
"msr nzcv, x1",
"add x1, x28, #0x1a0 (416)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x1], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x1], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x1], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldp x8, x9, [x28, #320]",
"ldp x10, x11, [x28, #336]",
"ldp x12, x13, [x28, #352]",
"ldp x14, x15, [x28, #368]",
"ldp x16, x17, [x28, #384]",
"ldp x19, x29, [x28, #400]",
"ldp w26, w27, [x28, #16]",
"str xzr, [x28, #1456]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"mov x4, x0"
]
},
"push ax, bx": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 2,