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OpcodeDispatcher: Handle VPMOVZXWD

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lioncash committed 2022-12-15 17:37:51 +00:00
1 parent b4079cfea3
commit 5c8d40d9be
4 files changed
+37 -1
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+1
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@@ -5965,6 +5965,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>},
{OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>},
{OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>},
{OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>},
{OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VCMPGT, 8>},
{OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSMIN, 1>},
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
Vendored
+2
View File
@@ -2693,6 +2693,8 @@ template
void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs);
template
void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs);
template
void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs);
OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize,
OrderedNode *Src, uint64_t Mode) {
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
Vendored
+1 -1
View File
@@ -308,7 +308,7 @@ void InitializeVEXTables() {
{OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
unittests/ASM/VEX/vpmovzxwd.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"],
"XMM1": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"],
"XMM2": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"],
"XMM3": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"]
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx]
; Memory operands
vpmovzxwd xmm1, [rdx]
vpmovzxwd ymm2, [rdx]
; Register only
vpmovzxwd xmm3, xmm0
vpmovzxwd ymm4, xmm0
hlt
align 32
.data:
dq 0x4142434485868788
dq 0x5152535455565758
dq 0x4142434485868788
dq 0x5152535455565758