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InstcountCI: Add callf/retf
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@@ -4473,6 +4473,45 @@
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"bfxil x4, x20, #0, #8"
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]
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},
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"retf 0x1234": {
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"ExpectedInstructionCount": 15,
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"Comment": "0xca",
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"ExpectedArm64ASM": [
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"mov x20, x8",
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"ldp w21, w22, [x20], #8",
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"mov w23, #0x1234",
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"add x8, x20, x23",
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"strh w22, [x28, #930]",
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"ubfx w20, w22, #2, #1",
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"and w22, w22, #0xfff8",
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"add x0, x28, x20, lsl #3",
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"ldr x20, [x0, #1168]",
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"ldr x20, [x20, w22, uxtw]",
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"lsr x22, x20, #32",
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"and w23, w22, #0xff000000",
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"orr w20, w23, w20, lsr #16",
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"bfi w20, w22, #16, #8",
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"str w20, [x28, #948]"
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]
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},
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"retf": {
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"ExpectedInstructionCount": 12,
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"Comment": "0xcb",
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"ExpectedArm64ASM": [
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"ldp w20, w21, [x8], #8",
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"strh w21, [x28, #930]",
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"ubfx w22, w21, #2, #1",
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"and w21, w21, #0xfff8",
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"add x0, x28, x22, lsl #3",
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"ldr x22, [x0, #1168]",
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"ldr x21, [x22, w21, uxtw]",
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"lsr x22, x21, #32",
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"and w23, w22, #0xff000000",
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"orr w21, w23, w21, lsr #16",
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"bfi w21, w22, #16, #8",
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"str w21, [x28, #948]"
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]
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},
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"cmc": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf5",
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@@ -2973,6 +2973,29 @@
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"strh w4, [x8, #-2]!"
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]
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},
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"call far [rsp]": {
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"ExpectedInstructionCount": 17,
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"Comment": "GROUP5 0xff /3",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"ldrh w21, [x8, #4]",
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"ldrh w22, [x28, #930]",
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"mov w23, #0x4",
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"movk w23, #0x1, lsl #16",
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"stp x23, x22, [x8, #-16]!",
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"strh w21, [x28, #930]",
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"ubfx w22, w21, #2, #1",
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"and w21, w21, #0xfff8",
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"add x0, x28, x22, lsl #3",
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"ldr x22, [x0, #1168]",
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"ldr x21, [x22, w21, uxtw]",
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"lsr x22, x21, #32",
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"and w23, w22, #0xff000000",
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"orr w21, w23, w21, lsr #16",
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"bfi w21, w22, #16, #8",
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"str w21, [x28, #948]"
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]
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},
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"push rax": {
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"ExpectedInstructionCount": 1,
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"Comment": "GROUP4 0xff /6",
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