mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 17:00:19 +02:00
Arm64: Fix bitmask used to match load/store instructions
When multiple threads simultaneously SIGBUS on the same address, one of them will perform the backpatching while the other will detect the backpatched instruction sequence and hence report the SIGBUS as "handled". This typo broke the instruction detection logic: The second thread would assume the source of the SIGBUS was unrelated to TSO emulation and hence report the signal as unhandled (generally triggering program abortion). In practice, this problem did not manifest as FEX does not currently share CodeBuffers between threads.
This commit is contained in:
1 parent
b148cc6ca3
commit
51d355da30
1 file changed
+1
-1
@@ -46,7 +46,7 @@ constexpr uint32_t LDSTREGISTER_MASK = 0b0011'1011'0010'0000'0000'1100'0000'0000
|
||||
constexpr uint32_t LDR_INST = 0b0011'1000'0111'1111'0110'1000'0000'0000;
|
||||
constexpr uint32_t STR_INST = 0b0011'1000'0011'1111'0110'1000'0000'0000;
|
||||
|
||||
constexpr uint32_t LDSTUNSCALED_MASK = 0b0011'1011'0010'0000'0000'1100'0000'0000;
|
||||
constexpr uint32_t LDSTUNSCALED_MASK = 0b0011'1011'1110'0000'0000'1100'0000'0000;
|
||||
constexpr uint32_t LDUR_INST = 0b0011'1000'0100'0000'0000'0000'0000'0000;
|
||||
constexpr uint32_t STUR_INST = 0b0011'1000'0000'0000'0000'0000'0000'0000;
|
||||
|
||||
|
||||
Reference in new issue
Block a user