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Merge pull request #3142 from Sonicadvance1/inline_syscall_fix

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Arm64: Fixes inline syscalls
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Mai authored and GitHub committed 2023-09-23 09:03:49 -04:00
2 parents 72d092e951 28fa0bda31
commit 4e9a114858
1 file changed
+2 -2
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FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp
+2 -2
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@@ -295,13 +295,13 @@ DEF_OP(InlineSyscall) {
// for registers RAX, RBX, and RSI. Which have just been spilled // for registers RAX, RBX, and RSI. Which have just been spilled
// Just load back from the context. Could be slightly smarter but this is fairly uncommon // Just load back from the context. Could be slightly smarter but this is fairly uncommon
if (Reg == ARMEmitter::Reg::r8) { if (Reg == ARMEmitter::Reg::r8) {
ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])); ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP]));
} }
else if (Reg == ARMEmitter::Reg::r4) { else if (Reg == ARMEmitter::Reg::r4) {
ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])); ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX]));
} }
else if (Reg == ARMEmitter::Reg::r5) { else if (Reg == ARMEmitter::Reg::r5) {
ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])); ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RCX]));
} }
else { else {
mov(EmitSize, RegArgs[i].R(), Reg); mov(EmitSize, RegArgs[i].R(), Reg);