From 28fa0bda31c1abde470342c7837caea68a08e3c5 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 23 Sep 2023 02:56:32 -0700 Subject: [PATCH] Arm64: Fixes inline syscalls Ever since we reordered registers in `X86Enums.h` this has silently been broken. This wasn't hit because RCLSE has been broken ever since SRA was added, so inlinesyscalls just weren't ever happening. Quick fix while I think of a way to more strictly correlate these registers so it doesn't happen again. --- FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp index 34d26fe35..0508fef40 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp @@ -295,13 +295,13 @@ DEF_OP(InlineSyscall) { // for registers RAX, RBX, and RSI. Which have just been spilled // Just load back from the context. Could be slightly smarter but this is fairly uncommon if (Reg == ARMEmitter::Reg::r8) { - ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])); + ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])); } else if (Reg == ARMEmitter::Reg::r4) { ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])); } else if (Reg == ARMEmitter::Reg::r5) { - ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])); + ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RCX])); } else { mov(EmitSize, RegArgs[i].R(), Reg);