IR: Implements support for Yield IR op

This is an IR op that produces nor consumes any SSA values, but has side
effects.

Turns in to the pause instruction on x86 and yield instruction on
AArch64.

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp

@@ -176,6 +176,7 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(INVALIDATEFLAGS,        NoOp);
   REGISTER_OP(PROCESSORID,            ProcessorID);
   REGISTER_OP(RDRAND,                 RDRAND);
+  REGISTER_OP(YIELD,                  Yield);
 
   // Move ops
   REGISTER_OP(EXTRACTELEMENTPAIR,     ExtractElementPair);

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -199,6 +199,7 @@ namespace FEXCore::CPU {
   DEF_OP(SetRoundingMode);
   DEF_OP(ProcessorID);
   DEF_OP(RDRAND);
+  DEF_OP(Yield);
 
   ///< Move ops
   DEF_OP(ExtractElementPair);

External/FEXCore/Source/Interface/Core/Interpreter/MiscOps.cpp

@@ -157,6 +157,11 @@ DEF_OP(RDRAND) {
   // Second result is if we managed to read a valid random number or not
   DstPtr[1] = Result == 8 ? 1 : 0;
 }
+
+DEF_OP(Yield) {
+  // Nop implementation
+}
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -330,6 +330,7 @@ private:
   DEF_OP(SetRoundingMode);
   DEF_OP(ProcessorID);
   DEF_OP(RDRAND);
+  DEF_OP(Yield);
 
   ///< Move ops
   DEF_OP(ExtractElementPair);

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -219,6 +219,10 @@ DEF_OP(RDRAND) {
   cset(Dst.second, Condition::ne);
 }
 
+DEF_OP(Yield) {
+  hint(SystemHint::YIELD);
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterMiscHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
@@ -237,6 +241,7 @@ void Arm64JITCore::RegisterMiscHandlers() {
   REGISTER_OP(INVALIDATEFLAGS,   NoOp);
   REGISTER_OP(PROCESSORID,   ProcessorID);
   REGISTER_OP(RDRAND, RDRAND);
+  REGISTER_OP(YIELD, Yield);
 
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -385,6 +385,7 @@ private:
   DEF_OP(SetRoundingMode);
   DEF_OP(ProcessorID);
   DEF_OP(RDRAND);
+  DEF_OP(Yield);
 
   ///< Move ops
   DEF_OP(ExtractElementPair);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -166,6 +166,10 @@ DEF_OP(RDRAND) {
   setc(Dst.second.cvt8());
 }
 
+DEF_OP(Yield) {
+  pause();
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterMiscHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
@@ -184,6 +188,7 @@ void X86JITCore::RegisterMiscHandlers() {
   REGISTER_OP(INVALIDATEFLAGS,   NoOp);
   REGISTER_OP(PROCESSORID,   ProcessorID);
   REGISTER_OP(RDRAND, RDRAND);
+  REGISTER_OP(YIELD, Yield);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/IR/IR.json

@@ -231,6 +231,11 @@
                 ],
         "DestSize": "16",
         "NumElements": "2"
+      },
+      "Yield": {
+        "HasSideEffects": true,
+        "Desc": ["This is a hint instruction that the CPU is likely to do a spin so it might want to pause to help out SMP",
+                 "Can be implemented as a NOP if necessary"]
       }
     },
     "Branch": {