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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2025-03-31 16:09:54 -04:00
1 parent c4f7b27459
commit 4b0e3bff54
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+201 -520
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unittests/InstructionCountCI/AVX128/VEX_map1.json
+63 -159
View File
@@ -2616,127 +2616,83 @@
]
},
"vcvttss2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z s2, s16",
"fcvtzs w4, s2"
]
},
"vcvttss2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z s2, s16",
"fcvtzs x4, s2"
]
},
"vcvttsd2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z d2, d16",
"fcvtzs w4, d2"
]
},
"vcvttsd2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z d2, d16",
"fcvtzs x4, d2"
]
},
"vcvtss2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32x s2, s16",
"fcvtzs w4, s2"
]
},
"vcvtss2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x s2, s16",
"fcvtzs x4, s2"
]
},
"vcvtsd2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"vcvtsd2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"vucomiss xmm0, xmm1": {
@@ -3023,73 +2979,52 @@
]
},
"vcvtps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b",
"frint32x v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s",
"stp xzr, xzr, [x28, #32]"
]
},
"vcvtps2dq ymm0, ymm1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"frinti v3.4s, v17.4s",
"ldr q4, [x28, #2912]",
"ldr q5, [x28, #2816]",
"fcvtzs v6.4s, v3.4s",
"fcmgt v3.4s, v5.4s, v3.4s",
"mov v16.16b, v3.16b",
"bsl v16.16b, v6.16b, v4.16b",
"frinti v2.4s, v2.4s",
"fcvtzs v3.4s, v2.4s",
"fcmgt v2.4s, v5.4s, v2.4s",
"bsl v2.16b, v3.16b, v4.16b",
"frint32x v3.4s, v17.4s",
"fcvtzs v16.4s, v3.4s",
"frint32x v2.4s, v2.4s",
"fcvtzs v2.4s, v2.4s",
"str q2, [x28, #32]"
]
},
"vcvttps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr q3, [x28, #2816]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b",
"frint32z v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s",
"stp xzr, xzr, [x28, #32]"
]
},
"vcvttps2dq ymm0, ymm1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"fcvtzs v5.4s, v17.4s",
"fcmgt v6.4s, v4.4s, v17.4s",
"mov v16.16b, v6.16b",
"bsl v16.16b, v5.16b, v3.16b",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.16b, v5.16b, v3.16b",
"frint32z v3.4s, v17.4s",
"fcvtzs v16.4s, v3.4s",
"frint32z v2.4s, v2.4s",
"fcvtzs v2.4s, v2.4s",
"str q2, [x28, #32]"
]
},
@@ -4544,45 +4479,31 @@
]
},
"vcvttpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr q3, [x28, #2864]",
"frintz v4.2d, v17.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
"fcmgt v3.2d, v3.2d, v17.2d",
"shrn v3.2s, v3.2d, #32",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b",
"frint32z v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d",
"stp xzr, xzr, [x28, #32]"
]
},
"vcvttpd2dq xmm0, ymm1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 9,
"Comment": [
"Map 1 0b01 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"frintz v5.2d, v17.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
"fcmgt v6.2d, v4.2d, v17.2d",
"shrn v6.2s, v6.2d, #32",
"bsl v6.16b, v5.16b, v3.16b",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"bsl v2.16b, v5.16b, v3.16b",
"zip1 v16.2d, v6.2d, v2.2d",
"frint32z v3.2d, v17.2d",
"fcvtzs v3.2d, v3.2d",
"xtn v3.2s, v3.2d",
"frint32z v2.2d, v2.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"zip1 v16.2d, v3.2d, v2.2d",
"stp xzr, xzr, [x28, #32]"
]
},
@@ -4611,47 +4532,30 @@
]
},
"vcvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b",
"frint32x v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d",
"stp xzr, xzr, [x28, #32]"
]
},
"vcvtpd2dq xmm0, ymm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 9,
"Comment": [
"Map 1 0b11 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"frinti v3.2d, v17.2d",
"ldr q4, [x28, #2912]",
"ldr q5, [x28, #2864]",
"frintz v6.2d, v3.2d",
"fcvtn v6.2s, v6.2d",
"fcvtzs v6.2s, v6.2s",
"fcmgt v3.2d, v5.2d, v3.2d",
"shrn v3.2s, v3.2d, #32",
"bsl v3.16b, v6.16b, v4.16b",
"frinti v2.2d, v2.2d",
"frintz v6.2d, v2.2d",
"fcvtn v6.2s, v6.2d",
"fcvtzs v6.2s, v6.2s",
"fcmgt v2.2d, v5.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"bsl v2.16b, v6.16b, v4.16b",
"frint32x v3.2d, v17.2d",
"fcvtzs v3.2d, v3.2d",
"xtn v3.2s, v3.2d",
"frint32x v2.2d, v2.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"zip1 v16.2d, v3.2d, v2.2d",
"stp xzr, xzr, [x28, #32]"
]
unittests/InstructionCountCI/DDD.json
+3 -6
View File
@@ -61,17 +61,14 @@
]
},
"pf2id mm0, mm1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": [
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #2912]",
"ldr d4, [x28, #2816]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
"frint32z v2.4s, v2.4s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+6 -13
View File
@@ -1313,7 +1313,7 @@
},
"Control - random block using cvtss2si 1": {
"x86InstructionCount": 7,
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 13,
"x86Insts": [
"mov rcx,rdx",
"cvttss2si rax,xmm1",
@@ -1325,11 +1325,8 @@
],
"ExpectedArm64ASM": [
"mov x7, x5",
"fcvtzs x20, s17",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"fcmp s2, s17",
"csel x4, x20, x21, gt",
"frint64z s2, s17",
"fcvtzs x4, s2",
"add x4, x4, x7",
"str x4, [x8]",
"ldr s2, [x9]",
@@ -1344,7 +1341,7 @@
},
"Control - random block using cvtss2si 2": {
"x86InstructionCount": 6,
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"x86Insts": [
"movss xmm1,dword [rbp+0x40]",
"roundss xmm1,xmm1,0x1",
@@ -1357,12 +1354,8 @@
"ldr s17, [x9, #64]",
"frintm s0, s17",
"mov v17.s[0], v0.s[0]",
"frinti s2, s17",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"frint32x s2, s17",
"fcvtzs w4, s2",
"str w4, [x29, #180]",
"mov w20, #0x3f800000",
"str w20, [x9, #72]",
unittests/InstructionCountCI/Secondary.json
+13 -27
View File
@@ -170,62 +170,48 @@
]
},
"cvttps2pi mm0, [rax]": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x2c",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"mov w20, #0xffff",
"ldr d2, [x4]",
"ldr d3, [x28, #2912]",
"ldr d4, [x28, #2816]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
"frint32z v2.4s, v2.4s",
"fcvtzs v2.2s, v2.2s",
"strb w20, [x28, #1298]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
]
},
"cvttps2pi mm0, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr d3, [x28, #2816]",
"fcvtzs v4.2s, v16.2s",
"fcmgt v3.4s, v3.4s, v16.4s",
"bsl v3.8b, v4.8b, v2.8b",
"str d3, [x28, #1040]",
"frint32z v2.4s, v16.4s",
"fcvtzs v2.4s, v2.4s",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
]
},
"cvtps2pi mm0, [rax]": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"frinti v2.4s, v2.4s",
"ldr d3, [x28, #2912]",
"ldr d4, [x28, #2816]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
"frint32x v2.4s, v2.4s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
]
},
"cvtps2pi mm0, xmm0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti v2.4s, v16.4s",
"ldr d3, [x28, #2912]",
"ldr d4, [x28, #2816]",
"fcvtzs v5.2s, v2.2s",
"fcmgt v2.4s, v4.4s, v2.4s",
"bsl v2.8b, v5.8b, v3.8b",
"frint32x v2.4s, v16.4s",
"fcvtzs v2.4s, v2.4s",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
unittests/InstructionCountCI/Secondary_OpSize.json
+19 -46
View File
@@ -125,35 +125,24 @@
]
},
"cvttpd2pi mm0, xmm0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 6,
"Comment": "0x66 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr q3, [x28, #2864]",
"frintz v4.2d, v16.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
"fcmgt v3.2d, v3.2d, v16.2d",
"shrn v3.2s, v3.2d, #32",
"bsl v3.8b, v4.8b, v2.8b",
"str d3, [x28, #1040]",
"frint32z v2.2d, v16.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
]
},
"cvtpd2pi mm0, xmm0": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 6,
"Comment": "0x66 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti v2.2d, v16.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"bsl v2.8b, v5.8b, v3.8b",
"frint32x v2.2d, v16.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"str d2, [x28, #1040]",
"mov w20, #0xffff",
"strh w20, [x28, #1048]"
@@ -228,30 +217,20 @@
]
},
"cvtps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": "0x66 0x0f 0x5b",
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b"
"frint32x v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s"
]
},
"cvtps2dq xmm0, [rax]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x5b",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"frinti v2.4s, v2.4s",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b"
"frint32x v2.4s, v2.4s",
"fcvtzs v16.4s, v2.4s"
]
},
"subpd xmm0, xmm1": {
@@ -1419,18 +1398,12 @@
]
},
"cvttpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xe6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr q3, [x28, #2864]",
"frintz v4.2d, v17.2d",
"fcvtn v4.2s, v4.2d",
"fcvtzs v4.2s, v4.2s",
"fcmgt v3.2d, v3.2d, v17.2d",
"shrn v3.2s, v3.2d, #32",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b"
"frint32z v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d"
]
},
"movntdq [rax], xmm0": {
unittests/InstructionCountCI/Secondary_REPNE.json
+28 -79
View File
@@ -98,115 +98,71 @@
]
},
"cvttsd2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z d2, d16",
"fcvtzs w4, d2"
]
},
"cvttsd2si eax, qword [rbx]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"fcvtzs w20, d2",
"mov w21, #0x80000000",
"ldr d3, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z d2, d2",
"fcvtzs w4, d2"
]
},
"cvttsd2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z d2, d16",
"fcvtzs x4, d2"
]
},
"cvttsd2si rax, qword [rbx]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z d2, d2",
"fcvtzs x4, d2"
]
},
"cvtsd2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"cvtsd2si eax, qword [rbx]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"frinti d2, d2",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d2",
"fcvtzs x4, d2"
]
},
"cvtsd2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"cvtsd2si rax, qword [rbx]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"frinti d2, d2",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d2",
"fcvtzs x4, d2"
]
},
"sqrtsd xmm0, xmm1": {
@@ -518,19 +474,12 @@
]
},
"cvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"frintz v5.2d, v2.2d",
"fcvtn v5.2s, v5.2d",
"fcvtzs v5.2s, v5.2s",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b"
"frint32x v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d"
]
},
"lddqu xmm0, [rax]": {
unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+4 -11
View File
@@ -13,19 +13,12 @@
},
"Instructions": {
"cvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"fcvtzs z5.s, p6/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
"mov v5.8b, v5.8b",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"movprfx z16, z5",
"bsl z16.d, z16.d, z3.d, z2.d"
"frint32x v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d"
]
}
}
unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+27 -75
View File
@@ -15,127 +15,79 @@
},
"Instructions": {
"cvttss2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z s2, s16",
"fcvtzs w4, s2"
]
},
"cvttss2si eax, dword [rbx]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr s2, [x6]",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z s2, s2",
"fcvtzs w4, s2"
]
},
"cvttss2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z s2, s16",
"fcvtzs x4, s2"
]
},
"cvttss2si rax, dword [rbx]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z s2, s2",
"fcvtzs x4, s2"
]
},
"cvtss2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32x s2, s16",
"fcvtzs w4, s2"
]
},
"cvtss2si eax, dword [rbx]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr s2, [x6]",
"frinti s2, s2",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32x s2, s2",
"fcvtzs w4, s2"
]
},
"cvtss2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x s2, s16",
"fcvtzs x4, s2"
]
},
"cvtss2si rax, dword [rbx]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x6]",
"frinti s2, s2",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x s2, s2",
"fcvtzs x4, s2"
]
},
"cvttps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x5b",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr q3, [x28, #2816]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b"
"frint32z v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s"
]
}
}
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+38 -104
View File
@@ -16,142 +16,93 @@
},
"Instructions": {
"vcvttss2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z s2, s16",
"fcvtzs w4, s2"
]
},
"vcvttss2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z s2, s16",
"fcvtzs x4, s2"
]
},
"vcvttsd2si eax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2864]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32z d2, d16",
"fcvtzs w4, d2"
]
},
"vcvttsd2si rax, xmm0": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64z d2, d16",
"fcvtzs x4, d2"
]
},
"vcvtss2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
"msr nzcv, x22"
"frint32x s2, s16",
"fcvtzs w4, s2"
]
},
"vcvtss2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x s2, s16",
"fcvtzs x4, s2"
]
},
"vcvtsd2si eax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"vcvtsd2si rax, xmm0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
"msr nzcv, x22"
"frint64x d2, d16",
"fcvtzs x4, d2"
]
},
"vcvtps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b"
"frint32x v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s"
]
},
"vcvtps2dq ymm0, ymm1": {
@@ -176,17 +127,13 @@
]
},
"vcvttps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr q3, [x28, #2816]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b"
"frint32z v2.4s, v17.4s",
"fcvtzs v16.4s, v2.4s"
]
},
"vcvttps2dq ymm0, ymm1": {
@@ -210,20 +157,14 @@
]
},
"vcvttpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr q3, [x28, #2864]",
"fcvtzs z4.s, p6/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
"mov v4.8b, v4.8b",
"fcmgt v3.2d, v3.2d, v17.2d",
"shrn v3.2s, v3.2d, #32",
"mov v16.16b, v3.16b",
"bsl v16.16b, v4.16b, v2.16b"
"frint32z v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d"
]
},
"vcvttpd2dq xmm0, ymm1": {
@@ -250,21 +191,14 @@
]
},
"vcvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"fcvtzs z5.s, p6/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
"mov v5.8b, v5.8b",
"fcmgt v2.2d, v4.2d, v2.2d",
"shrn v2.2s, v2.2d, #32",
"mov v16.16b, v2.16b",
"bsl v16.16b, v5.16b, v3.16b"
"frint32x v2.2d, v17.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v16.2s, v2.2d"
]
},
"vcvtpd2dq xmm0, ymm1": {