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Merge pull request #3075 from Sonicadvance1/optimize_bt_ops

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OpcodeDispatcher: Minor optimization to BT/BTC/BTR/BTS
This commit is contained in:
Mai authored and GitHub committed 2023-09-11 16:05:33 -04:00
2 parents 6fe643d270 e3a00fb2fb
commit 48521a4416
11 files changed
+365 -653
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FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+26 -12
View File
@@ -2918,8 +2918,8 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) {
const uint32_t Size = GetDstBitSize(Op);
const uint32_t Mask = Size - 1;
// Calculate flags early.
CalculateDeferredFlags();
// Deferred flags are invalidated now
InvalidateDeferredFlags();
if (Op->Src[SrcIndex].IsGPR()) {
Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
@@ -2931,7 +2931,9 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) {
}
if (Op->Dest.IsGPR()) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
// When the destination is a GPR, we don't care about garbage in the upper bits.
// Load the full register.
auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags, -1);
OrderedNode *BitSelect{};
if (AlreadyMasked) {
@@ -2965,6 +2967,8 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) {
// Now shift in to the correct bit location
Result = _Lshr(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Result))), Result, BitSelect);
}
// OF/SF/ZF/AF/PF undefined.
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(IR::SizeToOpSize(GetOpSize(Result)), 1, 0, Result));
}
@@ -2977,8 +2981,8 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
const uint32_t Size = GetDstBitSize(Op);
const uint32_t Mask = Size - 1;
// Calculate flags early.
CalculateDeferredFlags();
// Deferred flags are invalidated now
InvalidateDeferredFlags();
if (Op->Src[SrcIndex].IsGPR()) {
Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
@@ -2990,7 +2994,9 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
}
if (Op->Dest.IsGPR()) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
// When the destination is a GPR, we don't care about garbage in the upper bits.
// Load the full register.
auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags, -1);
OrderedNode *BitSelect{};
if (AlreadyMasked) {
@@ -3043,6 +3049,8 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
_StoreMemAutoTSO(GPRClass, 1, MemoryLocation, Value, 1);
}
}
// OF/SF/ZF/AF/PF undefined.
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(IR::SizeToOpSize(GetOpSize(Result)), 1, 0, Result));
}
@@ -3055,8 +3063,8 @@ void OpDispatchBuilder::BTSOp(OpcodeArgs) {
const uint32_t Size = GetDstBitSize(Op);
const uint32_t Mask = Size - 1;
// Calculate flags early.
CalculateDeferredFlags();
// Deferred flags are invalidated now
InvalidateDeferredFlags();
if (Op->Src[SrcIndex].IsGPR()) {
Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
@@ -3068,7 +3076,9 @@ void OpDispatchBuilder::BTSOp(OpcodeArgs) {
}
if (Op->Dest.IsGPR()) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
// When the destination is a GPR, we don't care about garbage in the upper bits.
// Load the full register.
auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags, -1);
OrderedNode *BitSelect{};
if (AlreadyMasked) {
@@ -3117,6 +3127,8 @@ void OpDispatchBuilder::BTSOp(OpcodeArgs) {
_StoreMemAutoTSO(GPRClass, 1, MemoryLocation, Value, 1);
}
}
// OF/SF/ZF/AF/PF undefined.
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(IR::SizeToOpSize(GetOpSize(Result)), 1, 0, Result));
}
@@ -3129,8 +3141,8 @@ void OpDispatchBuilder::BTCOp(OpcodeArgs) {
const uint32_t Size = GetDstBitSize(Op);
const uint32_t Mask = Size - 1;
// Calculate flags early.
CalculateDeferredFlags();
// Deferred flags are invalidated now
InvalidateDeferredFlags();
if (Op->Src[SrcIndex].IsGPR()) {
Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
@@ -3142,7 +3154,9 @@ void OpDispatchBuilder::BTCOp(OpcodeArgs) {
}
if (Op->Dest.IsGPR()) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
// When the destination is a GPR, we don't care about garbage in the upper bits.
// Load the full register.
auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags, -1);
OrderedNode *BitSelect{};
if (AlreadyMasked) {
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+4 -1
View File
@@ -1195,7 +1195,7 @@ private:
flagsOp = SelectionFlag::Nothing;
if (IsNZCV(BitOffset))
SetNZCV(InsertNZCV(GetNZCV(), BitOffset, Value));
SetNZCV(InsertNZCV(PossiblySetNZCVBits ? GetNZCV() : nullptr, BitOffset, Value));
else
_StoreFlag(Value, BitOffset);
}
@@ -1362,6 +1362,9 @@ private:
*/
void InvalidateDeferredFlags() {
CurrentDeferredFlags.Type = FlagsGenerationType::TYPE_NONE;
// No NZCV bits will be set, they are all invalid.
PossiblySetNZCVBits = 0;
}
/**
unittests/InstructionCountCI/H0F38.json
+3 -6
View File
@@ -416,7 +416,7 @@
]
},
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": [
"0x66 0x0f 0x38 0x17"
@@ -436,11 +436,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
unittests/InstructionCountCI/Primary.json
+5 -8
View File
@@ -3202,7 +3202,7 @@
]
},
"popf": {
"ExpectedInstructionCount": 42,
"ExpectedInstructionCount": 39,
"Optimal": "No",
"Comment": "0x9d",
"ExpectedArm64ASM": [
@@ -3211,18 +3211,15 @@
"mov w21, #0x202",
"orr x20, x20, x21",
"ubfx w21, w20, #0, #1",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"lsl x21, x21, #29",
"ubfx w22, w20, #2, #1",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"strb w20, [x28, #708]",
"ubfx w22, w20, #6, #1",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"ubfx w22, w20, #7, #1",
"bfi w21, w22, #31, #1",
"orr w21, w21, w22, lsl #31",
"ubfx w22, w20, #8, #1",
"strb w22, [x28, #712]",
"ubfx w22, w20, #9, #1",
@@ -3230,7 +3227,7 @@
"ubfx w22, w20, #10, #1",
"strb w22, [x28, #714]",
"ubfx w22, w20, #11, #1",
"bfi w21, w22, #28, #1",
"orr w21, w21, w22, lsl #28",
"ubfx w22, w20, #12, #1",
"strb w22, [x28, #716]",
"ubfx w22, w20, #14, #1",
unittests/InstructionCountCI/Primary_32Bit.json
+18 -32
View File
@@ -226,7 +226,7 @@
]
},
"aaa": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "0x37",
"ExpectedArm64ASM": [
@@ -240,14 +240,13 @@
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x2c",
"cbnz x20, #+0x28",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"mov w21, #0x0",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x2c",
@@ -264,7 +263,7 @@
]
},
"aas": {
"ExpectedInstructionCount": 32,
"ExpectedInstructionCount": 31,
"Optimal": "No",
"Comment": "0x3f",
"ExpectedArm64ASM": [
@@ -278,14 +277,13 @@
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x2c",
"cbnz x20, #+0x28",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"mov w21, #0x0",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x30",
@@ -494,7 +492,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0xd4",
"ExpectedArm64ASM": [
@@ -511,20 +509,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aad": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0xd5",
"ExpectedArm64ASM": [
@@ -541,20 +536,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": [
"aam with a different immediate byte base",
@@ -574,20 +566,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": [
"aad with a different immediate byte base",
@@ -606,14 +595,11 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
unittests/InstructionCountCI/Secondary.json
+85 -168
View File
@@ -200,7 +200,7 @@
]
},
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -214,11 +214,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
@@ -1836,24 +1833,20 @@
]
},
"bt ax, bx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1863,32 +1856,25 @@
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1898,30 +1884,24 @@
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1930,10 +1910,7 @@
"ldrb w21, [x4, x21, sxtx]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2319,28 +2296,24 @@
]
},
"bts ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"orr x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2354,36 +2327,29 @@
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"orr x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2397,15 +2363,12 @@
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2415,15 +2378,12 @@
"lsl x20, x22, x20",
"orr x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2436,10 +2396,7 @@
"orr x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2723,28 +2680,24 @@
]
},
"btr ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"bic x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2758,36 +2711,29 @@
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"bic x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2801,15 +2747,12 @@
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2819,15 +2762,12 @@
"lsl x20, x22, x20",
"bic x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2840,10 +2780,7 @@
"bic x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2930,28 +2867,24 @@
]
},
"btc ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"eor x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -2965,36 +2898,29 @@
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"eor x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3008,15 +2934,12 @@
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3026,15 +2949,12 @@
"lsl x20, x22, x20",
"eor x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3047,10 +2967,7 @@
"eor x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/SecondaryGroup.json
+104 -186
View File
@@ -22,375 +22,293 @@
]
},
"bt ax, 0": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"str w20, [x28, #728]"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"str w20, [x28, #728]"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt ax, 15": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w20, w20, #15",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, 31": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w20, w20, #31",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, 63": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"orr x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"orr x21, x20, #0x1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"orr x4, x20, #0x1",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"orr x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"orr x21, x4, #0x8000",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"orr x20, x20, #0x80000000",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"orr x21, x4, #0x80000000",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"orr x4, x4, #0x8000000000000000",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"and x21, x20, #0xfffffffffffffffe",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"and x21, x20, #0xfffffffffffffffe",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov x20, x4",
"and x4, x20, #0xfffffffffffffffe",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"and x20, x20, #0xffffffffffff7fff",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"and x21, x4, #0xffffffffffff7fff",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"and x20, x20, #0xffffffff7fffffff",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"and x21, x4, #0xffffffff7fffffff",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"and x4, x4, #0x7fffffffffffffff",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"eor x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"eor x21, x20, #0x1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"eor x4, x20, #0x1",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"eor x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"eor x21, x4, #0x8000",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"eor x20, x20, #0x80000000",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"eor x21, x4, #0x80000000",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"eor x4, x4, #0x8000000000000000",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/Secondary_OpSize.json
+3 -6
View File
@@ -145,7 +145,7 @@
]
},
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -159,11 +159,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
unittests/InstructionCountCI/VEX_map1.json
+3 -6
View File
@@ -3779,7 +3779,7 @@
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x2e 128-bit"
@@ -3797,11 +3797,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
unittests/InstructionCountCI/VEX_map2.json
+18 -36
View File
@@ -593,7 +593,7 @@
]
},
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 128-bit"
@@ -619,11 +619,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -632,7 +629,7 @@
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 35,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 256-bit"
@@ -666,11 +663,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -679,7 +673,7 @@
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 128-bit"
@@ -705,11 +699,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -718,7 +709,7 @@
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 35,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 256-bit"
@@ -752,11 +743,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -803,7 +791,7 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 128-bit"
@@ -825,11 +813,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -838,7 +823,7 @@
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 34,
"ExpectedInstructionCount": 31,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 256-bit"
@@ -868,11 +853,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
unittests/InstructionCountCI/x87.json
+96 -192
View File
@@ -10335,7 +10335,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe8 /5"
@@ -10396,18 +10396,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe9 /5"
@@ -10468,18 +10465,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xea /5"
@@ -10540,18 +10534,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xeb /5"
@@ -10612,18 +10603,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xec /5"
@@ -10684,18 +10672,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xed /5"
@@ -10756,18 +10741,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xee /5"
@@ -10828,18 +10810,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xef /5"
@@ -10900,18 +10879,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf0 /6"
@@ -10972,18 +10948,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf1 /6"
@@ -11044,18 +11017,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf2 /6"
@@ -11116,18 +11086,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf3 /6"
@@ -11188,18 +11155,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf4 /6"
@@ -11260,18 +11224,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf5 /6"
@@ -11332,18 +11293,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf6 /6"
@@ -11404,18 +11362,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf7 /6"
@@ -11476,11 +11431,8 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
@@ -22411,7 +22363,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe8 /5"
@@ -22472,11 +22424,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22491,7 +22440,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe9 /5"
@@ -22553,11 +22502,8 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"ldr w25, [x28, #728]",
"mov w0, w25",
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
@@ -22571,7 +22517,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xea /5"
@@ -22632,11 +22578,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22651,7 +22594,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xeb /5"
@@ -22712,11 +22655,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22731,7 +22671,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xec /5"
@@ -22792,11 +22732,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22811,7 +22748,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xed /5"
@@ -22872,11 +22809,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22891,7 +22825,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xee /5"
@@ -22952,11 +22886,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22971,7 +22902,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xef /5"
@@ -23032,11 +22963,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23051,7 +22979,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf0 /6"
@@ -23112,11 +23040,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23131,7 +23056,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf1 /6"
@@ -23193,11 +23118,8 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"ldr w25, [x28, #728]",
"mov w0, w25",
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
@@ -23211,7 +23133,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf2 /6"
@@ -23272,11 +23194,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23291,7 +23210,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf3 /6"
@@ -23352,11 +23271,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23371,7 +23287,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf4 /6"
@@ -23432,11 +23348,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23451,7 +23364,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf5 /6"
@@ -23512,11 +23425,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23531,7 +23441,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf6 /6"
@@ -23592,11 +23502,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23611,7 +23518,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf7 /6"
@@ -23672,11 +23579,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",