Merge pull request #3988 from alyssarosenzweig/opt/idea

Optimize `adc x, 0`

FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -115,6 +115,21 @@ DEF_OP(AdcWithFlags) {
   adcs(ConvertSize48(IROp), GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
 }
 
+DEF_OP(AdcZeroWithFlags) {
+  auto Op = IROp->C<IR::IROp_AdcZeroWithFlags>();
+  auto Size = ConvertSize48(IROp);
+
+  cset(Size, TMP1, ARMEmitter::Condition::CC_CC);
+  adds(Size, GetReg(Node), GetReg(Op->Src1.ID()), TMP1);
+}
+
+DEF_OP(AdcZero) {
+  auto Op = IROp->C<IR::IROp_AdcZero>();
+  auto Size = ConvertSize48(IROp);
+
+  cinc(Size, GetReg(Node), GetReg(Op->Src1.ID()), ARMEmitter::Condition::CC_CC);
+}
+
 DEF_OP(Adc) {
   auto Op = IROp->C<IR::IROp_Adc>();
 

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -302,7 +302,18 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs) {
     Before = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = true});
   }
 
-  Ref Result = CalculateFlags_ADC(Size, Before, Src);
+  Ref Result;
+  if (!DestIsLockedMem(Op) && Op->Src[SrcIndex].IsLiteral() && Op->Src[SrcIndex].Literal() == 0 && Size >= 4) {
+    HandleNZCV_RMW();
+    RectifyCarryInvert(true);
+    Result = _AdcZeroWithFlags(OpSize, Before);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(Before);
+    CalculatePF(Result);
+    CFInverted = false;
+  } else {
+    Result = CalculateFlags_ADC(Size, Before, Src);
+  }
+
   if (!DestIsLockedMem(Op)) {
     StoreResult(GPRClass, Op, Result, -1);
   }

FEXCore/Source/Interface/IR/IR.json

@@ -1171,6 +1171,21 @@
           "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
         ]
       },
+      "GPR = AdcZero OpSize:#Size, GPR:$Src1": {
+        "Desc": ["Adds GPR with inverted carry-in"],
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
+      "GPR = AdcZeroWithFlags OpSize:#Size, GPR:$Src1": {
+        "Desc": ["Adds and set NZCV for the sum of GPR and inverted carry-in given as NZCV"],
+        "HasSideEffects": true,
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
       "GPR = SbbWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
         "Desc": ["Subtracts and set NZCV for the difference of two GPRs and carry-in given as NZCV"],
         "HasSideEffects": true,

FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp

@@ -144,6 +144,14 @@ FlagInfo DeadFlagCalculationEliminination::Classify(IROp_Header* IROp) {
       .ReplacementNoWrite = OP_ADCNZCV,
     };
 
+  case OP_ADCZEROWITHFLAGS:
+    return {
+      .Read = FLAG_C,
+      .Write = FLAG_NZCV,
+      .CanReplace = true,
+      .Replacement = OP_ADCZERO,
+    };
+
   case OP_SBBWITHFLAGS:
     return {
       .Read = FLAG_C,

unittests/InstructionCountCI/FlagM/HotBlocks.json

@@ -596,6 +596,103 @@
         "subs x26, x10, x12"
       ]
     },
+    "bytemark idea 1": {
+      "x86InstructionCount": 8,
+      "ExpectedInstructionCount": 12,
+      "x86Insts": [
+        "movzx  eax,ax",
+        "imul   r8d,eax",
+        "mov    eax,r8d",
+        "shr    eax,0x10",
+        "movzx  r9d,r8w",
+        "sub    r8d,eax",
+        "cmp    r9d,eax",
+        "adc    r8d,0x0"
+      ],
+      "ExpectedArm64ASM": [
+        "uxth w4, w4",
+        "mul w12, w12, w4",
+        "mov w4, w12",
+        "lsr w4, w4, #16",
+        "uxth w13, w12",
+        "sub w12, w12, w4",
+        "cmp w13, w4",
+        "cset w0, lo",
+        "adds w26, w12, w0",
+        "cfinv",
+        "mov x27, x12",
+        "mov x12, x26"
+      ]
+    },
+    "bytemark idea 2": {
+      "x86InstructionCount": 12,
+      "ExpectedInstructionCount": 16,
+      "x86Insts": [
+        "movzx  eax,ax",
+        "imul   r10d,eax",
+        "mov    eax,r10d",
+        "shr    eax,0x10",
+        "movzx  esi,r10w",
+        "sub    r10d,eax",
+        "cmp    esi,eax",
+        "adc    r10d,0x0",
+        "mov    eax,r10d",
+        "mov    esi,r9d",
+        "xor    si,di",
+        "movzx  r10d,word [rsp+r8*1+0x158]"
+      ],
+      "ExpectedArm64ASM": [
+        "uxth w4, w4",
+        "mul w14, w14, w4",
+        "mov w4, w14",
+        "lsr w4, w4, #16",
+        "uxth w10, w14",
+        "sub w14, w14, w4",
+        "cmp w10, w4",
+        "cinc w14, w14, lo",
+        "mov w4, w14",
+        "mov w10, w13",
+        "eor w26, w10, w11",
+        "cmn wzr, w26, lsl #16",
+        "bfxil x10, x26, #0, #16",
+        "add x20, x8, x12",
+        "ldrh w14, [x20, #344]",
+        "cfinv"
+      ]
+    },
+    "bytemark idea 3": {
+      "x86InstructionCount": 11,
+      "ExpectedInstructionCount": 14,
+      "x86Insts": [
+        "movzx  eax,si",
+        "imul   r8d,eax",
+        "mov    eax,r8d",
+        "shr    eax,0x10",
+        "movzx  esi,r8w",
+        "sub    r8d,eax",
+        "cmp    esi,eax",
+        "adc    r8d,0x0",
+        "mov    esi,r8d",
+        "movzx  r8d,word [rsp+rdi*1+0x66]",
+        "test   dx,dx"
+      ],
+      "ExpectedArm64ASM": [
+        "uxth w4, w10",
+        "mul w12, w12, w4",
+        "mov w4, w12",
+        "lsr w4, w4, #16",
+        "uxth w10, w12",
+        "sub w12, w12, w4",
+        "cmp w10, w4",
+        "cinc w12, w12, lo",
+        "mov w10, w12",
+        "add x20, x8, x11",
+        "ldrh w12, [x20, #102]",
+        "cmn wzr, w5, lsl #16",
+        "cfinv",
+        "mov x26, x5"
+      ]
+    },
     "pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
       "ExpectedInstructionCount": 41,
       "Comment": [